JPH03187577A - Digital television receiver - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a digital television receiver that performs baseband video signal processing digitally, and is particularly characterized by its horizontal synchronization signal generation circuit. .

[Technical Background of the Invention and Problems Therewith] When processing television signals, it is important to follow the synchronization signals included in the broadcast signal and to separate the synchronization signals with high accuracy.

When digitally processing baseband video signals,
In particular, the accuracy of the synchronization signal is required, and if the position of the synchronization signal is inaccurate, a large time lag in the digital signal will occur, causing deterioration in image quality.

[Object of the Invention] Therefore, an object of the present invention is to provide a digital television receiver that can obtain horizontal synchronization signals with accuracy and stability, especially in a circuit that processes digital video signals. be.

[Summary of the Invention] According to the present invention, in a digital television receiver that performs signal processing after digitizing a video signal, means for detecting a horizontal synchronization signal from the digital video signal detects a composite synchronization signal from the digital video signal. a first horizontal synchronization detection signal that starts counting at the leading edge of each pulse of the composite synchronization signal separated by the means and deviates from each pulse each time the count value reaches a predetermined value; generating means, and said first generating means generated by said means.
and means for selecting and outputting a signal that is continuously generated at a predetermined period from among the horizontal synchronizing signals as the second horizontal synchronizing signal.

[Effects of the Invention] According to the present invention, a composite synchronizing signal is separated from a digital video signal, counting is started from the leading edge of each pulse of the composite synchronizing signal, and each time the count value reaches a predetermined value, the pulse is shifted from the pulse. A first horizontal synchronization detection signal is generated, and a signal that is continuously generated at a predetermined period from among the first horizontal synchronization signals is selected and output as a second horizontal synchronization signal.

Therefore, the first horizontal synchronization signal is generated with a shift from each pulse of the composite quantity JJA fH signal, so even if disturbances such as noise are mixed into each pulse, it will not be affected by this. It is possible to obtain a stable second horizontal synchronization signal. Moreover, since the second horizontal synchronization signal is also selected from among the first horizontal synchronization signals with continuous periods, an accurate horizontal synchronization signal can be obtained.

[Embodiment of the Invention] FIG. 1 shows blocks of essential parts of a digital TV receiver according to an embodiment of the invention. In the figure, an AC-coupled analog video signal 1 is input to a buffer circuit 2 . The output 3 of the buffer circuit 2 is guided to a low pass filter (LPF) 4 for band limiting. The cutoff frequency of LPF4 is 5.5 MHz because this system is shared by NTSCSPAL. The band-limited video signal output is input to a buffer amplifier circuit 8.

The buffer amplifier circuit 8 receives the analog video signal 1 at IV,
, the input signal 9 of the converter (ADC) l in the subsequent stage
is adjusted so that it becomes approximately 2V P + P.

The ADC 10 uses the input signal 9 as a sampling clock (φ8
) 12 and quantized to, for example, 8 bits and output. The sampling clock (φ5) 120 frequency f8 is fs”'fsc (f8c=color subcarrier frequency).

φsI2 is guided to the digital circuit section lz.

An 8-bit digitized video signal 11 (hereinafter referred to as a DVS signal) synchronized with φsI2 is also led to the digital circuit section 72 in the same manner. All blocks in the DigiMole circuit section IZ are composed of digital circuits. The DVS signal 11 is guided to a synchronization detection/timing generation circuit 27.

The synchronization detection/timing generation circuit 27 detects synchronization/P pulse from the DVS signal 11 and generates various timing signals 28, 29, 30° 31 + 3 according to the synchronous pulse detection signal.
Generates 2.

The pedestal clamp circuit 19 is a circuit for direct current reproduction of the video signal 1, and according to the timing signal 32, 9D
The pedestal level of the VS signal 11 is detected, and a control signal 20 is outputted so that the pedestal level becomes a predetermined value. The output 20 of the flag circuit 19 is connected to a D/A converter (D
AC),? J and converted into an analog signal. The output 22 of the DAC 2 is superimposed on the input of the buffer amplifier circuit 8 as a flag voltage via a resistor, and its DC
Control levels.

Timing signal 31 tit PLL (Phase
LockedLoop) This is a timing signal necessary for the control circuit 23. The PLL control circuit 23 is a circuit for controlling the frequency and phase of the sampling clock (φ5) 12. That is, ADC 10 - synchronization detection/timing generation circuit 27 - pI, I, mIJ control circuit 23 - 1) AC
PLI in the loop of 16~VCXO13~ADC10.

forming a circuit. In this embodiment, basically NTS
For C input, one of the phases of φ812 matches the I axis, and for PAL input, set the PL so that it matches the U axis.
L is applied.

NTSC and PAL input switching information is signal 15 (hereinafter referred to as N
(referred to as the TSC/PAL switching signal).

The control signal output 24 of the PLL control circuit 23 is guided to the DAC 16 and converted into an analog signal 14.

This analog control signal 14 is a voltage-controlled crystal oscillator (V
CXO) I3, which applies the sampling clock φ12 to the output of the VCXO13. VCXO
13 (D crystal oscillator uses NTSC/PAL conversion signal 15
It is possible to obtain a predetermined value of φ8. The principle of the PLL control system of this embodiment is described in US Pat. No. 4,291,332.

In FIG. 1, control data 17 is digital data for controlling the digital 'rV receiver, and is obtained from, for example, a remote control receiving circuit (not shown). The control data 17 is sent to the decoder 47 as #)f'' code,
Control each part. This decoded control signal consists of a color saturation button and contrast/light control signal 48 and a hue control signal 49. The hue control signal 49 controls the hue by changing the phase of the sampling clock φ812 via the PLL control circuit 23. PLL
The control circuit 23 also includes a horizontal fly-off error signal (hereinafter f).
HFI signal) 18 is input! +, well-known nosol identification when PAL input) (PAL Ident
) signal (hereinafter referred to as pH signal) 25 is generated.

The timing signal output 29 of the synchronization detection/timing generation circuit 27 is guided to the horizontal countdown circuit 32. The horizontal countdown circuit 32 performs horizontal synchronization playback from the timing signal 29 using the -''IIFII signal 18, and outputs the horizontal drive signal (foo out) s4.The horizontal countdown circuit 32 also uses the sampling clock (φ8) 12 and Determine the relationship with the horizontal synchronizing signal, and in the case of NTSC signal input, φs #910 /H (fH
;Horizontal frequency) I to S, for PAL φ8#113
Horizontal synchronization standard mode (HMOD) signal 3 when 5fH
Outputs 5.

Timing output 3 of synchronization detection/timing generation circuit 27
0 and the output 33 of the horizontal countdown circuit 32 are led to a vertical countdown circuit 36 that performs vertical synchronization playback. Vertical countdown circuit 36 outputs a regenerated vertical synchronization signal (fvDout) 37.

fII. The out signal 34 is amplified by a driver circuit (H driver buffer 50) and then guided to a horizontal deflection system (not shown) via a signal line 51.

On the other hand, the fvDout signal 37 is guided to a V rung 41 circuit 52 including a vertical rung generation and vertical hide control circuit, and its output 53 is guided to a vertical deflection system (not shown).

1) The vS signal 11 is also a luminance signal (■) and a chromaticity signal (C)
The signal is guided to a Y-C separation circuit 38 that separates the signal.

The Y-C separation circuit 38 includes a separation circuit that performs Y-○ separation using vertical correlation (known as a comb filter), and a separation circuit that uses horizontal sample points without using vertical correlation and performs only horizontal correlation. It has a separation circuit (well known as a bandpass filter) that constitutes a filter, and the separation circuit is selected by the HMOD signal 35. That is, HMOD =
When "1", Y-○ separation is performed with a comb filter, and HMo
When D=゛'0'', use Pantono J?S filter to Y
- Configured to perform separation. An NTSC/PAL switching signal is led to the y-c separation circuit 38, and the horizontal delay amount is switched in accordance with this switching signal. This delay amount #'1 NTSC is 910 bits,
delay, which is 1135 bit delay in PAL (known as IH delay line).

Separated color signal (C signal) 39, color demodulation reference phase (φc) 26, PID signal 25, control signal 48, burst flux IIFP
X8 is led to color processing circuit 4111C. Color process circuit 41 is automatic color saturation control (ACC)
circuit, color killer circuit, and 2-axis synchronous detection using φC26 as the reference color signal (I, NTSC).
Q signal, U in PAL.

(2) A color demodulation circuit that demodulates the signal).

Control signal 48 input to color gloss circuit 41
controls the ACC circuit and controls color saturation, that is, color density. The output 42 of the color process circuit 4 is a demodulating crab/+u.

LeN is obtained.

Luminance signal (Y' signal) separated by y-c separation circuit 38
40 is led to a Y gross process circuit 43. The other input of the Y gloss circuit 43 is a control data signal 48, and brightness and contrast are controlled by this signal. This Y gross circuit 43 is connected to Bright 1. It consists of a contrast control circuit and a circuit (6) for obtaining horizontal and vertical contour correction signals, and outputs a controlled or corrected Y signal 44.

The color demodulation signal 42 and the Y signal 44 are led to an RGB matrix circuit 45, and are converted into three primary colors R by predetermined matrix and matrix calculations.
, G, and B signals 46.

The R, G, and B signals 46 are converted back into analog signals by the DAC 54. DAC54 is R,G.

It is composed of three 8-bit DACs for B, and its output 55 is led to a buffer amplifier 56.

The buffer amplifier 56 amplifies the input signal into R and G signals.

The outputs 57, 58, 59 of B are routed to a color output circuit (not shown). The color output circuit is connected to CRT 60.

Next, the specific configuration of the main parts in FIG. 1 will be explained in detail.

First, the WS2 diagram is a diagram for explaining notation regarding the detailed explanation below. In the following explanation, positive logic will be used.

FIG. 2(,) shows an adder. This shows that the A input cuff 0 is made up of N bits, and the B input cuff 1 is made up of M bits, G, while the A+B output cuff 3 is L bits and G. Co7
2 indicates the carry force added to the lowest bit.

As shown in (,), the signal consisting of multiple bits is M・M
b, 1. It will be expressed as ti.

The figure (b) shows a subtracter. The A input cuff 5 and the B input cuff 7 are added together by an adder 78 to form the AB output cuff 6.

As shown in the figure, the input to be subtracted from among the inputs of the adder 780 is given a minus sign.

FIG. 3(c) shows an N-bit latch circuit.

The input 80 is led to the input circuit 83 and is latched at the rising edge of the clock signal 83, resulting in an output 84. Signal 8 in the diagram
2 indicates the input to the reset terminal R, and when the signal 82 is 1'', the latch output 84 is all IT ON. Also, the signal 81 in the figure indicates the input to the reset terminal Pr, and this signal 8 is 1n, the output 84 becomes all "'1".

Figure (d) shows a shift register. Signal 85 indicates input, signal 86 indicates shift clock (φ), signal 8
8 is the output. The signal 87 is generated by manual input from the reset terminal, and when this signal is 1'', the output 88 becomes all 0''.

FIG. 4(e) shows a synchronous M-bit quanta.

The input clock is 90, the clock synchronous reset signal is 91, and the output is 92.

In the figure, N indicates a counter number, and j=1 to M indicate M counter stages. button, clock 90
For counters having an asynchronous reset terminal, the reset terminal is written as R.

FIG. 2(f) shows a clock synchronous type presettable counter. That is, 96 indicates preset data input;
95 indicates a preset timing signal input.

The first base (g) is a NAND type set reset, ) (R8)
It shows a flip-flop, and when the g terminal input 99 is 0'',
The Q output 101 becomes Pa1''.

Figure (h) shows the data selector, with A input 104°■
Select input 105 according to signal (S) I 09 108
Output as . The logic of output 10g is S −A +SI
It becomes 3. That is, when S = "'l", the information of the A input 104 is output to the output 108, and when s = "o", the output is 1ul.
Information on the B input lθ5 is output to l.

What 1 In the following explanation, the color 71 of the multi-stage counter
- When expressing the state in units of input clocks, the counter output is expressed from the upper bits to QHrQN-,...C3,
When C2 and Ql, "o o.

...000" is 0, '000...001" is 1
1°ゝ000...010" to 2."000...01
1" will be expressed as 3.

(Synchronization Detection/Timing Generation Circuit) As shown in FIG. 1, when the output 22 of the pedestal flank DAC 2 is Ov, an analog video signal of the DCC clamp Ov is obtained at the output of the buffer 6. Now, D.C.
Clamp voltage Ov.

When analog video signal 1 is APL (Avera
When the smallest signal of gePicture Level) is input, the dynamic range of ADCZO is 3-1.3-2 and the ADC10 is
The buffer 2, LPF 4, buffer 6, and buffer amplifier 8 in FIG. 1 are adjusted so that the input of the signal has a waveform as shown in 3-3.

Press the button in Figure 3 to set the pedestal level (PDL) to 3-4.
is set to the value "00101111", and the horizontal synchronization signal separation level (SDI, H) s-s is selected to be approximately 3-4 levels (PDL) 00001111.The control loop of the pedestal flank in one embodiment of the present invention Therefore, the pedestal level of input video signal 1 is (PDL
) is clamped to a value of 3-4. This clamp circuit will be described later.

Regarding the dynamic range of the ADC 70, FIG. 4 shows the signal 4-2 of the pedestal clamp pressure Ov and the normal ramped signal 4-2. In Figure 4, (S
DL, V) 4-: t indicates the vertical synchronization signal separation level, and in order to ensure vertical synchronization reproduction especially against disturbances such as ghosts, (snbn) s - s #) (P
DL) It's close to 3-4. In this example (SD
LV) 4-J is” o o o i i i i
In this way, the digital video signal DYS 11 with the pedestal flag is guided to the synchronization detection/timing generation circuit 27.

FIG. 6 shows the configuration of the synchronization detection/timing generation circuit 27. This circuit 27 is broadly divided into a synchronization separation/horizontal synchronization/zero width detection circuit system 120, a horizontal synchronization periodicity/continuity detection circuit system 12, and a timing generation circuit system 122.

1. First, the input DVS signal 11 is guided to a horizontal synchronization separation circuit 123 and a vertical synchronization separation circuit 125 for separating the horizontal synchronization and vertical synchronization signals, respectively, where they are separated into a synchronization separation signal 124 and a CSv signal. 126 are separated. The synchronization separation signal 124 is filtered by an LPF 127 that removes high-frequency components and one-color frequency components.

Output 128 of LPF 127 is composite synchronization signal (C8H)
Yes, it is led to the horizontal synchronization pulse width detection counter output 29. The output 130 of the counter circuit 129 is input to the width detection circuit 131, and when this count value reaches a predetermined value, the first horizontal synchronization detection signal ( A width detection circuit 131 outputs a signal (IIsl signal) 132. Width detection counter control.

- The gate circuit 133 has a width detection circuit 131 and a width Hs/signal 1.
32 is output, the counter circuit 129 receives the C8H signal 1.
This is to prevent horizontal synchronization malfunctions due to cracking of the C8H signal 128 due to signal input with a large ghost. C8H signal 128 and counter circuit output 130 are C8H signal 1
The signal is led to a horizontal synchronization timing control circuit 135 that controls the falling edge timing of 28. This horizontal synchronization timing control circuit 135 is a timing generation circuit system 1 that generates various timing signals for burst flag pulses and PLL 1 crank if the C8H signal 128 does not fall within a certain period from the output timing of the Hs' signal 132.
22 is inactive.

In this way, since the PLL, clamp, etc. operations are performed only when the C8H signal 128 that satisfies the predetermined conditions arrives, a very stable (disturbance resistant) PLL k and clamp circuit can be constructed.

The horizontal synchronization periodicity/continuity detection circuit system 121 detects the periodicity and continuity of the horizontal synchronization signal (actually the H81 signal), and detects only Its/signal having a predetermined period and continuity as the second horizontal synchronization signal. Detection signal (n.

signal) obtained as 139.

The period detection counter 141 is an 11-stage counter that counts φ8 as a reference clock, and its 11-bit output 143 is led to a period memory circuit 144 that can store count values for two periods. Now, when the Its signal 139 with predetermined periodicity and continuity is obtained at the output of the horizontal synchronization periodicity/continuity detection circuit 138, the 5R6Q1out signal 447 is generated from the latch pulse generation circuit 146, which causes the counter The output 143 of 141 is stored in periodic memory circuit 144. The difference detection circuit 148 detects the difference between the values for two cycles in the periodic memory circuit 144, and the determination circuit 151 outputs a determination signal (DCK signal) 152 from the output iso of the difference detection circuit 148 when this difference is less than a predetermined value. Output.

Next, in the timing generation circuit system 122, the horizontal synchronous falling edge detection circuit 153 uses the 118 signal 139 and R84R.
The falling edge timing of the horizontal synchronizing signal is detected from the signal 136, and when the falling edge is detected, the counter 158 starts counting operation.
fl 56 and generates a reset signal 157. The counter 58 has a 6-stage configuration, and this counter 1
58 output 159 and the output 5R of the PLL control circuit described later.
9Q, signal 161, and 5R9Ql signal 162, PLL, various timing signals 163 to 169 necessary for clan f surrounding operation and burst flag signal 162 are activated.
FP),? The rubber burst flag, PLL, and flag timing generation circuit 160 generates the signal.

Regarding the synchronization detection/timing generation circuit 27 in FIG.
This will be explained more specifically. FIG. 7 shows a specific circuit diagram of the synchronization separation/horizontal synchronization width detection circuit system 120 and the horizontal synchronization periodicity/continuity detection circuit system 12 in FIG. 6.

Referring to FIG. 7, the DVS signal 11 is given to a comparison circuit (Compl) 180 as a horizontal synchronization separation circuit 123 as an X1 power, and is compared with a horizontal synchronization separation level (5DLH) J81 which is an X2 power. The output of x2≧X1 is obtained as the separated signal 124. Similarly, a comparison circuit (Comp2) 1 as a vertical synchronization separation circuit 125
82 vertical synchronization separation signal (csv) J ze
is obtained. Each horizontal and vertical synchronization separation level (5DLH
) 181.

(5DLV) No. 83f-J, as explained in Figures 3 and 4, 5DLII = "00001111'
, 5DLV="00011111", each of the comparison circuits 180 and 182 can be realized with one simple gate. The output 124 of the comparison circuit 180 is guided to a shift register 184 having four stages. shift register 184
The shift clock 1 is φ8. The output of each bit of this shift register 184 is output from a four-man NAND gate 185.
csit (the inverse of C3lI) is obtained as output 128. Shift register I84$- and K"-
The filter 185 configures an LPF 127 to remove components below the fsc period and the black frequency components.

On the other hand, the counter circuit 129 and the width detection circuit 131°-
In the timing control circuit 133 and the horizontal synchronization timing control circuit 134, as shown in the time chart in FIG.
= "1", the counter 187 starts counting, and the 48" count output of this counter 187 (ANDr
-) J 9 +7 (7) output) is shift register 1
91, width detection and through an AND gate 192.
Zorus (H8') 132 is obtained. The HRS flip-frog 193 from which the H8' signal is obtained is set, and the reset signal 189 of the counter 187 is forced to ``0'' through its Q output 195 and the gate 1BB. At the point where the timing control output is obtained, the count value of the counter 1870 is °゛48.
"1" is output between "1128" and "1128". Now, the C3lI signal falls during the period when the output of gate 196 is "1" (
When the C8H signal 128 rises), the waveform shown by R84R in FIG. I understand.NAND
Dart No. 94 has a count value of counter 187 of '239.
”, the Q output 195 of the flip-flop 191 is inverted. As a result, after the Hs' signal 132 is output, "240"-P48"="'192" (φS
The counter 187 operates in such a way that it does not receive the C3I signal input. AND gate 132-2 converts the logic output of Q18/R84Q (described later) to 132-2.
Output as 1.

The Its/signal 32 is guided to a horizontal synchronization periodicity/continuity detection circuit system 121. Before explaining the detection circuit system 12, the corresponding range of horizontal frequencies and the operation of the period detection counter 141 when receiving NTSC and PAL signals of the Denotal TV receiver of this embodiment will be described.

The NTSC signal defined by broadcast waves is 4f8c=91O,
/'ll (f, l: horizontal frequency, fB (2: 4 fs at color subcarrier frequency, = 14.3 MHz).

On the other hand, a signal such as 4 fBc\91OfH also exists in some II/J rubber signal generators, video demes, etc. That is, there is a signal that has no relationship between the color subcarrier frequency Inc and the horizontal frequency f)l. Now, if we assume that the corresponding horizontal frequency range is fH = 15.73 ± 0.5 kHz to avoid any practical problems, the sample clock φ8 (=4f8c) will be generated by the counter 187 within the 1,000-hour period corresponding to this range. °' 880 "～" 94
4” can be counted.

For PAL, 4f8c#1135f, C4f6.
#17.73M1lz) and similarly f++ = 1
Assuming 5-625 kHz±0.5kllz, the number of φ that can be counted in one horizontal period is "1099" ~
1173''.The periodicity detection of the horizontal synchronization signal must cover the above-mentioned horizontal frequency corresponding range.

Therefore, the period detection counter 7 in FIG. 7 detects periodicity.
41 (21J) is a counter capable of counting one horizontal period with φ6 as a reference, and has a 11-stage configuration. When the H8/signal 132 arrives, the counter 213 is set to '14' in NTSC.
By presetting the count to 4" and the count to 64" for PAL, the timing of periodicity detection can be determined easily. horizontal countdown circuit 3
The second circuit configuration can also be simplified.

FIG. 9 shows the relationship between the S/signal 132, the gate signal ('HM1R) indicating the horizontal period corresponding range, and the count value of the counter 213. Only the Hs' signal 132 is obtained as the horizontal open JuJ mountain detection signal ■I8 by the product logic shown as HB=Hs'・11MasR.5R6Q1 is this IIs signal 13
The output of the shift register 215 which stores and records 9 and 76 as shift clocks is shown. 9-1 and 9-2 in FIG. 9 are the NTSC of the counter 213.

I) A time chart for detecting the periodicity/continuity of the H8/signal 132 is shown in the O-th ioc indicating the count state when receiving each signal of AL. ) (MallR signal is NTS
When the C signal is received, the counter 213 as shown by Fi10-1
It rises at a count of "1024" and falls in synchronization with the fall of the Hs' signal. Also, if the H1 signal is missing as shown by )0-3, the HMa sR multiplied signal '1088
When the count falls, the counter 213 has a count of 11 preset to '144' and the next H1 signal arrives.

When the H1 signal is obtained again as shown at 10-4, 10
An Hs-fold signal is obtained from the Hs' signal indicated by -5. PAL
The basic operation is the same when receiving a signal.

As shown in FIG. 1O, it will be understood that the horizontal synchronization detection signal H8 is obtained as a highly accurate signal that is resistant to external disturbances.

By pressing the button in FIG. 7, Iyi is output as the output of the OR gate 207.
The asR signal is obtained, and the HI!I signal 139 is obtained as the output of the AND key"-) 20.8. The Hs' signal 132
The Q output of the RS free-lag frog 212, which is reset by the inversion of
11' Control signal when signal is missing (xts3q in Figure 10)
)give. The preset signal of the counter 213 is obtained as the output 203 of the OR dart 204. As described above, the reset data generation circuit 201 controlled by the NTSC signal generates the digital value "00010010000" corresponding to the "144" count when receiving the NTSC signal, and generates the digital value "00010010000" corresponding to the "64# count" when receiving the PAL signal. f direct'''oooo1oooooo': are generated, respectively.

IIg signal 139 is directed to shift register 215.

The QI output 147 of this shift register 215 is
The timing for latching the 11-bit output 214 of 213 to latch 216 is provided. The output 149 of latch 216 is routed to latch 217. These two stages of latches 216
, 217 constitute a first horizontal period memory circuit 144 and store two periods of r-ta from the button counter 213. It is the subtractor 219 as the difference detection circuit 148 that detects the difference between the values of the latches 216 and 217, and the difference output 220 is determined by the judgment circuit! Output to 5no.

In the determination circuit 151, the upper 9 bits of the 11-bit data of the difference output 220 are inputted to the NAND dart 221 and the AND gate 222.

- The outputs of the gates 221 and 222 are input to the OR dart 223 to obtain the DCK signal 152 as an output.

That is, if the difference between the output 149 of the latch 216 and the output 218 of the latch 217 is within ±63", the DCK signal 152 becomes 1".
, , the DCK signal 152 and the output 147 of the shift register 215 are led to the horizontal countdown circuit 32 of FIG.

FIG. 11 shows a specific configuration of the burst flag/PLL/flag timing generation circuit system 122. H
The inverted signal 232 of the s signal 139 is the RS7 receiver 70 signal 234, and the R84R signal 136 is the frizzoff, 7', ? Reset 34. 1 output 235 of the free lag frog 234 is the falling edge of the horizontal synchronization signal (#) (
It is guided to the 1 shift reno star 236, which is a signal that rises in synchronization with the trailing edge). Q of shift register 236! Output 1
54 is a one-stage Kara/Ri (frig-flock 7'), ?
, 77. Now, Ql output 15 of the shift register
When 4 changes from pa 0" to ゛'1", the counter 237's chisel 4
1 output 157 is "all", this is the counter 2
38 is released from the reset state and starts counting. The counter 238 has a six-stage configuration, and outputs Qss and Qss.
- Self-reset is applied via NAND dart 239 using the logic of Q33.

The operation of the timing generation circuit 160 is shown in FIG. In FIG. 12, the CH8 signal (output of LPF 727 in FIG. 7), the Hs signal 139. φ8, Q1 output 154 of shift register 236, Q41 output 157 of counter 237,
Various timing signals are shown along with the count value of the counter 238 in correspondence with the Q31 T Q3Z...Q36 outputs of the counter 238. These timing signal sections, outputs 28.163, 164, 165, 166.167
168, 169, 157, 230, 161° Noro 2 will be explained as appropriate in the detailed explanation of the flange circuit and PLL control circuit described later.

(Paired Stell 22 Fufu Circuit) The Bedestel crank circuit 19 in Fig. 1 is the same as Fig. 4-2
As shown by the waveform, the pedicle level of the incoming DVS signal 11 is expressed as (pI)I, )
This circuit flags the value of 01111''.

FIG. 13 shows a specific circuit diagram of the pedestal flag circuit 19. In the figure) ISD signal 280 is IIs signal 139
If ttlJt is obtained, the signal indicating the synchronization detection state is input to the synchronization detection determination circuit 285. Now, if H8D = "'O", that is, synchronization detection is not performed, it is not possible to obtain timing information (for example, RFP 2 B) to apply the pedestal flag, so first cut out the synchronization signal part. There is a need. Therefore, when the ll5D signal 280 changes from l" to "'O", the shift register 284 detects the fall of the H8D signal 280, and this detection signal 276 (output of the gate 275) converts the flag voltage into a digital quantity. The latch 272 which is stored as
1 output 22) is set to OV, and the flang control system is set to the initial state.

Generally, when a video signal input is present, the relationship between the dynamic range of the ADC and the signal, which is disabled at the time of initial setting, is as shown by 4-1 in FIG. 4. In FIG. 13, the output of the gate 252 that performs the OR logic of the 8-bit signal that is the DVS signal 11 is the LSI 311! of the dynamic range of ADClo! Only during the period when the human input signal crosses the I terminal, that is, the DVS signal 11 becomes all 0's, which is OJ+.The output of this gate 252 is 8.
It is guided to the shift register 253 of stage 1.

NOR with all outputs of shift register 253 as input
A signal corresponding to the signal obtained by passing the output of the dart 252 through an LPF is obtained as 1'' at the output 255 of the DART 254. These f-) 252, shift register 25
3. To Dart 254! 7. A level detection circuit 281 for the DVS signal 1 is configured. The rising edge of the output signal 255 of this detection circuit 281 is connected to NAND 2
Detected at 56 and set RS fly and pflo f257. In this case, the Q output 258 of the pflop f257 is 1
It is led to the B input of the data selector 269 for 0 bits and 5 bits. At this time, the B input data of the data selector 269 is sent to an encoder (not shown)! 7M5B side °'1
The data selector 269010 bit output 270 and the latch 272 (Dl 2 bit output 273) are matched in LSB and the difference is taken by the subtracter 271.The difference signal is input to the shift register. 253 Q3 output timing (AND+
"-), ? y g output timing), 1 is written to the latch 272 again.

By repeating the above operations, the flag level increases until the Itg signal 139 is obtained. When the Itg signal 139 is obtained, H8D = "1" and a synchronization detection state is entered. When H8D =''l'', switching circuit 2
The A signal 268 is led to the output 270 of the data selector 269 constituting 83, and the pedestal frang mode is established. The DVS signal 11 is converted to (PDL) 25 by a subtracter 250.
1 "00101111" is subtracted. The sign (sgn) bit of the output of subtractor 250 is directed as DVC8 signal 286 to a PLL control circuit to be described below. Further, the 8-bit output including the sgn bit of the subtracter 250 is led to the latch 263, and the 8-bit output including the sgn bit in FIG.
Q3113, which has a period of φ8 shown in Figure 12 from 8
Sampled at force 230.

Ka'J7. The circuit 265 and the latch 266 constitute a digital integration circuit 282. The number of integrations is determined by the φ input 163 of the latch 266. In order to perform the integration of the color burst period as shown in FIG. 12, the number of integrations is set to 12. Of the 2660 outputs 267, the lower 2 bits
) is output from data selector 2.
69 A input.

In addition, the Qsz output 241 from the counter 238 shown in FIG. There is. When the above-described 12 integrations are completed, the circuit 266 is reset at the timing of the L2R signal 164 from the timing generation circuit 160.

The subtracter 271, 272 also constitutes the integrating circuit 284, and the input 270 of the subtracter 271 is all "0".
The integral is inverted so that the pedestal level becomes stable. Note that the L12φ signal 169 from the timing generation circuit 160 and the output of 27
The inverted output 2o-1 is used for the r-cod and chi clocks of the flange DAC 21 (not shown in FIG. 1).

(PLL fljlJ control circuit) An example of the principle configuration of the PLL control circuit 23 is described in the specification of US Pat. No. 4,291,33230.
Here, the specific circuit configuration and characteristics of the PLL control circuit 23 will be described.

FIG. 14 is a block diagram showing a schematic configuration of the PLL control circuit 23. The error detection circuit 300 receives timing signals L7φ signal 162, LzR signal 164. Controlled by the L6R signal 165, the 3Jt distribution 31. on the DVS signal 11 is controlled by the L6R signal 165. I do. Note that the sampling point of P4J is shown on the color burst waveform 5-1 in FIG. In FIG. 5, 5-2 indicates a period (burst period) during which calculation is performed, and in this embodiment, 5-2 was used as 6. That is, the integral calculation of the above equation (1) is performed for six burst periods.

As shown in FIG. 5, if the target sampling phase with respect to the color burst phase is θ, then the error signal is as follows. The error calculation circuit 3 performs the error calculation of equation (2).
02, the calculation output 303 is the error integration circuit 304
guided by. The output 24 of the error integration circuit 304 is the DAC1
6, which causes PLL to be applied.

According to equation (2), by varying the value of θ (actually a value of 10), an arbitrary sampling phase can be obtained. Note that the hue is controlled by making the value of taJIO variable. That is, when the hue control data generation circuit 305 receives the control signal 49, the hue control data generation circuit 305 generates one θ according to predetermined control data.
A signal 306 indicating the selected value is output to the error calculation circuit 302.

On the other hand, the sgn bit of the output 301 of the oscillator error detection circuit 300, which is the result of the integral operation of the above-mentioned (1) equation, is led to the base sampling phase detection key circuit 314, where the reference phase that provides the reference sampling phase is sent to the base sampling phase detection circuit 314.・Zorusu 315
is generated. This reference phase pulse 315 is a reference 1? which continuously generates reference pulses. The reference phase is guided to the pulse generation circuit 316, and the I-axis and PA in the case of i p NTSC.
In the case of L, the signal 26, which indicates the U axis, is the reference t.
Obtained as 4 Rus. Note that for PAL, the U-axis is obtained as a reference phase and a PAL identity signal is required.

The DVC8 signal 2'86 consisting of 1 bit is guided to the burst plate wave integration circuit 308, and is inputted during the 6-cycle period of the color burst, φ. The signal 26 is sampled and the sampling result is integrated. Integral result 3o7 is P
Time constant circuit (
(equivalent to an integrating circuit) 310. Based on the output 311 of the time constant circuit 310, the circular signal 25, and the L12φ signal 169 which is a timing signal, the PAL ident judgment circuit 312 judges whether or not the PAL ident satisfies a predetermined relationship. If there is no relationship, a reset signal 313 is output. The PAL ident generation circuit 307 is a one-stage counter that receives the /IIF11 signal 18 as an input, and obtains a PID signal as its count output. A reset signal 313 is input to the reset terminal of this counter. The reference sampling phase is the U-axis portion of the PAL button, and has a phase of ±45° with respect to the burst phase according to the PID signal 25.

FIG. 15 shows a more specific circuit configuration of the PLL control circuit 23. DVS signal 11 is routed to channel 320. The reset signal for latch 320 is L6R signal 165.

The output 32 of latch 32σ is directed to subtracter 322.

The output 323 of the subtracter 322 is led to a latch 324, and the output 325 of the subtracter 324 is led to a latch 327.

The output 328 of the subtracter 327 consists of 12 bits and becomes one input of the subtracter 322. The MSB of this output 328
An 8-bit output 330 is led to the error calculation circuit 302 from the side. The 12-bit output 325 of the latch 320 is also led to the error calculation circuit 302.

L21 is the signal 164, and the Lyφ signal 162 is the signal that controls the error calculation circuit 302! 7. In the integral operation result shown in equation (1), the output 325 of the latch 324 has Σ(P4 j −P4 j−2), and the output J=1 of the latch 327 has Σ(P4j−1−P4j− 5) controls the switches 324 and 327 so that the value of J=1 is obtained. The sign bits 326 and 329 of the integration result data are led to a random sampling phase detection r-) circuit 314.

Now, if θ=33° in NTSC, the Q-axis (Q-axis) can be detected, and if θ=±45° in PAL, the U-axis can be detected under the control of the PID signal.

In FIG. 15, the AND dart 338 is the Q-axis detection case 9-
To deshi, AND Ke9-to 339,
340 is a U-axis detection cage.
The outputs of 8 to 340 are led to 0Rf-to 341. OR
The output 315 of the gate J41 is the reference pulse generation circuit 31.
6. The shift register 354 is for reference axis detection, and its Q1 output 355 sets a counter 356. The Q62 output 357 of the counter 356 is input to the shift register 358, and is synchronized with the clock signal φ. is obtained as signal 26. This φ. The rising edge timing of signal 26 indicates the Q-axis. In FIG. 16, L7φ signal 162
, LaR signal 165 , 5R9R signal 167 , input 315 of shift register 354 and its Ql output 35
5 r Qs+ + of counter 356. 62 output 357
．． φ8 and 7 lip flow in Fig. 11, Q of pull R85I
Each waveform of the output is shown.

The hue controller was set to 2 bits.

The control data 49 is encoded by a data decoder 333 and encoded by an encoder ROM 335. In the case of NTSC, control data 49 is I+
When 00 IP, the value of O is 33° (center value), °゛0
When it is 1", θ=27°, when it is '10', θ=37°,'
If we choose θ = 41° for 11#, -33° is approximated by 6 bits including sgn, then -33° = 001
0101” and similarly K tan 27°
=”010000”t taa 37°=”01100
0”.

tan41°=”011100” is encoded.

In the case of PAL, the decode value is controlled by the PID signal 26. When using PAL, the control data "00" is θ=±45°, and the encoded output is 7 including sgn.
When approximated by bits and PID = ``'1'', ``01111''
11" as encoded output +)N PID =
When '0' (hereinafter simply referred to as rain), '1000000'
I got it. When control data is “O1” θ= PID
0110000” in PID, “1000000” in PID
get. When control data data is 10H, PID
0111111'', re-6 to get ``1110000''. When control data l'11'', PID is ``011''.
Get ``111'' with 1 sword and ``1100000''.

In this way, regarding hue control, a predetermined encoded output (
An output ) 336 of the encoder 335 is obtained. An output 336 of the encoder 335 indicates a value of -σ and is led to the error calculation circuit 302.

The error calculation circuit 302 includes a multiplier 332 that multiplies the output 325 of the latch 324 and the output 336 of the encoder 335, and an adder 331 that adds the output 337 of the multiplier 332 and the output 330 of the latch 327. Timing signal (φ□φ) 168 provides multiplier 3320 multiplication timing. The output 343 of the adder 331 is input to an adder 344 which is connected to the error integration circuit 304 . Adder 3
The other input of 44 is the output 352 of latch 351.

The output 346 of the adder 344 is led to a circuit 351. The Ltzφ signal provides latch timing for the latch 351, is led to the AND gate 34F1.347, and is used for over-low-underflow detection timing.

These adder 344, latch 351, AND dart 34
7.348 constitutes the error integration circuit 304. cormorant,
The chip 351 has a 13-bit configuration, and a 9-bit output 24 from the MSI 3 side is led to the PLL DAC 76 shown in FIG.

As mentioned above, gate 348 is an overflow detection gate.
- When the output 349 is 1", the latch 351 is preset and the outputs are all 1". Ke9-3・
47 is an underflow detection gate, and the output 350 is 1.
”, the latch 351 is reset and its output becomes all “0”. Note that the output 353 of the adder 344 indicates an overflow output.

In FIG. 15, the DvC8 signal 286 is applied to the adder 3.
6, the output 362 of the adder 361 is led to the latch 363. The AND dart 359 outputs a U-axis detection sum signal 360 at the time of PAL, and supplies it to the latch 363 as a clock.

These darts 359, adder 361, and latch 363 constitute a burst detection integration circuit 30B. The sgn output 365 of this integration circuit 308 is guided to a time constant circuit 310 and further integrated.

The time constant circuit 310 includes an adder 366, the sgn output 368 of this adder 366, and the outputs 36 of the other 5 pits.
It is mainly composed of latches 371 and 372 that latch 7.

In addition, AND ke”-to 373.NOR da
374 and 374 are for overflow and underflow detection, respectively, and the detection timing signal is the φ□φ signal 168. An output 377 of the latch 371 is led to a PAL identity judgment circuit 379. Now, if the 071 output 381 of the counter 380 for PAL identity generation is 1'' and the output 377 of the latch 371 is 1#, the counter 380 outputs the reset signal 3 at the timing of the L12φ signal 169.
13 to return the U-axis detection and PAL ident to predetermined conditions. and counter 380 a
A PID signal 25 is obtained at the tt output.

(Horizontal Countdown Circuit) u (A detailed block diagram of the horizontal countdown circuit 32 shown in FIG. 1 is shown in FIG. 17. The horizontal countdown circuit 32 consists of four major components: 4G1.462, 463.
It consists of 464. Output L 4 out of the periodic memory circuit 144 of FIG. 6 where continuity button and synchronization are detected
Signal 149 and timing signal 147, determination circuit 151
1) The second horizontal period memory circuit 461 stores the synchronization of the incoming horizontal synchronization signal from the CK output 152. Also, the horizontal period data 424 stored in this way
is input, the relationship between the incoming horizontal frequency fII and φ8 is detected, and the IIMOD signal 40 indicating the horizontal standard mode 1 is generated.
0 is determined by the horizontal standard mode detection circuit 464.The HMOD signal 400 is Y- as shown in FIG.
C, /) Guided by the separation circuit 38, press the button, 11M0D=”l
'', as is well known, the Y-C separation circuit 38 separates both the Y and C signals using line correlation (this is known as a comb filter).

On the other hand, when IIMOD = "0", if y and c separation is performed using line correlation, the separation may become very poor in some cases (if the sample points on the IH delay line are far apart from each other on the screen, Therefore, Y and C separation is performed using a well-known BPF using horizontal sample points.In this way, the HMOD signal 400iJ functions to switch the operation of the Y-C separation circuit 38.

An output 424 of the horizontal period memory circuit 461 is led to a horizontal synchronization regeneration circuit 462, and a horizontal drive signal (fHo out ) 34 is obtained by the regeneration circuit 462. -'I
The phases of the IFB signal 18 and the arriving Hs signal 139 are compared, and if they do not have a predetermined phase relationship, the horizontal synchronization regeneration circuit 46
A horizontal phase detection circuit 463 is a circuit for outputting a signal 458 to the signal 458 and drawing in the phase.

Below, each professional in Figure 17 is 461.462°463.
464 will be explained in more detail.

(a) Horizontal periodic memory circuit 461 1.4out signal 149 is directed to subtracter 401.

On the other hand, 5 from the latch d' pulse generating circuit 146 in FIG.
The R6Q1out signal 147 is led to a horizontal period memory timing generation circuit 408, and this circuit 408 generates various timing signals 409, 410.degree. 411. These timing signals 409, 410, 411 are controlled by the DCK signal 152 of the determination circuit 151 in FIG.

The output 402 of the subtracter 4θ1 is a difference detection r-) circuit 405
is input, and the difference value is detected.

This gate circuit 405 is connected to the time constant switching circuit 403 and the control signal generation gate 1←1 path 4 depending on the magnitude of the difference value.
A wobbling signal 403-1.407 is supplied to the adder 412 when the difference value is zero.
Give 6. The time constant switching circuit 403 changes the system time constant according to the above difference value: lj! ] It operates to control. An output 404 of the time constant switching circuit 403 is led to an adder 412. The other input of the adder 412 is a 16-bit, 16-bit bit consisting of 11 bits on the MSB side, and a horizontal period value memory circuit 42.
1 output 424 and horizontal period correction memory circuit 422
This is a signal 425 consisting of an output 423 of 5 bits on the LSB side among the 6 bits. Of the 16 bits output from the converter 412, MSBa+qii bits are led to a switching circuit 415.

The other input of switching circuit 415 has a standard horizontal period. Second
Figure 3 shows a time chart of each timing signal.

As you can understand from Figure 23, Dart 485 is DCK.
When the signal 152 is '1', the self-reset signal 487 is output, and the output from Q3 onward of the shift register 484 will not be output.In other words, if the difference detection is φ8 and the value is more than '3', the periodic memory indicates that the previous state is maintained without performing the example operation.

The output of the subtracter 401 is 8 bits, and G is the effective bit length.
50B input. On the other hand, of the 8-bit signal 474, the LSB side 3-bit signal 473 is sent to the data selector 47.
It will be 5 eight-person power. Furthermore, the signal 4740M5B side 6-bit signal 472 e LSB side 2-bit signal 471
is led to a difference detection gate circuit 405, and the magnitude of the output of the subtracter 401 is detected. In the differential detection date circuit 406, 6 human power ANDr-) 4
79 #6ManpowerNORl'-) 4tt.

Each output is led to 071'-to 41J2.

The output 478 of the OR+"-t 482 will be tt 1 s if the difference is within +"3", and will be "0" if the difference is greater than or equal to +"3".

The output 404 of the data selector 475 has an 11-bit configuration. For example, when the output of the subtractor 401 is +°′2”, “010” is input to the eight-person force 473, and 9,
The output 478 of the OR key 482 becomes It I PI. At this time, the output 4θ4 of the data selector 475 becomes MS
It becomes "00000000010" from the B side. On the other hand, when the output of the subtracter 401 is 10'''8'', @00000100' is input to the B input 474, j=-shi, and the output 478 of the OR dart 482 becomes '0''.At this time, the data The output 404 of the selector 475 is “0000010000
0”.

That is, when the difference (signal 474) is large, the time constant is made small to speed up the convergence of the system, which will be described later, and when the difference is small, the time constant is made large to ensure the stability of the system. Therefore, the horizontal period memory circuit 461 converges quickly, and when the signal converges to a constant value of 1, the time constant is increased, so that a horizontal period memory value can be obtained with high performance.

Output 404 of data selector 475 is directed to adder 412. Other inputs of the adder 412 are the pit output 424 of the horizontal period value memory circuit 412011, and the outputs 51'4, 5 of the 5-bit horizontal period correction memory circuit 422.
This is a 16-bit signal 425 composed of 16 bits. The power for both people is 404.425, which is added by aligning the LSBs.

Wobbling input 406 of adder 412 (adder LS
(adding “1” to B) is the difference detection circuit 40.
5 is obtained as the output of AND dart 4113 when zero is detected.

Out of the output 476 of the adder 412 consisting of 16 bits, M
SB side 11 bit 50B is B of data selector 509
Guided by input. The following 3 bits 507 are led to chi 5 no 3 in the horizontal period correction memory circuit 422, and 2 bits on the LSB side.

To is guided by the latch 5 no 5. data selector 50
The value of the standard horizontal period is output to the A input 427 of No. 9. In other words, the value of "1054" in NTSC is "100001"
11110", the value of '1199' in PAL"'100
10101111''. The output 510 of the data selector 509 is led to the output 512.

In FIG. 18, an abnormal value detection dirt circuit 431 that detects an abnormality in the horizontal period value is a 0-F circuit that determines whether the period value is within a predetermined range. 1024" to "ioss" is detected by 6 people using AND key) 517.P
In AL, it is detected by the ANDr.-to 519-1 whether or not it is within the range of °'1160" to "1224". If the period value 424 is not within a predetermined value, the output 5 of the NOR dart 521 is detected.
22 becomes "i" and is led to ORr"-1503.

The other input of 0Rr-) 50 is the H8D signal 280.

When the input 502 of the shift register 503 becomes 61",
If the output 505 of the AND gate 504 is It l 71, this output 505 controls the data selector 509. ANDr-) 500 outputs φ8 clock 499 at this time. This AND key) 5 (output 499 of 717
and shift register 484 (DQs output 490 is 0
R-3'-)497. OR+'-1-497
The output 498 of is the clock input of latches 512, 513, and 515. Output 505 of gate 5o4 also resets latch 513 and resets latch 515 through 0Re-) 495.

Signal 477 and Q output 492 of Pfrog 491 are AND+''-) 494, ORf-) 495
The latch 515 is reset throughout. FIG. 24 shows a time chart of the horizontal period value reset circuit.

(b) Horizontal standard mode detection circuit 464 FIG. 19 shows a detailed circuit diagram of the horizontal standard mode detection circuit 464. In FIG. 19, the horizontal standard mode detection circuit 42
8 detects the value of the output 424 of the horizontal period value memory circuit 421, and outputs 'l' to the output 550 when it determines that it is the standard mode.

Considering the standard mode for each of NTSC and PAL in Fig. 20, the value of N is '904 as shown at 560 in Fig. 20.
(For inputs that are “~”916”) IMOD = ”
1” (indicates standard mode input), otherwise FI
Set MOD = “0”. 560 indicates the output of the horizontal period value memory circuit 421 as the output f of the latch 512 in FIG.
This is what was shown directly. In other words, when looking at the output of the latch 512, '1048''~''1060 is HMOD=''
1# f@ enclosure.

562r 56J is similarly shown for PAL.

In the case of PAL, the output of the latch 512 is 1192"
11M0D="l for the input of ~"'1208"
” becomes.

Click the button in Figure 19 and turn the keys 540, 541 and 542 to N.
This is for detecting TSC's IIMOD.Goo 1-544,545. ．． 547 is for detecting 11M0D of PAL. The detection signal 550 is ANDed with the 5R12Q a signal 493 which is a timing signal.
The signal is input to the counter 555 and sets the RS flip 70 and 558.

In addition, the signal 5500 inverted signal, together with the signal 493, is
The input signal is input to the D gate 552 and becomes the input signal to the counter 555.The reset of the RS flip-flop f558 is performed using a NAND gate which calculates the AND of the outputs of each counter 555.
- output 557 of port 556. As shown in the figure, the integration circuit 430 needs to satisfy the integration of 8 consecutive horizontal synchronization inputs for the input where 11M0D = "0". J IIMOD signal 40
0 stability has been improved. Therefore, as a result, y−c
Separation stability is ensured.

<cr Horizontal Synchronization Regeneration Circuit 462 As shown in FIG.
A predetermined foo out signal 34 is obtained.

FIG. 21 shows a specific circuit configuration of the horizontal synchronization reproducing circuit 462. The output 424 of the circuit 512 and the output 460 of the horizontal counter control amount encoder circuit 459 shown in FIG. The output 460 of the encoder circuit 495 is data for controlling the count number of the horizontal counter and pulling in the horizontal phase, and when the phases of the IIg signal 139 and /HFI signal 18 match, all degrees are 0°.
The output of the adder 570-1 consisting of 11 bits is led to the latch 570-2, and the phase of the dB multiplied signal is synchronized.

The output 43'6 of latch 570-2 is directed to match detection circuit 437, which also includes an 11-bit comparator 571. The other input to comparator 571 is the output 11 bits of horizontal counter 572. The coincidence output 438 of the comparator 57 is applied to the reset terminal PT of the counter 572, and at the same time, it is applied to the shift register 5 in the horizontal drive pulse generation circuit 439.
Guided by 76. Q+ output 57 of shift register 576
7 sets the RSS free lag flag 578. A Qt output 441 of the shift register 576 is a signal indicating that the counter 572 has been preset, and is led to the horizontal phase detection circuit 463.

The horizontal counter 572 is a counter for the fno out signal 34, and is composed of an 11-stage counter using φ8 as a clock input. In the case of NTSC, the preset data of this counter 572 is "145" as a count value.
665" in PAL, and these are given by the grid data generation circuit 574. This preset value is a value that is 91 counts ahead of the preset value of the horizontal period detection counter 213 in FIG. are doing.

Then, the count value of 573 is taken out as the Tl1c signal 447 through ANDf-) 573.

The reset signal of the RSS free lag flop 5 in the horizontal drive/IP pulse generation circuit 439 is y-t579.5.
11O,581. Furi, goof mouth, goof 57
An f11D signal 440 is obtained at the output of 8. f0 signal 4
Reference numeral 40 denotes a dry pnosol which is controlled in units of φ8 clocks.

FIG. 25 shows the output 445 of the comparator 571, the Q1 output 44 i * fHp signal 440 of the shift register 576, and the count value of the counter 572 for pressing NTSC and PAL.

FIG. 26 shows a general fHD signal 440, IfH,B signal '8' TlIc signal 447, and NTSC, P
The outline and phase relationship of the count value of the counter 572 in AL are shown. In the same figure, T110 signal 447 rises 9
The timing of 832 counts is the fIIFB signal 1.
It can be seen that it is located approximately in the middle of 801 cycles.

The 5-pit output (3 bits s i 4 on the MSB side, 2 bits 516 on the LSB side) of the horizontal period correction memory circuit 422 in FIG. 18 is led to a decoder circuit 448.

In FIG. 21, decoder circuits 448 and 590 are composed of 5-pit input and 32-output decoders. Decoder 5
90 is 5 bits, and when the input is 'ooooo', the first decode output 587 is 61''.
, the second decode output 588 is '1'''11
111'', the final decode output 589 becomes '°1''. Outputs 581, 588 . of decoder 590 . ...589
becomes one input of the AND darts 583, 584, .

The fHO signal 440 is input to a tapped horizontal drive d' pulse delay circuit 442 consisting of 62 inverter rows, and at the same time is guided to r-1583. Delay circuit 442
The total delay amount of the 062 inverter rows is preferably one period of φ8, and assuming the case of NTSC, the total delay amount is 7 Q n5ec, and the delay amount per inverter stage is approximately 1 n5ec. It will be about. Output lines 582 and 5116 are output from the delay circuit 442 for every two inverters, and each output is given to one input of ANII'' -1583, 584, -5850 in the selection r-to circuit 444. 583°584,...
The total 32-bit output of 585 is led to OR dart 586, and the fno Out signal 34 is sent to the output of OR dart 586.
is obtained.

In this way, the delayed output of the 1'+10 signal 440 is selected according to the output of the horizontal period correction memory circuit 422,
A fllD out signal 34 is obtained. As a result, fl
The 1D out signal 34 has a resolution more accurate than the φ8 clock unit.

FIG. 29 is a diagram for explaining this effect in correspondence with a specific noso turn on the TV screen. Figure 29 (,
) indicates a vertical line that should originally be displayed on the screen. Same figure (b)
is fno o in units of φ without performing the above horizontal period correction.
This shows an example of how vertical lines are displayed when the ut signal 34 is output.

When φ8\N-f,, (that is, when the relationship between φ8 and fH is not an integral multiple, as is the case with PAL standard signals, for example), the vertical line that should originally be displayed (broken line in the figure), ?
9-4 is displayed as shown by the solid line, 29-1929
As shown at point -2.29-3, a gear with a width of φ8 period is generated. Since the φ8 period is approximately 56 n5ec in PAL, this gear can be detected with the naked eye. Unless this gear is below the detection limit of the naked eye on the screen, it is not sufficient for a high-quality television receiver.

In this embodiment, in order to bring this gear sufficiently below the detection limit, as described above, the output 514° 516 of the horizontal period correction memory circuit 442 shown in FIG. By controlling the amount of delay, the resolution of horizontal synchronous reproduction can be improved to φ8 units or less.

As a result, as shown in Fig. 29(c), the gear I speed is theoretically reduced to 1/32 compared to that shown in Fig. 29(b).
In practical terms, there is no interlayer at all.

(d) Horizontal phase detection circuit 463 As shown in FIG. detect,
The horizontal frequency BJJ iff generation circuit 462 is controlled according to the detected phase information, and as a result, the Hs signal 139 and f11F
This is a circuit for pulling in the phase 41 to bring the B signal 18 into a predetermined phase relationship. In this case, the phase is drawn in continuously and the drawing time is fast.

FIG. 22 shows a specific circuit configuration of the horizontal phase detection circuit 463. In FIG. 22, the fHF8 signal 18 is guided to the shift register 600 of the f□, B detection circuit 450, and
II''-) 601 The rising edge is detected.

-' When the rising edge of the HFI signal 18 is detected, the detection signal 451 sets the INSNS flag flag 603 in the timing generation counter circuit 463. An output 604 of the free-lag f603 is input to a preset terminal of an eight-stage counter 641. Counter 64! The reset value is ``20'' for NTSC.
In the case of NTSC and PAL, the following comparison pulses are used for both NTSC and PAL. The output 605 of the counter 641 is the comparison J? pulse generation circuit 454. The ratio pulse generating circuit 45'4 outputs /HF! to the incoming) Ig signal 139. +Various timing signals (comparison) of signal 18 J? rus) occurs. Comparison: Zorus has 6 types of reeds: TPI, TP2...TP6, as shown in the diagram.
09.610.611 and RSS Flip Frog 6
1,619. σ20, 621, and 622 are made. -) 6170 output 612 is 'r p i and 1 furi, f floor zo 619 output 624 is TP2, flip flora f 618 output 6237') 'T P 3
, the output 626 of the flip-flop 620 is TP4, the output 628 of the flip-flop f622 is TP5, and the output 627 of the flip-flop f621 is rP6.

fHFB signal 1B in a state where the phase is pulled in in FIG. 27,
Counter reset timing 604 (CTR9PT
), Hs signal 139 + T P 1 r T
P2.

Each time chart of TP3, TP4, TP5, and TP6 is shown together with the count value of the counter 641. Counter (CTR9) 541 counter value in Figure 27
104" to "108" are values approximately in the middle of the period of "IIFII signal 18.

11Jj2No4'x T P 1 and T P 2 are pulses located on both sides of the retracted position as shown in the figure.
A that detects that the horizontal phase is slightly shifted? It's Luz. TP3. TP4 is a comparison signal as shown in the figure of "flFB signal pulse Itl", which detects a deviation of about 60 clocks from the pull-in position by about φ8 clocks. TP5 and TP6V, for example, a TV channel. due to switching, etc.) /IIFB (c' No. 78
This is a pulse that detects that the Itg signal 139 is largely out of phase, and the THc signal (Fig.
47).

For Figure 22, Comparison Nocellus TP1612゜TP2
624. TP2425. TP3623゜TP4626.
TP5622. The TP6627 is led to a phase comparison circuit 457, where phase comparison with the Hs signal 139 and detection are performed.

TP3623゜TP4626. TP5622. TP66
27 is warned by 4-Bit and is guided by Chiro 29. The clock of latch 629 is led by H8 signal 139.

For example, when TP3 is 11, the Ha signal 139 is input to the output of the latch 629.
) and the PI-8 signal 594 is at,”
becomes. In this way, the comparison No4rus TP3゜TP4. T.P.
5. When the Hs signal 139 arrives in the TP6, the output of the chiro 29 becomes 'l#' according to the comparison/e pulse input. The output of the latch 629 corresponding to each comparison signal is PI −
8 signals 594°1) I+-8 signals 593, PI +
32 signal 591°I) I+321ti number 592. These signal signals are -8, +8. +32. −
32 indicates the control value of the count value of the horizontal synchronization counter 572 in FIG. This is the signal for phase pull-in with a delay of 1 minute.
21, the 5R13Qi signal 44 from f frog 576 is connected to the reset terminal of U7chi 629.
The lunch 629 is cleared every time the horizontal synchronization counter 572 is reset. Comparison pulse T P 16, ? close to desired phase? .

TP2624 is designed to ensure stability of retraction.
3. TP4. TP5. It is handled separately from the case of TP6. The T P 1 /# pulse 612 is input to the AND dart 630 together with the Hs signal 139, and the output of the key 1630 is guided to a two-stage counter 632. Kara/ri6
The logic output of TPl-I8 is led to the reset terminal R of 32.

flip f70 through the driver 1633. If you set the pro 34 and reset it with the 5R13Q l signal 640, the PI
-2 signal 596 is obtained. That is, IIs (No. 8 13
If 9 is present four times in a row in the TPI signal 612,
A control signal PI-2 is obtained.

Similarly, for the TP2 signal 624, the frig 70
A PI+2 signal 595 is obtained from the output of the PI signal 639.

When the 21st V button is pressed, the output PI-2 signal 596 of the phase comparator circuit 457. PI+2 signal sys, PI-8 signal 594
, PI+8 signal 593. PI-32 signal 59Z,
PI+32 signal 591 is guided to horizontal counter control amount encoder circuit 459. As shown in the figure, for example, when the PI+32 signal 591 is °'l'', this encoder circuit 459
Output “0100000” indicating the value of +32, and
-32 signal 592 is ul m, output 460 -3
It outputs "1100000" indicating a value of 2.The output 460 of the encoder 459 is then led to an adder 570 in the horizontal counter reset value calculation circuit 435.

(Vertical Countdown Circuit) As shown in FIG. 28, the vertical countdown circuit 36 for FIG.
The synchronization establishment determination circuit 36-2 is configured to determine whether or not 39 is detected. Regarding the vertical reproducing circuit 36-1, please refer to a known document: Japanese Patent Application Laid-open No. 159673/1983 entitled "Vertical Synchronization Circuit", which provides a detailed example of a basic circuit. The vertical reproduction circuit 36-1 according to the embodiment of the present invention may be constructed by partially modifying the above-mentioned known document. Regarding this changed part, the counter 65113.653 in FIG.
Each counter has two stages corresponding to 10°12 in the figure.

In this embodiment, the Q86 signal 650 is input to the counter 651.
Input black and white, Q2 output 652 of counter 651
is input to the counter 653, and the counter 653 outputs 2.
Obtain the fII signal. In addition, the reset input of the counter 65 outputs 5ft13Q as a signal 441, and the reset input of the counter 65 becomes the signal 441.
53 reset input is 5R13Q + signal 10 Re5et
1 (see Figure 4 of the above-mentioned known document). Further, the CSV signal 126 may be used instead of the CS described in the above-mentioned known document. The fyOout signal 37 in FIG. 28 is the vertical drive signal. The fvDoo signal 37 is routed to Color/R66σ. The reset input of the counter 66θ is the Hs signal 139. The RS Frizzo Frog 663 records the judgment status of synchronization establishment with 1, and also with Q.)
It is set by the Is signal 662 and reset by the output of the NAND &''-toro 61. That is, if one or more Hs signals 139 are output within one cycle of the fvnoul signal, it is determined that synchronization has been established. , Furiazo.The output of the flop 663 becomes °゛1''. This Q output is synchronized with the φ8 signal by the shift register 665, and the H8D signal 280 is obtained from the output of the shift register 665.

That is, when the synchronization fails and h, H8D = ``1#''.Actually, as shown in the figure, the Q output of free lag 70.f663 is R818Q +/vo out-Q 141
The resultant signal is ORed as shown in FIG. The signal 664 connects the clamp circuit I9 to VJJjl once every two vertical periods of 11SD.
This becomes a signal for entering the J state.

[Brief explanation of drawings]

The figures are for explaining one embodiment of the present invention. Figure 1 is a block diagram of the main parts of a 7J digital TV receiver, and Figure 2 is for explaining the notation method of the circuit shown in the same embodiment. diagram,
Figures 3 and 4 are ADC dynamic range and video signal waveform diagrams to explain the operation of the same) ε embodiment, Figure 5 is a burst waveform diagram to explain the principle of the PLL circuit, and Figure 6 is a burst waveform diagram to explain the principle of the PLL circuit. The figure is a block diagram of the synchronization detection/timing generation circuit, Figure 7 is a specific circuit diagram of the synchronization separation circuit button and horizontal phase detection circuit, and Figures 8 to io are time charts showing the operation of Figure 7. The HuIt diagram shows the burst flag
A concrete circuit diagram of a timing generation circuit for PLL-clamp, a time chart showing the operation of FIG.
Fig. 14 is a block diagram of the PLL control circuit, Fig. 15 is a specific circuit diagram of the PLL control circuit, and Fig. 16 shows the operation of Fig. 15. The block diagram of the circuit, FIG. 18 is a concrete circuit diagram of the horizontal rotation memory circuit, UII 9 (31g, the concrete circuit diagram of the horizontal detection mode detection circuit NtS 12J,
Figure 20 is a table explaining the operation of Figure 19, Figure 21 is a concrete example of the horizontal synchronization reproducing circuit, Figure 1, Figure 22 is a concrete diagram of the horizontal phase detection circuit. Figures Wt5, 23 and 24 are time charts showing the operation in Figure 18, Figures 25 and 26 are time charts showing the operation in Figure 21, and Figure 27 shows the operation in Figure 8g22. 28 is a circuit diagram of the vertical countdown circuit, and FIG. 29 is a diagram for explaining the operation of FIG. 21. 11 (DVS)...Digital video signal, 27.
...Synchronization detection/timing generation circuit, 32...Horizontal countdown circuit, s s, 4 o O (HMOD
)...mark i%11 mode detection ILl signal, 38...y
-c separation circuit, 735? (IIg)...Horizontal synchronization detection signal, 461...Horizontal periodic memory circuit, 464...
Horizontal standard mode detection circuit.

Claims (1)

[Claims] In a digital television receiver that performs signal processing after digitizing a video signal, means for detecting a horizontal synchronization signal from the digital video signal separates a composite synchronization signal from the digital video signal. means for starting counting at the leading edge of each pulse of the composite synchronization signal separated by the means, and generating a first horizontal synchronization detection signal shifted from the pulse each time the count value reaches a predetermined value; , and means for selecting and outputting a signal that is continuously generated at a predetermined period from among the first horizontal synchronizing signals generated by the means as a second horizontal synchronizing signal. Digital television receiver.