JPH0318776A - Logic circuit functional verification method - Google Patents

Abstract

PURPOSE:To easily recognize an unverified state by describing in advance a state to be verified against an arbitrary function unit in a logic circuit, and detecting whether the state to be verified is generated in the course of simulation or not. CONSTITUTION:The description of the function of the logic circuit is registered in a function description registering means 11, and a state to be verified is registered to an arbitrary function unit in the description in a verification item registering means 13. In a verification executing state storage means 15, in the case the state to be verified is generated against each state to be verified, a verification executing state flag set to an ON state is set to an OFF state and stored. Subsequently, the description of the function of the means 11 is inputted to a simulator 12 and brought to simulation. In this case, when the state to be verified is generated, the verification executing state storage means 15 sets the verification executing state flag to ON at every state. When the simulation is ended, an unverified item display means 16 displays a fact that the verification executing state flag of the means 15 is OFF.

Description

[Detailed Description of the Invention] Industrial Field of Application The present invention relates to a method of functionally verifying the function of a logic circuit using a simulator, and in particular, the present invention relates to a method for verifying the function of a logic circuit using a simulator. This is a functional verification method for a logic circuit that can easily determine whether the functionality of a logic circuit is verified, and can easily determine the unverified contents if there are verification items that have not been verified among the verification items that should be functionally verified.

BACKGROUND OF THE INVENTION In recent years, functional verification methods for logic circuits have been developed to describe the functions of logic circuits using a diagrammatic language that graphically expresses the connections between logic elements or functional elements, or a high-level language called a hardware description language. This is done by inputting the verification pattern into the above description to execute the simulation, and determining whether the functional verification result is pass or fail based on whether the output value of the simulation and the expected value match. It is carried out in

Problems to be Solved by the Invention However, with the above-mentioned method, it is not easy to judge whether all the functions of the logic circuit that should be verified are verified manually or not. Even if some of the content has not been verified, there is a problem in that a misunderstanding may occur that if the human output relationship is as expected, then all of the logic circuits are functionally designed correctly. are doing.

In view of the above-mentioned problems, the present invention registers the states to be verified for arbitrary functional units in a logic circuit, and checks whether the above-mentioned states to be verified occur during simulation. By displaying the unverified states among the states to be verified after the simulation is completed, it is easy to check whether all the states to be verified have been verified using the verification button used in the simulation. The purpose of the present invention is to provide a method for verifying the function of a logic circuit, which can be determined and easily grasp unverified portions and unverified states.

Means to solve the problem i! In order to solve the problem, the present invention provides a functional verification method for a logic circuit that includes a simulator, which includes a functional description registration means for describing and registering the functions of the logic circuit, and any one of the above descriptions. For functional units,
A verification item registration means for registering a state to be verified as a verification item, and when a state to be verified registered as described above occurs during simulation execution, a verification execution state flag set for each state is set to on. a verification execution state checking means for storing the state of the verification execution state flag; and a verification execution state storage means for storing the state of the verification execution state flag; and unverified item display means for displaying the unverified items.

Operation The present invention uses the above-mentioned 1/1 control to first register a description of the function of a logic circuit in the function description registration means, and then the verification item registration means G to check the state to be verified for any functional unit in the above description. Register.

The verification execution state storage means sets and stores a verification execution state flag, which is set to an on state when a state to be verified for each state to be verified registered in the verification item registration means occurs, to an off state. do.

The function description of the function description registration means described above is manually entered into the simulator and the simulation is executed.

During simulation execution, the verification execution status inspection means manually inputs the state of the functional unit whose state to be verified is registered in the verification item registration means from the simulator, and checks the state of the functional unit and the state to be verified for the functional unit. If a state to be verified occurs, the verification execution state flag is turned on, and the verification execution state storage means stores the state of the verification execution state flag. At the end of the simulation, the unverified item display means:
The verification execution state flag stored in the verification execution state storage means is checked, and verification items for which the verification execution state flag is off are displayed to determine whether the verification button used in the simulation or all of the states to be verified have been verified. It is possible to easily determine whether or not the test has been carried out, and it is also possible to easily grasp the unverified state.

EXAMPLE Hereinafter, a method for verifying the function of a logic circuit according to an example of the present invention will be explained with reference to the drawings. In Figure 1,
11 is a function description registration means for describing and registering the function of the logic circuit to be verified, 12 is a simulator for inputting the above function description and executing a simulation, and 13 is a function description registration means for performing verification on any functional unit in the function description. Verification item registration means for registering a description in which the desired state is defined in advance; 14 indicates the state to be verified for any functional unit registered in the verification item registration means and the state of the corresponding functional unit at the time of execution of simulation; l5 is the above-mentioned verification execution state checking means for checking whether or not a state to be verified has occurred by comparing with Verification execution state storage means for storing the state of the verification execution state flag, and t6 is an unverified item display means for displaying verification items for which the verification execution state flag of the verification execution state storage means is off after the simulation is completed. be.

The functional verification method for the logic circuit configured as described above will be explained below in Figures 1 and 2. Figures 3 and 4. Figure 5,
The operation will be explained using FIGS. 6 and 7.

First, FIG. 2 shows an example of registering a functional description for the 1,000-stage functional description registration l1. In this example, the functional description describes and registers the function of a logic circuit in a high-level language called a hardware description language. Figure 3 is verification item registration 1,000 steps l3
In this example, a state to be verified for an arbitrary functional unit described in the hardware description language of FIG. 2 is registered.

The description defining the state to be verified registered in the verification item registration means 13 as shown in FIG.
5, and the verification execution state storage means 15 stores a verification execution state flag that is set to an on state when a state to be verified occurs for each state to be verified registered in the verification item registration means 13. The state of the verification execution state flag is set to OFF as an initial state and is stored. For example, the initial state of the verification execution state storage means 15 for FIG. 3 is as shown in FIG. 4.

The functional description registered in the functional description registration means 11 as shown in FIG. 2 is input to the main calculator 12, and a simulation is executed. The verification execution state checking means 14 checks the verification execution state flag at the time of simulation execution, and sequentially obtains from the simulator the state at the time of 'y3 execution of the functional unit to be verified for which the verification execution state flag is OFF. The data is imported and compared with the state to be verified to detect whether the state to be verified has occurred. When a state to be verified occurs, the corresponding verification execution state flag is turned on and the state of the verification execution state flag is stored in the verification execution state storage stage 15. For example, as for the operation of the malfunction detection stage 14 during the execution of the system shown in FIG.
The states of ER 1 and TER 2 are checked and compared with all the states in FIG. 3, and if they match, the verification execution state flag is set to on. The verification execution state storage stage 15 stores a verification execution state flag.

For example, at the first rising edge of clk from the initial state, SEL is H, T-R1 is -10, and TER2 is +2.
In the case of 3, the state of the verification execution state storage stage 15 is as shown in FIG.

On the next rising edge of the clk signal, SEL and TE
The states of R1 and TER2 are checked and compared with the state in which the verification execution state flag in FIG. 3 is OFF, and if they match, the verification execution state flag is set to ON. The verification execution state storage stage 15 stores a verification execution state flag. After the simulation is completed, the unverified item display means 16 checks the state of the verification execution state flag stored in the verification execution state storage means 15, and selects the verification items for which the verification execution state flag is off. It is inserted and displayed from the registration means 13. For example, if the state of the verification execution state memory 15 at the end of the simulation is as shown in FIG. 6, the unverified item display means 16 will display as shown in FIG.

As described above, according to this embodiment, by describing the functions of the logic circuit to be verified in a high-level language and by describing the state to be verified for any i-function unit, When running a simulation, it is checked whether a state that should be verified has occurred, and after execution of the simulation, the state that was not verified by the above input button is displayed. You can easily understand the current state. Note that in this embodiment, the function description registration means l1
Although the method described above is a means for registering a functional description in a high-level language, it may also be a means for registering a functional description in a diagrammatic language that graphically expresses the connection relationships of elements included in a logic circuit. 8th
The figure shows an example of a functional description in a graphical language that graphically expresses the connection relationships of elements included in a logic circuit in the 1,000-stage functional description registration. A method for verifying the function of a logic circuit in which the function description registration means 11 is configured as a means for registering a function description in a diagrammatic language that graphically expresses the connection relationships of elements included in the logic circuit is also described in FIG. Depending on the configuration, it can be implemented in the same way as the above embodiment.

In the functional verification method for a logic circuit in which the function description registration 11 steps is used as a means to register a functional description in a diagrammatic language that graphically expresses the connection relationship of elements included in the logic circuit, the logic circuit to be verified is By describing the functions of a logic circuit in a diagrammatic language that graphically expresses the connection relationships of elements included in the logic circuit, and by describing the state to be verified for any functional unit, simulation can be performed for any input pattern. It is checked whether a state that should be verified has occurred during execution, and the states that were not verified by the above input button are displayed after the simulation is executed, so it is easy to understand the states that were not verified by the above input pattern after the simulation is executed. can.

Effects of the Invention As described above, the present invention provides a function description registration means for describing and registering the functions of a logic circuit, and a verification method for registering a state to be verified as a verification item for any functional unit in the above description. an item registration means; a verification execution state checking means for setting on a verification execution state flag set for each state when the registered state to be verified occurs during simulation execution; and the verification execution state flag. By providing a verification execution state storage means for storing the state of the verification execution state, and an unverified item display means for displaying the verification items for which the verification execution state flag of the verification execution state storage means is OFF after the completion of the validation process, the logical Describe in advance the state to be verified for any functional unit in the circuit,
By checking whether the above-mentioned state to be verified has occurred during the simulation, it is possible to easily grasp the state that was not verified by the simulation manual pattern after the simulation was executed.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a functional verification method for a logic circuit according to an embodiment of the present invention, Fig. 2 is a diagram showing an example of registering a description in a high-level language to the functional description registration means, and Fig. 3 is a diagram showing verification item registration. FIG. 4 is a diagram showing an example of the initial state of the verification execution state storage means, and FIG. 5 is a diagram showing an example of the state of the verification execution state storage means during simulation execution. , FIG. 6 is a diagram showing an example of the state of the verification execution state storage means after simulation execution, FIG. 7 is a diagram showing an example of displaying unverified contents displayed on the unverified contents display means, and FIG. The figure shows an example of registering a description in a graphical language to the function description registration means. 11...Function description registration means, 12...
simulator, 13... Verification item registration means,
l4... Verification execution state inspection means, 15...
. . . Verification execution state storage means, l6 . . . Unverified item display means.

Claims (2)

[Claims] (1) In a method for functional verification of a logic circuit equipped with a simulator, there is a function description registration means for describing and registering the functions of the logic circuit, and a state to be verified as a verification item for any functional unit in the above description. a verification item registration means to be registered; a verification execution state checking means for setting on a verification execution state flag set for each state when the registered state to be verified occurs during simulation execution; The present invention comprises a verification execution state storage means for storing the state of an execution state flag, and an unverified item display means for displaying verification items for which the verification execution state flag of the verification execution state storage means is off after the simulation ends. A functional verification method for a logic circuit characterized by: (2) The functional description registration means is a means for registering a functional expression that expresses an operation equivalent to a logic circuit in a high-level language, or a functional expression that expresses an element included in a logic circuit in a graphical language. A functional verification method for a logic circuit according to claim (1).