JPH0318777B2 - - Google Patents

Description

[Detailed Description of the Invention] <Detailed Description of the Invention> The present invention is a phase-locked loop (hereinafter referred to as PLL).
The present invention relates to a synthesizer type radio receiver configured to obtain a local oscillation signal from the PLL and sweep the frequency of the local oscillation signal by varying the division ratio of the programmable frequency divider in the PLL.

<Background Art> In radio receivers of this type, accurately setting the division ratio of the programmable frequency divider is a condition for achieving accurate reception frequency sweeping operation, and various methods have been used to date. has been developed and put into practice.

By the way, the tuning operation in this type of synthesizer type radio receiver is normally performed by pressing a push button for tuning, and while the push button is held down, the frequency division ratio is varied to sweep the frequency, and the broadcast frequency is When the user releases the push button when the number matches the number, the above-mentioned sweep operation is stopped and reception is performed.

In such receivers, the frequency sweep speed is constant, so depending on the device, the sweep speed may be too fast and cannot receive the desired station, or it may be too slow. The drawback was that it was not possible to select stations reliably at high speed.

<Object of the present invention> The present invention was invented in view of the conventional situation as described above. For example, it is possible to perform a sweep operation by changing the analog output of an analog variable element such as a volume. Therefore, it is an object of the present invention to provide a synthesizer type radio receiver that allows the user to reliably set the frequency division ratio of a programmable frequency divider at any speed.

<Embodiment of the present invention> An embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

Configuration: FIG. 1 is a block circuit diagram of an embodiment of the synthesizer receiver according to the present invention, in which 1 is an antenna, 2 is a high frequency amplification circuit, 3 is a mixer, 4 is an intermediate frequency amplification circuit, and 5 is a detection circuit, 6 is an audio amplification circuit, and 7 is a speaker.

8 is a well-known phase-locked loop (PLL) consisting of a voltage controlled oscillator (VCO) 9, a first reference oscillator 10, a programmable frequency divider 11, a phase comparator 12, and a low-pass filter 13, and the programmable frequency divider The voltage controlled oscillator 9 generates a local oscillation signal with a frequency corresponding to the frequency division ratio set to 11.
The signal is outputted from the mixer 3, and the mixer 3 outputs an intermediate frequency that is the difference between the received frequency and the received frequency obtained from the high frequency amplification circuit 2.

Reference numeral 14 denotes a frequency division ratio setting device, which is a characteristic part of the present invention, and has a circuit configuration shown in FIG.

That is, in FIG. 2, 15 is a second reference oscillator that generates a reference signal fc of a specific frequency.
This reference oscillator 15 may be removed and the first reference oscillator 10 may also be used.

Reference numeral 16 denotes a first frequency divider that divides the frequency of the reference signal fc obtained from the second reference oscillator 15 to a frequency f1 that can be processed by the first counter means ₁₇ at the next stage and outputs the frequency.

The first counter means 17 converts the output frequency f ₁ of the first frequency divider 16 into the maximum value N ₂ of the frequency division ratio N set in the programmable frequency divider 11 (corresponding to the lower limit of the reception frequency band). ) is a counter that can count up to a constant number n greater than ), and is reset and refreshed each time it receives a reset pulse RP from the second frequency divider 18.

The second frequency divider 18 is the same as the first frequency divider 16.
A reset pulse RP is output every time the output frequency f ₁ of 1 is divided by N ₂ +n.

Reference numerals 19 and 20 are second and third counter means which both receive the output frequency fc from the first frequency divider 16 in the same manner as the first counter, and are comprised of, for example, a shift register.

The second counter means 19
The output frequency f ₁ inputted from the frequency divider 16 is divided by the frequency division ratio N set in the programmable frequency divider 11.
When it counts the minimum value N ₁ (corresponding to the upper limit of the receiving frequency band), it outputs a count end signal N ₁ consisting of a single pulse, and when it receives the reset pulse RP, it is reset and the count value is refreshed. It is something that

Further, when the third counter means 20 counts the output frequency f ₁ inputted from the first frequency divider 16 by a number equivalent to the maximum value N ₂ , it outputs a count end signal eN ₂ consisting of a single pulse. Thereafter, when it receives the reset pulse RP, it is reset and the count value is refreshed.

Reference numeral 21 denotes a fourth counter means, such as a shift register, etc., which sets a stable oscillation frequency fv from the variable frequency oscillator 23, which is obtained according to the output of the analog signal generator 22 as a channel selection operation means, to a set value N ₀ When it has counted up to, it outputs a count end signal _eN0 , and is then reset and refreshed by receiving the reset pulse RP.

The analog signal generator 22 is composed of a variable resistor 22' such as a volume resistor, and the variable frequency oscillator 23 is composed of an unstable multivibrator. If the analog output is large, the oscillation frequency fv is high, and if the analog output is small, the oscillation frequency fv is low.
Output.

Therefore, depending on the magnitude of this oscillation frequency fv, the time length required for the fourth counter means 21 to count the set value N ₀ changes; if the oscillation frequency fv is large and such time length is short, then If the count value of the first counter means 17 (that is, the frequency division value N for the programmable frequency divider 11) is small, and the oscillation frequency fv is small and the time length is long, the first counter means 17 at that time is small. The count value (frequency division value N) is made to increase.

The time length required for the fourth counter means 21 to count the variable frequency fv up to the set value _N0 when the analog output of the analog signal generator 22 is maximized is determined by the first and second counter means 17,
19 is equal to the time length required to count the output frequency f ₁ of the first frequency divider 16 to the above-mentioned minimum value N ₁ , and when the analog output is minimized, the fourth counter means 21 is equal to the time length required to count the output frequency f 1 of the first frequency divider 16 to the above-mentioned minimum value N 1 . Set value N ₀
The time required to count up to the first and third
It is assumed that the counter means 17 and 21 are set equal to the time length required for counting the output frequency f ₁ to the maximum value N ₂ .

24 is three R-S flip-flops (hereinafter referred to as
FF) 25, 26, and 27; six AND circuits 28 to 33; and an exclusive OR circuit 34.
It is connected to the frequency divider 18 and the second to fourth counter means 19 to 21 as shown in the figure, and its specific operation will be explained in detail in the next operation section, but the point is that the second counter Means 19 is the lowest value of the frequency division ratio N.
When it counts N ₁ and outputs the count end signal eN ₁ , it enters the operation standby state. After that, when the count end signal eN ₀ is obtained from the fourth counter means 21, it enters the operation state and outputs the memory set pulse MS. and then a reset pulse
When RP is input, the operating state is canceled and the system returns to the initial state.

Reference numeral 35 denotes a memory means for supplying the division ratio N to the programmable frequency divider 11, and each time the memory set pulse MS is obtained, the count value of the first counter means 17 at that time is set to the division ratio N.
The frequency division ratio N is read in and stored as , and the frequency division ratio N is supplied to the programmable frequency divider 11 as described above.

Effect: The present invention is constructed as described above,
The effect will be explained below.

Now, in the frequency division ratio setting device 14, immediately after the reset pulse RP (see waveform (a) in FIG. 3) is output from the second frequency divider 18, the first to fourth counter means 17, 19 , 20 and 21 are all reset to refresh the count values up to that point, and the signal processing circuit 24 assumes an initial state.

In this initial state (period T ₁ from time t ₁ to t ₂ in FIG. 3), each FF 25 to 2 of the signal processing circuit 24
Since FF 7 is in the reset state, each FF 25 to 27
output terminal, i.e., output terminal Q of FF25, FF2
The output terminal of FF 27 and the output terminal Q of FF 27 have waveforms as shown in FIG. 3 (c), (e), and (g).

Coupled with this, the AND circuits 28 to 30 in the previous stage
The output levels of the AND circuits 31 to 33 at the subsequent stage are all at the "L" level as shown in FIG. (See waveform (h) in Figure 3) is not output.

In such an initial state, the first frequency divider 1
The output frequency f ₁ outputted from 6 is supplied to first to third counter means 17, 19 and 20,
Further, the oscillation frequency fv outputted from the variable frequency oscillator 23 in accordance with the analog output of the analog signal generator 22 is supplied to the fourth counter means 21, but as the supply of each of these frequencies f ₁ and fv progresses, the above-mentioned When the second counter 19 finishes counting the lowest value N ₁ of the frequency division ratio, which is the set value (time t ₂ ), the second
The counter 19 outputs a pulse-like count end signal.
eN ₁ (see waveform (b) in Figure 3) is output.

Simultaneously with the output of this end signal _eN1 , the FF 25 enters the set state and inverts the output of the output terminal Q to "H". Therefore, as shown in FIG.
If one input terminal of both 9 and 30 becomes "H" level, and at the same time, the signal processing circuit 24 receives the count end signal _eN0 , it will generate a memory set pulse.
It enters an operation standby state in which MS can be output.

Therefore, if the fourth counter means 21 does not count the frequency fv up to its set value N ₀ at the instant the end signal eN ₁ is output (unless the count end signal eN ₀ is output), the FF 25 In the set state, the AND circuit 30 outputs “H” to one input terminal.
The AND circuit 33 receiving the level input cannot make its output "H" level, and the output of each AND circuit becomes as shown in FIG. 5, and the memory set pulse MS is output from the signal processing circuit 24. There isn't.

However, if the analog output of the analog signal generator 22 in the initial state is set to the maximum and the oscillation frequency fv of the variable frequency oscillator 23 is the highest, the fourth counter 21
, the second counter 19 has the lowest value N ₁
At the same time as it finishes counting and outputs the count end signal, it also finishes counting the set value N ₀ and outputs the count end signal eN ₀ (see the dotted line part of waveform f in Figure 3).
This means outputting . Then, the count end signal eN ₀ is supplied to the other input terminal of the AND circuit 33 at the same time as the signal processing circuit 24 enters the operation standby state as described above, so that the input/output level of each AND circuit becomes as shown in FIG. The memory set pulse MS (see the dotted line portion of the waveform h in FIG. 3) is output from the exclusive OR circuit 34.

When the memory set pulse MS is output in this way, the memory means 35 simultaneously
The current count value of the counter means 17 is read and stored as the frequency division ratio N, and is also supplied to the programmable frequency divider 11 to set the frequency division ratio (minimum value N ₁ ) of the frequency divider 11.

By setting the frequency division ratio N, the VCO 9 outputs a local oscillation signal having a frequency corresponding to the frequency division ratio N, and supplies it to the mixer 3.

As a result, radio broadcasting at a frequency corresponding to the frequency of the local oscillation signal can be received.

In this case, since the frequency division ratio N is the smallest value, the reception frequency of the radio broadcast is the highest frequency.

Now, as mentioned above, the second counter means counts the lowest value _N1 and sends a count end signal.
At the instantaneous timing (time t ₂ ) of outputting eN ₁ , the fourth counter means 21 has not yet finished counting the set value N ₀ , but after that, the third counter means 20 counts the maximum value N ₂ . For example, if the analog output of the analog signal generator 22 is set so that the fourth counter means 21 finishes counting the set value _N0 at the timing of time _t3 , the fourth counter In accordance with the output of the count end signal eN ₀ (see the solid line of waveform f in FIG. 3) accompanying the end of counting by the means 21, the FF 27 of the signal processing circuit 24 enters the set state, and the signal eN ₀ enters the operation waiting state. The signal is supplied to the other input terminal of the AND circuit 33 in the signal processing circuit 24 .

Therefore, as is clear from FIG. 6, the outputs of the AND circuits 31 to 33 become "H", "L" and "H" levels at the same time as the count end signal eN ₀ is output, so that the exclusive OR circuit 34 A memory set pulse MS is outputted, and the memory means simultaneously reads the current count value of the first counter means 17 as the frequency division ratio N and supplies it to the programmable frequency divider 11.

Further, when the analog signal generator 22 is set so that the analog output is the lowest and the oscillation frequency fv of the variable frequency oscillator 23 is the lowest, the fourth counter 21 is set to the lowest analog output. finishes counting the above maximum value _N2 and outputs the count end signal _eN2 , and at the same time, the set value
After completing N ₀ , a count end signal eN ₀ (see the dashed line portion of the waveform f in FIG. 4) is output.

Then, at the same time as the count end signal _eN0 is output, the FF 27 is inverted to the set state and the output of the output terminal Q is set to the "H" level (see the dot-dashed line in waveform g in FIG. 4). FF to terminal
The output of the AND circuit 29 which has received the "H" level input from 25 becomes "H" level, and at the same time, the count end signal _eN2 is output from the AND circuit 3.
2, the output of the AND circuit 32 becomes "H" level (see FIG. 7), and as a result, the output from the exclusive OR circuit 34, that is, the signal processing circuit 24 is Set pulse MS
is output.

Then, upon receiving this memory set pulse MS, the memory means 35 reads the count value (maximum value N ₂ ) of the first counter means 17 at that time as the frequency division ratio N, and converts it into a programmable frequency divider _. 11 and set the frequency division ratio N.

Based on the setting of the frequency division ratio N, the radio circuit of FIG. 1 receives the lowest frequency radio broadcast.

As described above, the second frequency divider 18 counts N ₂ +n of the output frequency f ₁ at the timing (time t ₅ ) immediately after the fourth counter means 21 finishes counting the maximum value N ₂ When the reset pulse RP (see waveform a in Fig. 4) is output upon completion, the reset pulse RP is supplied to all the first to fourth counter means and the reset input terminal R of each FF, and resets each counter means. and refresh the count value up to that point.
The FF is reset and the signal processing circuit 24 is set to its original initial state.

<Effects of the Present Invention> Since the present invention is constructed as described above, in a synthesizer type radio receiver, the user himself/herself operates the analog signal generator as the channel selection operation means and outputs the analog signal. Since the channel selection operation can be performed by changing the speed, the user can set the channel selection speed arbitrarily.
This allows for more reliable channel selection.

Furthermore, if the analog signal generator is configured with a variable resistor, for example, the resistance value will be maintained at the position of the variable resistor's control knob, so even if the power to the device itself is turned off and then turned on again. This is an excellent feature that allows you to listen to the last broadcast station that was being received without any operations, and can realize the memory function of the last broadcast station that was being received with a simple configuration in a synthesizer-type radio receiver. It is an invention.

[Brief explanation of drawings]

Fig. 1 is a block circuit diagram of a synthesizer type radio receiver according to the present invention, Fig. 2 is a block circuit diagram showing a specific example of a frequency division ratio setting device in the same receiver, and Fig. 3 is a block diagram of the above frequency division ratio. The output waveform diagrams of each component and FIGS. 4 to 7 are provided to explain the operation of the setting device, and are explanations showing the input and output states of each AND circuit. It is a diagram. 8: PLL, 11: Programmable frequency divider, 1
5: second reference oscillator, 18: second frequency divider (reset pulse generator), 19 to 21: second to fourth counter means, 22: analog signal generator, 23: variable frequency oscillator, 24 : Signal processing circuit, 35: Memory means.

Claims (1)

[Claims] 1 Synthesizer type radio reception configured to obtain a local oscillation signal from a phase-locked loop (hereinafter referred to as PLL) and sweep the frequency of the local oscillation signal by varying the division ratio of a programmable frequency divider in the PLL. a reference oscillator that generates a reference signal of a specific frequency; a first counter means that counts the frequency of the reference signal output from the reference oscillator; a reset pulse generator that generates a reset pulse that resets the counter every time the counter is counted up to a certain number larger than the maximum frequency ratio; and a reset pulse generator that counts the frequency of the reference signal. second and third counter means that output a count end signal when the frequency is counted up to the minimum value and the maximum value of the frequency division ratio, respectively, and that are reset by receiving the reset pulse at the same time as the first counter means; an analog signal generator that changes its analog output when externally operated; a variable frequency oscillator that changes its oscillation frequency according to the analog output of the analog signal generator;
When the variable oscillation frequency output from the variable frequency oscillator is counted up to a set value, a count end signal is output, and the fourth counter means is reset by the reset pulse, and the second counter means outputs a count end signal. Then, in the operation waiting state, when a count end signal is obtained from the fourth counter means in the operation waiting state, a signal processing circuit outputs a memory set pulse, and when receiving the memory set pulse, the first counter means A synthesizer type radio receiver comprising memory means for reading and storing a count value at that time and supplying it to the programmable frequency divider as a frequency division ratio.