JPH03188522A - Serial arithmetic circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a serial arithmetic circuit that serially outputs the sum of k (k≧3) serial data as an arithmetic result.

[Conventional technology]

FIG. 2 is a circuit configuration diagram showing a conventional serial arithmetic circuit.

In the same figure, 1 indicates eight serial data inputs DO to D.
7. The first-stage full adders FAII, FAI2, FA13, and FA14 are connected using the serial data inputs (DO, DI), (D2.D3), (D4.D5), and (D6.D7) of input section 1 as addend inputs, respectively. has been done. Then, full adders FAII, FAI2 and full adder FA13. Second-stage full adders FA21 and FA22 are connected, each using the addition output of FA14 as an addend input. The addition outputs of these full adders FA21 and FA2 are used as addend inputs to the third stage (final stage) full adder FA.
31 is connected. The addition output of the full adder FA31 is serially output from the output terminal 3 as the calculation result Dout.

Said full adder FAII~14. FA21. FA22 and FA31 (Hereinafter, when collectively referred to, simply [full adder FA
It's called J. ) are each carry holding register R
11-14. R21, R22, and R31 (hereinafter collectively referred to as simply "carry holding register R")
is connected. The carry holding register R stores the carry output of the corresponding full adder FA, delays the carry output by one bit time, and outputs it as the carry input of the same full adder FA. Then, one carry holding register R and one corresponding full adder FA provide one
It consists of two series adders.

In this way, the serial arithmetic circuit configures the calculating section 10 by connecting serial adders in series with one for every two inputs for the eight serial data inputs DO to D7, and the final stage serial adder The addition output of (FA31.R31) is calculated as D
Outputs serially as out.

Since the serial arithmetic circuit with the above configuration has a three-stage configuration of serial adders, the serial data inputs DO to D7 of the input section 1
The final operation result is output from the output terminal 3 after a three-bit time delay from the time when the most significant bit of the bit data is taken in, respectively.

Therefore, when the least significant bit of the next serial data SDI is fetched into the input section 1 with a delay of less than 3 bits from the time when the most significant bit of the previous serial data SDO was fetched into the input section 1, the serial data SD1
There is a problem in that the influence of the least significant bit of the serial data SDO appears in the calculation result Doll.

A serial arithmetic circuit for solving this problem is shown in FIG. As shown in the figure, in addition to the calculation unit 10, a full adder FAIL'~14'FA21',FA22' and FA
31' and carry holding registers R11' to 14'
Calculation unit 1 consisting of R21', R22' and R31'
A calculating section 10' having exactly the same configuration as that of 0 is connected to the input section 1.

Then, the addition results of the calculation units 10 and 10' are taken into the eight inputs and the B input of the selector 2, respectively.

The selector 2 selectively outputs the addition result (A input) of the calculation unit 10 in the A mode and the addition result (B input) of the calculation unit 10' in the B mode to the output terminal 3 as the calculation result Dout.

With this configuration, from the time to when the most significant bit of the previous serial data SDO was taken into the input section 1,
Next serial data SD1 with delay within 3 bit time
Even if the least significant bit of is taken into input section 1, for example,
With selector 2 set to A mode, input section 1 is connected to calculation section 10 until time to, and after time to, input section 1 is connected to calculation section 10' and desired calculation result Dout is obtained. By continuing to set the selector 2 to A mode until the time, the influence of the least significant bit of the serial data SDI becomes the operation result Dou of the serial data SDO.
It can be output as an accurate calculation result Dout without appearing in t.

[Problem to be solved by the invention]

The conventional serial arithmetic circuit is configured as described above, and it takes (m+n) bit time to finally obtain the addition result of two m-bit serial data as the arithmetic result D out.

- Therefore, if the time interval between successive m-bit serial data sequentially taken into the input section 1 is within n-bit time, as in the serial arithmetic circuit shown in FIG.
There is a problem in that the circuit scale becomes large, such as by providing twice the number of full adders as usual (FIG. 2).

This invention was made to solve the above-mentioned problems, and even if the input time interval of successive serial data is short, without increasing the circuit scale, it is possible to avoid being affected by subsequent serial data. , the object is to obtain a serial arithmetic circuit that can output the arithmetic result of previous serial data.

[Means to solve the problem]

The serial arithmetic circuit according to the present invention is a circuit that serially outputs the sum of k (k≧3) serial data as an arithmetic result, and includes an input section having k 1-bit input terminals; a first calculating section which connects serial adders in series at a ratio of one for every two inputs to the input section and serially outputs the addition result from the final stage serial adder; , serial adders are connected in series at a ratio of one for every two inputs to the carry holding register of the first-stage serial adder connected to the input section, and the addition result is serially transmitted from the final-stage serial adder. The carry output of the serial adder and the corresponding serial adder of the first calculation unit of the corresponding stage are output to the carry holding register of the serial adder of the second calculation unit. The first one selectively gives one of the carry outputs.
and a second selection means for selectively outputting one of the addition results of the first calculation section and the addition results of the second calculation section as the calculation result. There is.

[Effect]

In this invention, the following processing becomes possible. Until the input time of the most significant bit of the serial data applied to the input section, the first selection means selects the carry holding register of the serial adder of the second calculation section from the corresponding first calculation section of the corresponding stage. The carry output of the serial adder is given, and the second
The selection means outputs the addition result of the first calculation section as the calculation result. Then, when the input time of the most significant bit of the serial data has passed, the first selection means selects the second
The carry output of the serial adder is given to the carry register of the serial adder of jf12 by the second selection means.
By outputting the addition result of the calculation section as the calculation result, addition processing is performed on the output of the carry holding register of the first stage serial adder of the first calculation section.

〔Example〕

FIG. 1 is a circuit diagram showing a serial arithmetic circuit according to an embodiment of the present invention.

In the same figure, 1 indicates eight serial data inputs DO to D.
7. The first-stage full adders FAIL, FAI2, FA13, and FA14 are connected with the serial data inputs (DO, Di), (D2.D3), (D4.D5), and (D6.D7) of input section 1 as addend inputs, respectively. ing. Then, full adders FAII, FAI2 and full adder FA13. Second-stage full adders FA21 and FA22 are connected, each using the addition output of FA14 as an addend input. The third stage (final stage) full adder FA3 uses the addition outputs of the full adders FA21 and FA2 as an addend input.
1 is connected. The addition output of this full adder FA31 is connected to eight inputs of the selector 20.

The full adders FA11-14. FA21. FA22 and FA31 each have a carry holding register R11.
~14. R21, R22 and R31 are connected.

The carry holding register R stores the carry output of the corresponding full adder FA, delays the carry output by one bit time, and outputs it as the carry input of the same full adder FA. One serial adder is constituted by one carry holding register R and one corresponding full adder FA.

Further, the first-stage full adders FAII-14 are further connected with carry holding auxiliary registers 5RII-5R14. Carry holding aid SR11~5R
14 stores the carry outputs of the corresponding full adders FA11 to FA14, delays the stored carry outputs by 1 bit time, and the carry outputs stored in 5R11 and 5R12 are used as the addend input of the auxiliary full adder 5FA21, and 5R13
And the carry output stored in 5R14 is sent to the auxiliary full adder 5.
It is used as the addend input of FA22.

The addition outputs of the auxiliary full adders 5FA21 and 5FA22 are:
It becomes the addend input of the auxiliary full adder 5FA31. Then, the addition output of the auxiliary full adder 5FA31 is connected to the B input of the selector 20.

In addition, auxiliary full adders 5FA21, 5FA22 and 5FA
The carry output of 31 is the selector 21, 22 and B of 31.
given to the input. These selectors 21, 22 and 3
A full adder FA21. FA22 and FA
31 carry outputs are provided. Selector 21.22
and 31 selectively output one of the carry outputs obtained from the A input and the B input to the carry holding auxiliary registers 5R21, 22, and 31. The carry holding auxiliary registers 5R21, 22 and 31 delay the stored carry output by one bit time and output it as a carry input to the corresponding auxiliary full adders 5FA21, 22 and 31. Further, the selector 20 selectively selects one of the addition outputs obtained from the eight inputs and the B input as the calculation result D ou
It is output from output terminal 3 as t.

In this way, the serial arithmetic circuit is configured by connecting serial adders consisting of a carry holding register R and a full adder FA in series for the eight serial data inputs DO to D7 at a ratio of one for every two inputs. A serial adder consisting of a carry holding auxiliary register SR, an auxiliary full adder SFA, and a selector is connected in series to the outputs of the calculated calculation unit and carry holding auxiliary registers 5R11 to 5R14 at a ratio of one for every two inputs. An auxiliary calculation section configured in connection is provided. Then, the selector 20 selectively selects the addition result of one of the calculation section and the auxiliary calculation section as the calculation result D out
Output as .

In such a configuration, normally the selectors 20-. 2
1.22 and 31 select the bit data obtained from the eight inputs and output the addition result of the calculation section as the calculation result D out. At this time, carry holding auxiliary register 5R2
1, 22 and 31, full adder FA21.22 and 31
The carry output of is stored. This means that when switching from normal mode to carry operation mode, which will be described later, the auxiliary calculation section
This is done in order to be able to accurately derive the addition result by taking into account the carry output of the serial data that has been input up to that point. Then, when the time to when the most significant bit of the previous serial data SDO was taken into the input section 1 has passed, the mode shifts to carry operation mode, and the selectors 20 to 22 and 31 select the bit data obtained from the B input. The addition result of the auxiliary calculation section is output as the calculation result D out.

Since the addition process of the auxiliary calculation section is performed based on the outputs of the carry holding auxiliary registers 5R11 to 5R14,
Next, the time at which the least significant bit of the serial data SDI taken into the input section 1 influences the addition processing of the serial data SDO in the auxiliary calculation section is longer than that of the conventional This will result in a one pit time delay. Therefore, from time to 3
Even if the least significant bit of the serial data 8-Dl is captured with a delay of more than the bit time, the effect of the least significant bit of the serial data SDI is calculated as the calculation result D of the serial data association DO.
It can be made not to appear in out.

Furthermore, the number of full adders can be reduced by four compared to the serial arithmetic circuit shown in FIG. 3, so the circuit scale can be reduced. In other words, if the serial arithmetic circuit that adds two m-bit serial data is configured as in this embodiment, the number of full adders will be reduced by two compared to the serial arithmetic circuit configured as shown in Figure 3. In this embodiment, a serial arithmetic circuit that adds 8 (-23) pieces of serial data has been described, but the present invention is not limited to this. In addition, full adders FA and SFA, carry holding registers R and SR, and selectors 20 and 21
．． 22 and 31 may be of any type as long as they fulfill their functions.

〔Effect of the invention〕

As explained above, according to the present invention, the following processing becomes possible. Until the input time of the most significant bit of the serial data applied to the input section, the first selection means selects
The carry output of the serial adder of the corresponding first calculation unit of the corresponding stage is given to the carry holding register of the serial adder of the second calculation unit, and the second selection means selects the carry output of the serial adder of the first calculation unit of the corresponding stage. Output the result as a calculation result. Then, when the input time of the most significant bit of the serial data has passed, the first selection means applies the carry output of the serial adder to the carry register of the second serial adder, and the second selection means applies the carry output of the serial adder to the carry register of the second serial adder. By outputting the addition result of the second calculation section as the calculation result, addition processing is performed on the output of the carry holding register of the first stage serial adder of the first calculation section.

The second calculation unit performs addition processing based on the output of the carry holding register of the first stage serial adder of the first calculation unit, so that in consecutive serial data, the later serial data is different from the previous serial data. The time that affects the operation result of serial data can be delayed by 1 bit time, which is the time for passing through the carry holding register. As a result, even if the input time interval of successive serial data is shortened by 1 bit time compared to the conventional method, the calculation result of the previous serial data can be output without being affected by the subsequent serial data.

Further, since the number of first-stage serial adders is kept to be the same as the number of first-stage serial adders in a serial arithmetic circuit with a normal configuration, the circuit scale does not increase significantly.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a serial arithmetic circuit according to an embodiment of the present invention, and FIGS. 2 and 3 are circuit diagrams showing conventional serial arithmetic circuits. In the figure, 1 is an input section, 20, 21, 22, and 31 are selectors, 3 is an output terminal, FA11-14, FA21.
FA22 and FA31 are full adders, εFA21, 5FA
22 and 5FA31 are auxiliary full adders, R11 to 14. R
21, R22 and R31 are carry holding registers, S
R11 to 14 degrees 5R21, 5R22 and 5R31 are auxiliary registers for holding carry. Note that the same reference numerals in each figure indicate the same or corresponding parts. Figure 2

Claims (1)

[Claims] (1) A serial arithmetic circuit that serially outputs the addition total value of k (k≧3) pieces of serial data as an arithmetic result, comprising an input section having k 1-bit input terminals, and an input section for the input section. , a first calculation unit which connects series adders in series at a ratio of one to two inputs and serially outputs the addition result from the final stage serial adder; and the input unit in the first calculation unit. The serial adder is connected in series at a ratio of one to two inputs to the carry holding register of the first stage serial adder connected to the second stage, and the addition result is serially output from the final stage serial adder. and a carry holding register of the serial adder of the second calculation unit, the carry output of the serial adder and the carry output of the corresponding serial adder of the first calculation unit of the corresponding stage are stored in the carry holding register of the serial adder of the second calculation unit. , a first selection means for selectively giving one carry output, and selectively selecting one of the addition results of the first calculation unit and the addition result of the second calculation unit as the operation result. a serial arithmetic circuit comprising a second selection means for outputting an output to the second selection means;