JPH03188523A - multiplication circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a multiplication circuit for two's complement digital data and absolute value representation digital data.

BACKGROUND OF THE INVENTION In recent years, digital processing has been used in various fields, especially general-purpose digital signal processors (DSPs).
) and in digital filter technology, multiplication functions have come to be used frequently.

Conventionally, these multiplication functions are often implemented as parallel multiplication circuits.

A conventional multiplication circuit will be described below.

FIG. 5 is a circuit diagram of a conventional multiplication circuit, 51 to 59
are the input data (XO"X2...2's complement representation) and the coefficient data (yo"y2...absolute value representation)
Logical product (AND) gate for creating a product with, 60~
62 is an inverter for inverting coefficient data;
3 to 74 are full adders for adding various types.

This multiplier circuit multiplies 2's complement data, which is often used in digital filters, etc., with coefficient data expressed as an absolute value. 2n-1.
2”Yk crab-0, latitude Ok+0 are obtained.

Further, the coefficients are treated as 1 or less, that is, as decimal numbers.

Problem to be Solved by the Invention However, in the above conventional configuration, (nxm) A
ND gate, full adder, m inverters, and m
This has the problem of requiring multiple full adders, resulting in a very large circuit scale and increased costs.

The present invention solves the above-mentioned conventional problems, and aims to provide a multiplication circuit that can realize multiplication between two's complement and absolute value representation data and has a small circuit scale.

Means for Solving the Problems To achieve this object, the multiplication circuit of the present invention performs EOR inversion of data by the MSB of two's complement data, and serial multiplication of its output with data in absolute value representation. It consists of a multiplier and a circuit that detects zero in the multiplication result.

Effect With this configuration, data in two's complement representation with positive and negative values are all converted to positive values by EOR, and serial multiplication can be realized. The number of bits required is only m, which is the number of bits of multiplication coefficient data expressed in absolute value, and the circuit scale can be reduced.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a multiplication circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram of the serial multiplier of FIG. 1, FIG. 3 is a circuit diagram of the zero detection circuit of FIG. 1, and FIG. is an explanatory diagram of the operation of a serial multiplier.

In FIG. 1, 11 is a serial multiplier for inverting data in two's complement representation, EOR 112 is a serial multiplier for multiplying the output of EORII by a coefficient in absolute value representation, and 13 is for holding the output of serial multiplier 12. 15 is a zero detection circuit that detects that the value of shift register 13 is zero; 14 is shift register 13;
EOR 181 is a serial input terminal for data in two's complement representation, 82 is an MSB input terminal for inputting the MSB of data in two's complement representation, and 83 is a switching signal for controlling the serial multiplier and zero detection circuit. 84 is a terminal for inputting coefficients, 85 is a signal output terminal, and 86 is a shift clock input terminal for a serial multiplier and a shift register.

In FIG. 2, 21 to 25 are D flip-flops for shifting input data, 26 to 29 are AND gates that receive the outputs and coefficients of the D flip flops, and 30 to 32 are outputs of the AND gates. 33 to 35 are D flip-flops to hold the carry output of the full adder, 36 is a selector, 83
84 is a switching signal input terminal, 84 is a coefficient input terminal, 86 is a shift clock terminal thereof, and 87 is a serial input terminal.

In FIG. 3, 41 is a large power NOR gate for detecting all zeros of input data, and 42 is a NOR gate.
Inverter for controlling gate 41, 43 is NOR
AND with the output of gate 41 and MSB data as input
gate, 44 is a D flip-flop for holding the output of AND gate 43, 89 is a data input terminal, 9
0 is a zero detection signal terminal.

The operation of the multiplication circuit of this embodiment will be explained with specific numerical examples.

First, n=5. Assume that m=4, input digital data in two's complement representation is "10010(B)-14", and coefficient data in absolute value representation is "1010<s>". Here, all coefficients are 1
and “1010(B)” is “0.1010<s
>=10/16". Of the input two's complement digital data, excluding the MSB <(n-1
) bit is input from the serial input terminal 81 to the least significant bit (L
SB) side is input first, and the MSB data is input from the MSB input terminal 82.

Data input from the serial input terminal 81 is inverted according to the MSB at EORll in FIG. 1, and all data is converted into positive values. That is, input data “0010(B)=
14” is converted to “1101(B)=13”.

Next, the serial multiplier 12 multiplies "1101(B)=13" and "0.1010(B)=10/16".

This operation will be explained with reference to FIG. Figure 4 shows 5 bits of D flip-flops 21 to 25 that constitute a shift register and carry/save registers 33 to 3503.
3 is a truth diagram showing the states of bits and input terminals A and B of the selector 36. FIG. It is assumed that all are cleared in the initial state.

First, when the LSB of data "1101" enters the D flip-flop 21 constituting the shift register, the fourth
The state shown in (A) in the figure is reached, but the input terminal A of the selector 36
, B both remain O.

Next, the second bit of data is D, which constitutes the shift register.
When it enters the flip-flop 21, it becomes the state (B), and the input terminal B of the selector 36 becomes 1 due to the product of the second bit of the coefficient and the first bit of the data. Similarly,
Data is input to a shift register, a product of this data and coefficient data is generated, and the products are added to realize multiplication.

As a result, the values output to the input terminals A and B of the selector 36 are A=1101.0000 B=1000.0010, and the upper 4 bits of the integer part are A=110.
1(B)=13 B=1000<a>=8 where A is the original input data, B is the multiplication result with the coefficient, and the selector 36 selects the input terminal B by the switching signal.
is selected, "1000(a)=8" is held in shift-L/di, 113 in FIG.

Next, by inverting the multiplication result thus obtained using EOR again according to the MSB input from the input terminal 82, it is necessary to return the data that was originally a negative value to the multiplication result as negative data. However, if the data that was originally a negative value becomes smaller than 1 during the multiplication process, that is, if it becomes less than or equal to B=OOO0,1111, the value in the shift register 13 will be all zeros, and the MSB will remain as is. If it is inverted according to the following, "1111(B)=1" will be obtained. Therefore, a zero detection circuit 15 is provided, and a multi-input NOR shown in FIG.
The gate 41 detects that the values in the shift register 13 are all zeros, and in the case of all zeros, the zero detection signal 90 of the zero detection circuit 15 is set to "L" level regardless of the MSB value. The value of the shift register 13 is output as is without inversion at EOR.

For which numerical example, from the multiplication number result "1000(a) = 8", NOR gate 4 in Figure 3
The output of 1 becomes “H”, and the AND gate 4
The output of EOR1 in FIG.
4, the value of the shift register 13 is “1000(B)=
8” is inverted and “0111” is output. This is M
When expressed including SB, it shows "10111(B)=9".

In this way, 14x 10/16=-8, 75<-9 (round down) can be obtained.

As described above, according to this embodiment, by making the multiplication circuit a serial multiplier and performing all multiplications using positive numbers, the circuit size can be increased (without increasing the size of the circuit), and two's complement representation and absolute value representation can be performed. Data multiplication can be realized.

Effects of the Invention According to the present invention, a serial multiplier is used in the multiplication circuit, and an EO for converting all multiplication data into positive values is used.
By providing R, it is possible to realize multiplication of data in two's complement representation and coefficient data in absolute value representation without increasing the circuit scale.In addition, by providing a zero detection circuit, multiplication can be realized without increasing the circuit scale. Negative data that becomes smaller than 1 in the process is not inverted again (0 can be output,
Furthermore, by providing a selector in the serial multiplication circuit, it is possible to realize an excellent multiplication circuit that can select either the multiplication result or the original data.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a multiplier circuit in one embodiment of the present invention, FIG. 2 is a circuit diagram of a serial multiplier in FIG. 1, and FIG.
4 is a truth diagram for explaining the operation of a serial multiplier, and FIG. 5 is a circuit diagram of a conventional multiplier circuit. 11.14... EOR, 12... Serial multiplier, 13... Shift register, 15
...Zero detection circuit, 21-25.33-35.
...D.Flip-flop, 26-29...
...AND, 30-32...Full adder, 3
6...Selector, 41...Multi-input N0
R142...Inverter, 43...A
ND, 44...D Flip Flip Flip, 51
~59...AND, 60-62...Inverter, 63-74...Full adder, 81.
...Serial input terminal, 82 ...MSB
Input terminal, 83...Switching signal, 84...
・Coefficient, 85...Serial output, 86...
...Shift clock, 87... Serial input of multiplier, 88... Serial output of multiplier, 8
9...Data input terminal, 90...Zero detection signal.

Claims (2)

[Claims] (1) Exclusive OR (EOR) that inverts (n-1) bits excluding the MSB using the most significant bit (MSB) of an n-bit digital signal in two's complement representation, and its output and coefficient. A serial multiplier that performs serial multiplication, a shift register that holds the output of this serial multiplier, a zero detection circuit that detects that the value of this shift register is zero, and a A multiplication circuit comprising an EOR for inverting the output of a shift register. (2) The multiplication circuit according to claim 1, wherein the serial multiplier includes a selection circuit that is controlled by a switching signal and selects input data or a multiplication result as output data.