JPH03188569A - Analysis system for fan-in/out designing rule of logic circuit - Google Patents

Abstract

PURPOSE:To reduce the memory capacity by providing a symbol fan-in/out information storage means, a logic circuit connection information storage means, a hierarchy control means, a logic circuit designing rule analyzing means, an automatic symbol fan-in/out information generating means, and an analyzing result output means. CONSTITUTION:If a fan-in/out error is detected, the error subject area is designated. Then an automatic symbol fan-in/out information generating means 5 produces the fan-in/out information which defines a single module as a single symbol based on the logic circuit connection information equivalent to a single module stored in a logic circuit connection information means 2 related to a module selected under the control of a hierarchy control means 3 and the fan-in/out information on each symbol stored in a fan-in/out information storage means 1. Then the produced fan-in/out information is stored in the means 1. At the same time, a logic circuit designing rule analyzing result output means 6 outputs the error subject area designated by a logic circuit designing rule analyzing means. Thus it is possible to reduce the capacity of a memory which is used for analysis of a logic circuit of a large scale.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a fan-in fan-out design rule analysis method for logic circuits, and in particular to a fan-in fan-out design rule for logic circuits that can analyze large-scale logic circuits. Regarding analysis method.

[Conventional technology]

Conventionally, fan-in fan-out design rule analysis methods for logic circuits include symbol fan-in fan-out information storage means and logic circuit connection information storage means.

It was configured to include a logic circuit design rule analysis means and a logic circuit design rule analysis result output means.

Here, the logic circuit connection information storage means does not divide the logic circuit into logically organized functional description units (modules) and store the logic circuit connection information hierarchically, but the logic circuit connection information is stored in only one layer. I remembered the information.

[Problems to be Solved by the Invention] In the conventional logic circuit fan-in fan-out design rule analysis method described above, the logic circuit connection information is stored in only one layer by the logic circuit connection information storage means, so it is difficult to solve the problem on a large scale. A drawback is that a large amount of memory is required to perform fan-in fan-out design rule analysis for logic circuits (this requirement limits the scale of logic circuits that can be analyzed). .

In view of the above-mentioned points, an object of the present invention is to provide a fan-in system for logic circuits that does not limit the scale of logic circuits that can be analyzed and allows fan-in fan-out design rule analysis of logic circuits even for large-scale logic circuits. The purpose of the present invention is to provide a fan-out design rule analysis method.

[Means to solve the problem]

The fan-in fan-out design rule analysis method for logic circuits of the present invention includes a symbol fan-in fan-out information storage means for storing fan-in fan-out information for each symbol, which is basic in the fan-in fan-out design rule analysis for logic circuits. , a logic circuit connection information storage means for hierarchically storing logic circuit connection information of the logic circuit for each module, and processing the logic circuit connection information of each module in the logic circuit connection information storage means from a module in a lower hierarchy. Logic circuit connection information for one module in the logic circuit connection information storage means related to the module selected by the control by the hierarchy control means and in the symbol fan-in fan-out information storage means. A logic circuit design rule that specifies the error target part when a fan-in fan-out error is detected by analyzing the fan-in fan-out design rule of the logic circuit corresponding to the module based on the fan-in fan-out information for each symbol. analysis means, logic circuit connection information for one module in the logic circuit connection information storage means relating to the module selected under control by the hierarchical control means, and a fan for each symbol in the symbol fan-in fan-out information storage means; 1 module for this 8 yen module based on infan-out information.
symbol fan-in fan-out information automatic generation means for generating fan-in fan-out information regarded as a symbol and storing the fan-in fan-out information in the symbol fan-in fan-out information storage means; and the logic circuit design rule analysis means. and logic circuit design rule analysis result output means for outputting information indicating the designated error target portion.

[Effect]

In the fan-in fan-out design rule analysis method for logic circuits of the present invention, the symbol fan-in fan-out information storage means stores fan-in fan-out information for each symbol, which is basic in the fan-in fan-out design rule analysis for logic circuits. , the logic circuit connection information storage means hierarchically stores the logic circuit connection information of the logic circuits for each module, and the hierarchy control means stores the logic circuit connection information of each module in the logic circuit connection information storage means for the modules in the lower hierarchy. The logic circuit design rule analysis means processes one module's worth of logic circuit connection information and symbol fan-in fan-out information in the logic circuit connection information storage means for the module selected under the control of the hierarchical control means. Analyzes the fan-in fan-out design rules for the logic circuit corresponding to the module based on the fan-in fan-out information for each symbol in the storage means, and if a fan-in fan-out error is detected, specifies the error target part, The symbol fan-in fan-out information automatic generation means generates one module's worth of logic circuit connection information in the logic circuit connection information storage means and the symbol in the symbol fan-in fan-out information storage means related to the module selected by the control by the hierarchical control means. Based on the fan-in fan-out information for each module, fan-in fan-out information is generated regarding one module regarding the module in question as one symbol, the fan-in fan-out information is stored in the symbol fan-in fan-out information storage means, and the logic The circuit design rule analysis result output means outputs information indicating the error target portion specified by the logic circuit design rule analysis means.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the fan-in fan-out design rule analysis method for logic circuits of the present invention. A fan-in fan-out information storage means 1, a logic circuit connection information storage means 2,
Hierarchical control means 3, logic circuit design rule analysis means 4,
The system includes symbol fan-in/fan-out information automatic generation means 5 and logic circuit design rule analysis result output means 6.

FIG. 2(a) is a diagram showing an example of a logic circuit (logic circuit 7) on which fan-in fan-out design rule analysis is performed according to the present embodiment.

FIG. 2(b) is a diagram showing each module (modules 8 to 10) when the logic circuit connection information of the logic circuit 7 is stored hierarchically for each module. In FIG. 2(b), module 8 is a module in the upper layer,
Modules 9 and 10 are modules in a lower hierarchy (the hierarchy of module 9 and the hierarchy of module IO are at the same level).

Next, the operation of the fan-in fan-out design rule analysis method for the logic circuit of this embodiment configured as described above will be described.

The symbol fan-in fan-out information storage means 1 stores fan-in fan-out information for each symbol, which is the basis for fan-in fan-out design rule analysis of a logic circuit to be analyzed.

The logic circuit connection information storage means 2 stores logic circuit connection information of the logic circuit to be analyzed hierarchically for each module.

The hierarchy control means 3 performs control to process the logic circuit connection information of each module stored in the logic circuit connection information storage means 2 from the module in the lower hierarchy (selecting from the module in the lower hierarchy) control J).

The logic circuit design rule analysis means 4 stores logic circuit connection information for one module in the logic circuit connection information storage means 2 related to the module selected by the hierarchy control means 3 and the symbol fan-in fan-out information storage means 1. Based on the fan-in fan-out information for each symbol, a fan-in fan-out design rule analysis of the logic circuit corresponding to the module is performed. Specify the location where the error occurred (error target location).

The symbol fan-in fan-out information automatic generation means 5 generates the logic circuit connection information for one module in the logic circuit connection information storage means 2 related to the module selected by the hierarchy H111 means 3 and the symbol fan-in fan-out information storage means 1. Based on the fan-in fan-out information for each symbol stored in the symbol fan-in fan-out information stored in The information is stored (stored) in the information storage means l.

The hierarchy control means 3 sequentially selects the modules as described above from the lower hierarchy to the upper hierarchy.

The logic circuit design rule analysis means 4 and the symbol fan-in fan-out information automatic generation means 5 are connected to the hierarchical control means 3.
The above-described process is repeated based on the selection made by .

The logic circuit design rule analysis result output means 6 outputs information indicating the error target portion specified by the logic circuit design rule analysis means 4.

Next, with reference to FIGS. 2(a) and 2(b), the operation when the fan-in fan-out design rule analysis of the logic circuit 7 is performed will be described.

In this case, the symbol fan-in fan-out information storage means 1 stores fan-in fan-out information for each symbol 11 to 22 of the logic circuit 7. Further, the logic circuit connection information storage means 2 stores the logic circuit connection information of the modules 8 to 10 in a hierarchical manner.

The hierarchical control means 3 first selects the logic circuit connection information of the module 9 in the logic circuit connection information storage means 2, and uses the logic circuit design rule analysis means 4 and the symbol fan-in fan-out information automatic generation means 5. to start.

The logic circuit design rule analysis means 4 analyzes the logic circuit connection information of the module 9 in the logic circuit connection information storage means 2 and the fan-in fan-out for each symbol 11 to 22 stored in the symbol fan-in fan-out information storage means 1. Based on this information, a fan-in fan-out design rule analysis of the logic circuit corresponding to the module 9 is performed.

In this fan-in fan-out design rule analysis, it is assumed that a fan-in fan-out error is detected in the connection between the terminal 27 of symbol 12 and the terminal 30 of symbol 15. When such a fan-in fan-out error is detected, the logic circuit design rule analysis means 4
specifies symbols 12 and 15 and terminals 27 and 30 as error target parts.

On the other hand, the symbol fan-in fan-out information automatic generation means 5 generates a module based on the logic circuit connection information of the module 9 and the fan-in fan-out information for each symbol 11 to 22 stored in the symbol fan-in fan-out information 1. Fan-in fan-out information is generated in which 9 is regarded as one symbol (symbol 52). That is,
The value of the terminal 44 of the symbol 52 is the sum of the fan-in numbers of the terminals 24, 25 and 26 connected to the external input/output terminal (external input terminal) 57, and the value of the terminal 45 of the symbol 52 is the external input/output. Terminal (external output terminal) 58
Find the minimum fanout number of terminals 28 and 32 connected to the terminal 3 connected to the external input/output terminal (external output terminal) 59 as the value of the terminal 46 of the symbol 52.
The minimum value of the fan-out number of 3 is determined, and these values are stored in the symbol fan-in fan-out information storage means 1 as the fan-in fan-out information of the symbol 52.

Second, the hierarchical control means 3 selects the logic circuit connection information of the module IO in the logic circuit connection information storage means 2,
Logic circuit design rule analysis means 4 and symbol fan-in fan-out information automatic generation means 5 are activated.

The logic circuit design rule analysis means 4 analyzes the module IO based on the logic circuit connection information of the module 10 and the fan-in fan-out information for each symbol 11 to 22 stored in the symbol fan-in fan-out information storage means 1.
Analyze fan-in fan-out design rules for logic circuits corresponding to .

In this fan-in fan-out design rule analysis, it is assumed that no fan-in fan-out errors are detected.

On the other hand, the symbol fan-in fan-out information automatic generation means 5 generates a module based on the logic circuit connection information of the module 10 and the fan-in fan-out information for each symbol 11 to 22 stored in the symbol fan-in fan-out information 1. Fan-in fan-out information is generated by regarding 10 as one symbol (symbol 53), and the fan-in fan-out information is stored in the symbol fan-in fan-out information storage means l.

Thirdly, the hierarchical control means 3 selects the logic circuit connection information of the module 8 in the logic circuit connection information storage means 2 and uses the logic circuit design rule analysis means 4 and the symbol fan-in fan-out information automatic generation means 5. to start.

The logic circuit design rule analysis means 4 extracts the logic circuit connection information of the module 8 and the fan-in fan-out information (symbol fan-in fan-out information automatic) for each symbol 11 to 22 stored in the symbol fan-in fan-out information storage means l. (including fan-in fan-out information of the symbols 52 and 53 previously generated by the generating means 5)
Based on this, a fan-in fan-out design rule analysis of the logic circuit corresponding to module 8 is performed.

In this fan-in fan-out design rule analysis, it is assumed that no fan-in fan-out errors are detected.

On the other hand, the symbol fan-in fan-out information automatic generation means 5 generates a module based on the logic circuit connection information of the module 8 and the fan-in fan-out information for each symbol 11 to 22 stored in the symbol fan-in fan-out information 1. 8 is regarded as one symbol, and the fan-in fan-out information is stored in the symbol fan-in fan-out information storage means 1. (to facilitate fan-in fan-out design rule analysis of corresponding logic circuits).

The logic circuit design rule analysis result output means 6 outputs information (in this case, the symbol 12 and 15 and information indicating terminals 27 and 30).

〔Effect of the invention〕

As explained above, the present invention provides a symbol fan-in fan-out information storage means, a logic circuit connection information storage means 1 layer 1 m control means, a logic circuit design rule analysis means, a symbol fan-in fan-out information automatic generation means, and a logic circuit design By providing a rule analysis result output means, the memory capacity for performing fan-in fan-out design rule analysis of large-scale logic circuits can be reduced, and the scale of logic circuits that can be analyzed is limited. This has the effect that fan-in fan-out design rule analysis of logic circuits can be performed even for large-scale logic circuits.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIGS. 2(a) and (b) show the specific operation of the fan-in fan-out design rule analysis method for the logic circuit shown in FIG. It is a figure for explaining. In the figure, 1...Symbol fan-in fan-out information storage means, 2...Logic circuit connection information storage means, 3...
Hierarchical control means, 4 ・ ・ ・ ・ ・ 5 ・ ・ ・ ・ ・ 6 ・ ・ ・ ・ 7 ・ ・ ・ ・ 8-10 ・ 11-22゜23-5 l ・ 54-64 ・ Logic circuit design rules analysis means, symbol fan-in fan-out information automatic generation means, logic circuit design rule analysis result output means, logic circuit, module, 52.53 symbol, terminal, external input/output terminal.

Claims (1)

[Claims] Symbol fan-in fan-out information storage means for storing fan-in fan-out information for each symbol, which is basic in fan-in fan-out design rule analysis of logic circuits; a logic circuit connection information storage means for hierarchically storing logic circuit connection information for each module; a hierarchical control means for controlling the logic circuit connection information of each module in the logic circuit connection information storage means to be processed from a module in a lower hierarchy; Logic circuit connection information for one module in the logic circuit connection information storage means relating to the module selected under control by the hierarchical control means and fan-in fan-out information for each symbol in the symbol fan-in fan-out information storage means; a logic circuit design rule analysis means for analyzing a fan-in fan-out design rule of a logic circuit corresponding to the module based on the above and specifying an error target part when a fan-in fan-out error is detected; and control by the hierarchical control means. for the module selected based on logic circuit connection information for one module in the logic circuit connection information storage means and fan-in fan-out information for each symbol in the symbol fan-in fan-out information storage means for the module selected by. 1
symbol fan-in fan-out information automatic generation means for generating fan-in fan-out information regarding a module as one symbol and storing the fan-in fan-out information in the symbol fan-in fan-out information storage means; and the logic circuit design rule. 1. A fan-in fan-out design rule analysis method for a logic circuit, comprising logic circuit design rule analysis result output means for outputting information indicating an error target portion specified by the analysis means.