JPH0318924A - Floating point addition and subtraction circuit - Google Patents

Abstract

PURPOSE:To shorten the computation time by inverting the result of subtraction when this result obtained between the exponent parts of two numbers is negative and shifting the value stored in a shift register by an extent equal to the inverted result of subtraction and then shifting the value to the right by one bit. CONSTITUTION:The data (a) and (b) on the exponent parts are used as the inputs of a subtractor 1, and a carry signal (e) is equal to '1' and '0' when the result of subtraction is negative and positive respectively. Then the smaller one of data on the mantissa parts (c) and (d) is used as the input data of a shift register 6 based on the signal (e) and the other data is used as the input data of an adder/subtractor 11 respectively. When the signal (e) is equal to '0' and '1', the result of subtraction of the subtractor 1 is stored as it is in a shift counter 5 and the inverted result of subtraction of the subtractor 1 is stored in the counter 5 respectively. Then the value of the register 6 is shifted to the right by an extent equal to the value of the counter 5. Furthermore the shifted result is shifted more to the right by one bit when the signal (e) is equal to '1'. As a result, a process to obtain two complements can be omitted and the digit matching process can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic circuit that performs digit alignment that occurs when performing addition and subtraction of floating point numbers.

[Conventional technology]

FIG. 2 is a diagram showing a conventional technique. The case of adding floating point numbers will be explained with reference to this figure.

a and b represent the exponent parts of floating point numbers X and Y, and C2d represents the mantissa part. a, c is a floating point number with summand X, b
, d is a floating point number with addend Y.

1 is a subtracter that calculates the difference between the exponent parts "a-b" of two types of floating point numbers and generates a carry signal. A selector 2 selects which of the mantissa parts c and d of two types of floating point numbers is input to the shift register A6 and which is input to the adder/subtractor 11 by a carry signal of 1. 3 is a selector that selects the larger exponent part of the input data and stores it in the exponent part result register 12; 4 inverts the result if the carry signal is 1' and then adds it to adder 1.
14 is an adder that adds +1 to the inverted value when the carry signal e of 3 is "1". be.

A shift counter 5 has information on how many bits the value of the shift register 6 is to be shifted.

6 is a shift register A that stores the value to be shifted.

7 is a barrel shifter that shifts the value of the shift register A6 according to the value of the shift counter.

A shift result register 10 stores the result shifted by the barrel shifter 7. Reference numeral 11 denotes an adder/subtractor that adds or subtracts the mantissa data whose digits have been aligned according to 1 to 14 above and another mantissa data whose digits have not been aligned. 12
is an exponent result register that stores the exponent result.

13 is a mantissa result register that stores the mantissa result.

Next, we will explain the operation. First, regarding the operation of the mantissa part, data a and b of the exponent part are input to the subtracter 1, and a subtraction of "a-b" is performed on these two numbers. At this time, if the result is negative, the carry signal e becomes "1 degree", and if it is positive, it becomes 0'.

Then, based on the carry signal e of the mantissa parts c and d, the mantissa data of the smaller exponent part is input to the shift register A6, and the other mantissa data is used as the input data of the adder/subtractor 11. Next, if the carry signal e is 0', the result of the subtraction of the exponent part of 1 is stored as is in the shift counter 5, and if it is 1', the inverted value of the subtraction result of the exponent part of 1 is taken, and the value obtained by adding +1 to it is stored in the shift counter 5. Store. Once the value of the shift counter 5 is determined, the value of the shift register 6 is shifted to the right by the value of the shift counter 5. Finally, the shift result and the unaligned input data are added or subtracted, and the result is stored in the mantissa result register 13. Next, the exponent parts a and b of the two input data are determined by the carry signal e, and the larger one is stored in the exponent part result register 12.

[Problem to be solved by the invention]

Conventional addition and subtraction of floating-point numbers uses the result of subtracting the exponent part of two numbers as the number of shifts of the mantissa when performing digit alignment as described in [Prior Technology], but the result of this subtraction is negative. In this case, it cannot be used as a shift number as is (the shift number must be an absolute value), so it was necessary to take the two's complement. To take two's complement, we must first invert the data and then add +1 to it. When this addition is executed, it takes time to determine the value of the number of shifts, resulting in a problem that the execution time of the operation itself becomes longer.

The present invention has focused on the above-mentioned problems and aims to reduce the time required for digit alignment processing when adding and subtracting floating point numbers by eliminating the time-consuming process of calculating two's complement numbers.

[Means to solve the problem]

In order to solve the above-mentioned problems, the present invention solves the problem that when determining the number of shifts of the mantissa when performing digit alignment during addition and subtraction of floating point numbers, the result of subtracting the exponent part of two numbers is negative. Instead of taking the 2's complement and using it as the number of shifts, we can invert the result of the subtraction, shift the value in shift register A by that value, and then shift the result after the shift by 1 bit to the right. It is characterized by correcting the results.

〔Example〕

FIG. 1 is a diagram showing an embodiment of the present invention. This embodiment will be explained with reference to FIG. 3 (contents of each register, etc. in the case of addition of floating point numbers) showing the contents of each register and signal when a value is actually input.

a and b indicate the exponent parts of the two input data, and C1d indicates the mantissa part. a, floating point number with summand X in C, b
, d is a floating point number with addend Y.

1 is a subtracter that calculates the difference between the exponent parts "a-b" of two types of floating point numbers and generates a carry signal e. 2 is a subtracter that calculates the difference between the exponent parts "a-b" of two types of floating point numbers and generates a carry signal e.
This is a selector that selects which one is input to the shift register A6 and which one is input to the adder 11. 3 is a selector which selects the larger exponent part of the input data in response to a carry signal and stores it in the exponent part result register 12; 4 is a circuit that inputs the inverted value of the result into the shift counter 5 if the carry signal is Ill, and inputs the subtraction result as it is to the shift counter 5 if it is 0°.

5 is a shift counter having information on how many bits to shift the value of shift register A6. 6 is a shift register A that stores the value to be shifted. A barrel shifter 7 shifts the value of the shift register A6 by the value of the shift counter 8. A shift register 8 stores the result shifted by the barrel shifter 7. A shifter 9 shifts the value of the shift register B8 to the right by one bit when the carry signal is l'. IO is a shift result register that stores the value of shift register B shifted by 1 bit by the shifter 9 when the carry signal is 1°, and stores the value of shift register B when the carry signal is "0". This is an adder/subtractor that adds or subtracts the mantissa data whose digits have been aligned and another mantissa data whose digits have not been aligned. 12 is an exponent result register that stores the result of the exponent. 13 is the mantissa data. This is a mantissa result register that stores the result of .

Next, we will explain the operation. First, the data a and b of the exponent part are input to the subtracter 1, and a subtraction of "a-b" is performed for these two numbers. At this time, if the result is negative, the carry signal e becomes 1', and if it is positive, it becomes 0°.

Based on the mantissa parts c and d, the mantissa data of the smaller exponent part is sent to the shift register 6 based on the carry signal e, and the other data is input to the adder/subtractor 11. Next, if the carry signal e is "0", the result of subtraction of the exponent part of 1 is stored in the shift counter 5 as is, and if it is "1", the inverted value of the subtraction result of the exponent part of 1 is taken and stored in the shift counter 5. Once the value of shift counter 5 is determined, the value of shift register 6 is shifted to the right by the value of shift count 5. If the carry signal e is 1°, the result after the shift is further shifted to the right by 1 bit, and finally the shift result register 10 and the input data of the unaligned mantissa selected by the selector at the beginning are input. The result is stored in the mantissa result register 13. Next, regarding the operation of the exponent part, the data of the exponent parts a and b of the two input data are judged by the carry signal e, and the larger one is sent to the exponent part result register 12.
Store in.

Next, the contents of each register when input data is actually input will be explained with reference to FIG. First, input data “3FFF
8000000000000000” (exponent part a,
mantissa part C) and “400180000000000000
Regarding the exponent part of “00” (exponent part S, mantissa part d), “Ia
-b" is subtracted. The subtraction result is FFFE" and the carry signal generated at this time is "l".

Next, since the carry signal e is “1”, shift register A6
The content of the mantissa C is “5oooooooo ooooooo
oo” is input, and the content of the mantissa part d “5oooooooo oooooooo” is input to one side input of the adder 11. At the same time, the carry signal is “1”, so the subtraction result “F”
Input the value "0001"', which is the inverted version of "F F E ", into the shift counter 5.Then, the value "80000000o o o o o o o o o" of the shift register A6 is input.
" is shifted by the value "0001" of the shift counter 5, and the result "4000000000000000" is input to the shift register B7.Next, since the carry signal e is "L", it is further shifted to the right by one more bit and the result is "20000".
00000000000'' is input to the shift result register 10.Then, the data on one side of the adder 11 selected at the beginning is ``'5oooooooo ooooooooo''.
and the value of shift result register 10 ゛2000000000
000000″′ and the result is “AOOOOOO
OO00000000'' is input to the mantissa result register 13. The above is the flow of the mantissa data.

Next, the exponent part will be explained. The data flow of the exponent part is simple, and in this example, the carry signal is "1", so the value "4001" of the exponent part is stored in the exponent part result register 12.

〔Effect of the invention〕

In the present invention, when determining the number of shifts for digit alignment of the mantissa part during digit alignment processing, which was conventionally performed during addition and subtraction of floating point numbers, when the result of subtraction between exponent parts becomes negative, the number of shifts of the absolute value is determined. Conventionally, two's complement was used to obtain the result, but the present invention shifts it to one's complement and then shifts the result by one bit to the right, making floating point addition and subtraction easier than before. Now I can do it faster.

[Brief explanation of drawings]

Fig. 1 is a diagram showing an embodiment of the present invention, Fig. 2 is a block diagram of a conventional technique, and Fig. 3 is a diagram showing the values of each register, signal, etc. when the results are actually input in Fig. 1. be. l...Subtractor, 2...Selector, 3.
...Selector, 4...Inverting circuit, 5...
...Shift counter, 6...Shift register A, 7...Barrel shifter, 8...Shift register B, 9...Shifter, 10...・・・
・Shift result register, 11...Adder/subtractor, 1
2...Exponent part result register, 13...
Mantissa result register, 14...Adder.

Claims (1)

[Claims] In a floating point binary addition/subtraction circuit, there is a subtracter that calculates the difference between the exponents of the summand and the addend or the subtractive and the subtram; if the subtraction result of the subtractor is positive, the subtraction result is used as the shift count; For example, a circuit that uses a value obtained by inverting the result of the subtraction as the number of shifts; and a barrel shifter that shifts the value of the mantissa part of the summand, the summand, the minuend, or the subtrahend, whichever is smaller than the exponent part, in one direction according to the shift circuit. , if the result of the subtraction is positive, the same value is used as the shift result, and if it is negative, the shifted result is further shifted by 1 bit in the same direction and used as the shift result, and the value of the mantissa obtained by the circuit is 1. A floating point addition/subtraction circuit comprising: