JPH03189726A - Data processor - Google Patents

Abstract

PURPOSE:To improve the universal applicability of a data processor by storing the data substituting the data stored in a data ROM into a substitute read/write enable memory and then storing the information into the read/write enable memory for each phase to select the data ROM or the read/write enable memory. CONSTITUTION:A 1st storage means 11 stores the prescribed data corresponding to each phase, and a 2nd storage means 12 stores the data substituting the data corresponding to the phases. A control means 10 selects the means 11 or 12 based on the selection information stored in the means 12 and loads the data corresponding to the phases into the selected storage means. That is, the data stored in the read/write enable storage means 12 is loaded in place of the data stored in the storage means 11. Thus, a partial change of data is attained and different actions are carried out in response to the substitute data. Then the universal applicability is improved for a data processor.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a system for loading data stored in another memory instead of data stored in a read-only memory and performing operations according to the data. The present invention relates to a data processing device that executes.

[Conventional technology]

In a conventional data processing device, a memory (ROM) only for data (program) reading is provided, and a predetermined program corresponding to each phase (program break) and address data corresponding to the phase are stored in advance in the ROM. Then, a program of a desired phase corresponding to the address data is loaded and an operation corresponding to the program is executed.

[Problem to be solved by the invention]

However, in the above data processing device, in order to prevent inoperability due to erasure of the program, the above program is stored in a memory only for data reading, as described above, so a part of the above program may be changed to perform different operations. Even if you want to run the program, you cannot change the program, so there is a problem that it lacks versatility.

The present invention has been made in view of the above-mentioned problems, and it is possible to store data in place of the data stored in the data read-only memory in the substitute memory, thereby making it possible to partially change the data. An object of the present invention is to provide a data processing device that can perform different operations.

[Means to solve the problem]

The present invention has a first storage means dedicated for reading data such as a ROM that stores address data corresponding to each phase (data delimiter) and data corresponding to the address data, and In a data processing device that loads data such as a desired program corresponding to the above and executes an operation according to the data, address data corresponding to the phase and data corresponding to the address data are stored in the first storage means. selection information for selecting a storage means that stores data to replace the stored data and stores data used during the operation;
Control of a second readable/writable storage means such as a flash memory that stores data in association with the phase, and a central processing unit that loads corresponding data from the first and second storage means according to the selection information. and means.

[Effect]

A first storage means that stores predetermined data that corresponds to each phase, and a second storage means that stores data that replaces the data that corresponds to the phase, are selected as stored in the second storage means. The control means selects and loads data corresponding to the above phase in accordance with the information.

Therefore, by loading the data stored in the readable/writable second storage means as a substitute for the data stored in the first storage means, it becomes possible to partially change the data, and the data can be changed to the above-mentioned alternative data. You can perform different corresponding actions.

〔Example〕

Embodiments of the present invention will be described in detail based on the drawings of FIGS. 1 to 6.

FIG. 1 is a block diagram showing an outline (M configuration) of a data processing device according to the present invention.
PU) 10 includes ROMI 1 and FLASH memory 12
Data (program) stored in a predetermined storage area within
is loaded and executes an operation according to the program, and also performs write control to write a desired program into a predetermined storage area in the FLASH memory 12.

As shown in FIG. 2, the ROM 11 stores a phase table consisting of address data (for example, A, B, C, D, . . . ) in the ROM II corresponding to each phase. By sequentially specifying the address data, the MPU10 can select the corresponding ROMI1.
A desired program can be read from the storage area within the computer.

The FLASH memory 12 is a memory that can erase data all at once and write data byte by byte under electrical control.Similar to the ROM II, as shown in FIG. address data (e.g. AB-(,"Ilm...)
The RO according to the present invention stores a phase table consisting of
The M/FLASH section stores data 13 (see FIG. 1). In other words, the data 13 of the ROM/FLASH portion is, for example, if the memory from which the program is read is RO.
In the case of MI 1, “0” data is written to the corresponding phase, and the memory from which the program is read is FLAS.
In the case of the H memory 12, it is constructed by storing "1" data in the corresponding phase.

The MPU10 uses the data 13 to determine the ROM/FLASH division stored in the FLASH memory 12.
A program can be loaded from FLASH memory 12 to replace the program stored in ROMI.

Next, the operation of program load control according to the present invention will be explained based on the flowchart of FIG.

In the figure, MPU10 first includes FLASH memory 12.
The ROM/FLASH portion stored in is data 1.
3, the memory from which the program for each phase is to be read is checked (step 101). Then, it is determined whether the data corresponding to the phase is "0" (step 102).

Here, if the data is "0", it is determined that the memory to be read by the program is ROMII (step 103), and the ROMII corresponding to the address data is
A desired program is loaded from the storage area within (step 105). If the above data is "1", it is determined that the memory from which the program is to be read is the FLASH memory 12 (step 104), and the program in ROMI is read from the storage area in the FLASH memory 12 corresponding to the address data. A desired alternative program is loaded (step 105). Then, it is determined whether or not the data judgment has been completed for the ROM/FLASH section corresponding to all phases (step 106), ROM/FLASH
If the data has not yet been determined for the FLASH segment, the process returns to step 101 and repeats the above operations, and the ROM/FLASH data corresponding to all of the above phases is
When the judgment of the data is completed, the above operation is completed.

Therefore, in the present invention, by loading an alternative program stored in the FLASH memory, it is possible to partially change the program, and a different operation corresponding to the above-mentioned alternative program can be executed.

FIG. 4 is another embodiment of a block diagram showing a schematic configuration of a data processing device according to the present invention. In FIG. 4, components similar to those shown in FIG. 1 are given the same reference numerals.

In the figure, the MPU10 stores the ROM/FLASH portions stored in the FLASH memory 12 according to the data and corresponds to each phase from the phase table created in the ROM 11 and the FLASH memory 12 as shown in FIG. address data (for example, A, B, C-D,
) is loaded and transferred to the RAM 14 to create an address table. Therefore, MPU10 has the above RA
By the address table created in M14, ROM
A program that replaces the program stored in FLASH memory 11 can be loaded from FLASH memory 12.

Next, another embodiment of the program load control operation according to the present invention will be described based on the flowchart of FIG.

In the figure, MPU10 is operated by thumb check etc.
It is determined whether the FLASH memory 12 stores data and is in a standby state (step 201).

Here, the FLASH memory 12 is in a standby state (READY).
), load the address data of the phase table in ROMII and transfer the above address data to RA.
Copy to the address table of M14 (step 202
). Further, when the FLASH memory 12 stores data and is in a standby state, next, the ROM/FLASH division digitator 13 stored in the FLASH memory 12
The memory from which the program for each phase is to be read is checked, and it is determined whether the data corresponding to the phase is "0" (step 203).

Here, if the data is "0", it is determined that the memory from which the program is read is the ROM11, the address data of the ROMII corresponding to the above phase is loaded from the phase table, and the RA corresponding to the phase is loaded.
Post to the address table of M14 (step 2o4
). If the data is "1", it is determined that the memory to be read by the program is the FLASH memory 12, the address data of the FLASH memory 12 corresponding to the above phase is loaded from the phase table, and the address data corresponding to the phase is loaded. The data is transferred to the address table of the RAM 14 (step 2o5).

Then, it is determined whether or not the address data corresponding to all phases has been transferred to the address table of the RAM 14 (step 2o6).

Here, if the transcription of the address data corresponding to all phases has not been completed, return to step 203 and repeat the above operation, and if the transcription of the address data corresponding to all the phases has been completed, RAM14 above
ROMII or FLASH based on the address table of
Memo 1J12 (7) Load the desired program from the storage area (step 207) and end the above operation.

Therefore, in the present invention, when a program is executed, an address table consisting of address data of the program to be executed is created on the RAM, and a desired program is loaded from the storage area of the ROM or FLASH memory based on the created address table. Therefore, it becomes possible to load an alternative program stored in the FLASH memory, thereby making it possible to partially change the program and perform a different operation corresponding to the alternative program. Furthermore, in the present invention, by creating an address table on the RAM, selection speed at the time of program selection can be improved.

〔Effect of the invention〕

As explained above, in the present invention, data in place of the data stored in the data read-only memory is stored in the alternative read/write memory, and the data is read only or read/write in the read/write memory. Since the memory selection information is stored for each phase, data can be changed for each phase, and different operations corresponding to alternative data can be executed. This increases the versatility of the data processing device. can be improved.

A block diagram showing a schematic configuration of another embodiment of the data processing device, FIG. 5 is a diagram showing the phase table of the ROM and FLASH memory shown in FIG. 4, and an address table of the RAM, and FIG. 3 is a flowchart for explaining the operation of program loading control by the MPU according to the present invention.

10...Central processing unit (MPU), 11...RO
M, 12...FLASH memory, 13...ROM/
FLASH portion is data, 14...RAM0

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a data processing device according to the present invention, and FIG. 2 shows the ROM and FLAS shown in FIG.
3 is a flowchart for explaining the operation of program loading control by the MPU according to the present invention shown in FIG. 1, and FIG. 4 is a diagram showing the phase table of the H memory according to the present invention. Figure 6

Claims (2)

[Claims] (1) It has a first storage means that stores address data corresponding to each phase and data corresponding to the address data, and loads desired data corresponding to the address data and responds to the data. In a data processing device that executes an operation, address data corresponding to the phase and data corresponding to the address data and replacing data stored in the first storage means are stored and used during the operation. a second storage means for storing selection information for selecting a storage means in which data is stored in association with the phase; and a second storage means for storing corresponding data from the first and second storage means in accordance with the selection information. A data processing device comprising: a control means for loading data. (2) It has a first storage means that stores address data corresponding to each phase and data corresponding to the address data, and loads desired data corresponding to the address data and responds to the data. In a data processing device that executes an operation, address data corresponding to the phase and data corresponding to the address data and replacing data stored in the first storage means are stored and used during the operation. a second storage means for storing selection information for selecting a storage means in which data is stored in association with the order of use; a first control means for loading the address data from the second storage means; a third storage means for storing the loaded address data; and a first control means for storing the loaded address data; and second control means for loading from the first and second storage means.