JPH03190165A - Read-only memory device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a memory device, in which TAT can be shortened and MOS transistors can be densely arranged, by a method wherein a groove is provided onto the surface of a semiconductor substrate nearly vertical to a direction in which the MOS transistors are arranged, a gate electrode is formed on the surface of the sidewall of the groove, and impurity is selectively introduced into the sidewall of the groove. CONSTITUTION:A P-type well region 2 is formed on an N-type silicon substrate 1, and straight line grooves 3 parallel with each other are formed on a surface 2a. The sidewall 4 of the groove 3 is nearly vertical to the primary surface of the substrate 1, and the base 5 of the groove 3 is cut parallel to the primary face of the substrate 1. A thick field oxide film 6 used for isolating elements from each other is formed in a belt-shaped pattern sandwiching both the sides of a MOS transistor row. A region surrounded with the field oxide film 6 is made to serve as an active region, and MOS transistors are formed to serve as memory cells respectively.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an NA in which a plurality of MOS transistors are connected in series.
The present invention relates to an ND type read-only memory device and a manufacturing method thereof.

[Summary of the invention]

The present invention provides a read-only memory device in which a plurality of MOS transistors are connected in series on a semiconductor substrate, and a method for manufacturing the same, in which a plurality of grooves are provided parallel to the surface of the semiconductor substrate, and a gate electrode layer is provided on the sidewalls of the grooves. By forming MOS transistors, turnaround time (TAT) can be shortened and integration can be increased.

[Conventional technology]

In a read-only memory device called a mask ROM, information is written during the manufacturing process. These mask ROMs can be roughly divided into NOR type and NAND type.
There is a type. Among these, NOR type mask ROMs have the advantage of short TAT, but are difficult to integrate. On the other hand, NAND type mask ROM
Although it is easy to achieve high integration, conventional NAND-type mask ROMs require an E/ROM that selectively forms enhancement-type and depletion-type MOS transistors, for example.
In the structure D, impurity ions must be ion-implanted into the channel region before forming the gate electrode, and the TAT becomes longer by the number of steps after ion implantation (for example, see Japanese Patent Laid-Open No. 52-30388). ).

(Problem to be Solved by the Invention) In order to shorten the TAT of such a mask ROM, instead of writing information by selectively implanting impurities into the channel, the source and drain regions of each MOS transistor are NAND type mask R for writing information depending on whether or not to form metal wiring that causes short circuit.
OM has also been proposed, and such technology is described in, for example, Japanese Patent Laid-Open No. 60-9157.

However, in such a mask ROM, the source
It is necessary to bring the metal wiring into contact with the drain region, which increases the area of the contact, which is disadvantageous in achieving high density, and there are various practical problems such as the need for two layers of metal wiring.

SUMMARY OF THE INVENTION In view of the above-mentioned technical problems, it is an object of the present invention to provide a read-only memory device and a method for manufacturing the same, which can shorten TAT and arrange MOS transistors at high density.

[Means to solve the problem]

In order to achieve the above-mentioned object, a read-only memory device of the present invention has a memory cell constituted by a plurality of MOS transistors arranged in a straight line and connected in series on a semiconductor substrate, A groove is formed on the surface of the semiconductor substrate with its longitudinal direction substantially perpendicular to the direction in which the MOS transistors are arranged, and a gate electrode of the MOS transistor is formed on the side wall surface of the groove with an insulating film interposed therebetween. It is characterized in that information is written by selectively introducing impurities into the sidewalls of the device.

Further, the method for manufacturing a read-only memory device of the present invention includes:
A step of forming a plurality of grooves parallel to each other on the surface of a semiconductor substrate, a step of forming an insulating film on the surface of the semiconductor substrate having the grooves, and a step of forming an electrode layer on the entire surface and etching only the side walls of the grooves. a step of leaving the electrode layer on the substrate, a step of introducing impurities into the semiconductor substrate using the remaining electrode layer as at least a part of a mask to form source/drain regions of the MOS transistor, and a step of introducing impurities into the sidewalls of the groove portions. The method is characterized in that it has a step of selectively introducing information to write information.

[Effect]

By forming the gate electrodes of a plurality of MOS transistors connected in series on the sidewalls of the trench, the gate electrodes can be formed in a consistent manner on the sidewalls using a sidewall forming technique. Therefore, it is advantageous for high integration. When the gate electrode is formed on the sidewall of the trench in this manner, the channel region is formed along the sidewall. Therefore, the channel region and the gate electrode are positioned so that they do not overlap from above the semiconductor substrate, and it is possible to selectively introduce impurities even after the gate electrode is formed. Therefore, TAT can be shortened.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

First Example First, the structure of the read-only memory device of this example will be explained in the first example.
This will be explained with reference to FIGS.

In the read-only memory device of this embodiment, a p-type well region 2 is formed on an n-type silicon substrate 1, and a surface 2a of this p-type well region 2 is arranged along the Y direction in FIG. Linear grooves 3 are formed that are parallel to each other in the longitudinal direction. The cross-sectional shape of the groove portion 3 is such that the side walls 4 thereof are formed at an angle substantially perpendicular to the main surface of the substrate, and the bottom portion 5 has a surface cut parallel to the main surface of the substrate. In addition,
In this embodiment, four trenches 3 are formed per one series MOS transistor column, but the invention is not limited to this.

A thick field oxide film 6 for isolating elements is formed on the surface of the P-type well region 2 having such a groove 3.
It is formed in a band-like pattern extending in the X direction so as to sandwich both sides of the S transistor row. On the plane, these field oxidation 1M! The region surrounded by 6 is an active region, and each MOS transistor serving as a memory cell is formed in the active region. That is, in FIG. 1, a plurality of MOS transistors connected in series are arranged in the X direction.

FIG. 2 is a cross-sectional view taken along the line ■-■ in FIG. 1, showing a cross section of the active region.A gate electrode of a MOS transistor is connected to the side wall 4 of the trench 3 via a gate insulating film 7. There are respective word lines WL.

~WL, and selection lines SL, SL2 are formed.

These word lines WL, -WL and selection line SL1. SL2
is formed along the side wall 4 of the groove portion 3, so its longitudinal direction is the Y direction. These word lines WL, .about.WL and selection lines st, . . . SL are formed of, for example, a polysilicon layer doped with impurities. Therefore, these word lines WL, ~WL and selection lines SL, SL2 can be formed by a so-called sidewall forming technique.
That is, after forming the gate insulating film 7 on the surface of the groove 3,
By depositing a polysilicon layer over the entire surface and performing an etch bank, the polysilicon layer can be left in alignment with the sidewalls 4. Word line WL for each side wall 4 of each groove 3
, ~WL, or selection line SL.

SL is formed, and a pair of word lines and the like face each other in one groove portion 3.

Further, in the active region sandwiched between field oxide films 6 for element isolation, impurities are introduced into the bottom of the trench 3 and the surface 2a of the well region 2, and the impurities cause the source/drain regions 8a to 81 to be It is formed. Among these source/drain regions 8a to 81, the source/drain region 8a.

8c, 8e, 8g, and 8i are formed on the surface 2a side of the well region 2. In addition, source/drain regions 8b, 8d
, 8f and 8h are formed at the bottom 5 of the groove 3. In this way, in each MOS transistor, one source/drain region is formed on the surface 2a of the well region 2, and the other is formed on the bottom 5 of the trench 3, so that the channel region of each MOS transistor is formed along the sidewall 4. The direction of the channel length is perpendicular to the main surface of the substrate. Each of the source/drain regions 8a to 81 is composed of an n-type high concentration impurity diffusion region and an n-type low concentration impurity diffusion region. The n-type low concentration impurity diffusion region is formed by ion implantation in a direction perpendicular to the main surface of the substrate using the field oxide film 6 as a mask, and is formed over the bottom 5 of the trench 3. It is formed on the surface a of the well region 2. The n-type high concentration impurity diffusion region is formed by the field oxide film 6 and the word lines WL, -
They are formed using WL or selection lines SL, SL as a mask, and are formed on the bottom 5 of the trench 3 and the surface 2a of the well region 2. This n-type high concentration impurity diffusion region is used for word lines WL, ~WL, or selection lines SL+, st, z
In order to use these word lines WL, ~WL, as a mask,
Or the bottom 5 of the groove 3 below the selection lines SL, SLt.
Therefore, n is not formed in the bottom 5 of the groove 3 under the word lines WL, ~WLh or the selection lines SL, SL.
Only a type of low concentration impurity diffusion region is formed. In addition, this n° type high concentration impurity diffusion region has a diffusion depth of n
The source/drain region 8a is shallower than the - type low concentration impurity diffusion region and is on the surface side.

8c, 8e, 8g, and 8i have a double diffusion structure.

Such a double diffusion structure can alleviate the concentration of the drain electric field, and is particularly advantageous when high integration of read-only memory devices is attempted.

Each groove 3 formed in the n-type well region 2 is covered with a glabella insulating film 9 covering the entire surface thereof.

A contact hole 10 is formed in the interlayer insulating film 9 above the source/drain region 81, and a bit line 11 made of an aluminum wiring layer is connected to the source/drain region 81 via the contact hole 10.
is formed. This bit line 11 is connected to the glabella insulating film 9
It is formed so that its longitudinal direction is in the X direction, and as shown in FIGS. 1 and 3, it is formed in a planar manner on the field oxide film 6 between two MOS transistor rows. .

In the read-only memory device of this embodiment having such a structure, impurities are selectively introduced into the channel forming region of each MOS transistor, and enhancement type (normally off) and depletion type (normally on) MOS transistors are formed.
It is made into an S transistor. In FIGS. 1 and 2, the shaded regions 12 are examples of regions into which n-type impurities are introduced by ion implantation, depending on the information to be written. This ion implantation is performed in a direction perpendicular to the main surface of the substrate, and is implanted into the channel region of the MOS transistor to be of the depletion type. A MO3I-transistor in which n-type impurities are implanted into the channel region in this manner is considered to be a depletion type, and conversely, a MOS transistor in which n-type impurities are not implanted into the channel is considered to be an enhancement type. The ion implantation process for writing this information is performed on each word line WL, ~W, which is a gate electrode.
This is performed after the formation of Lh or the selection lines SL, SL2, and since the channel region is offset from each word line, etc. and bit line in the plane, it is also possible after the formation of the word line, etc. and bit line.

Therefore, the information writing process during the manufacturing process can be moved to a sufficiently later stage, making it possible to significantly shorten the TAT.

Next, a method for manufacturing the read-only memory device of this embodiment will be described with reference to FIGS. 6a to 6e.

First, as shown in FIG. 6a, an n-type silicon substrate 21
An n-type well region 22 is formed thereon.

Then, a plurality of substantially parallel linear trenches 23 are formed in a region of the surface 22a of this n-type well region 22 where a memory cell array is to be formed. The formation of this groove portion 23 is as follows:
For example, this is performed by anisotropic etching such as RIE, and the sidewalls 24 of the grooves 23 are etched so that they are substantially perpendicular to the main surface of the substrate. The bottom 25 of the groove 23 is connected to the surface 22.
It has a surface substantially parallel to a. Height H of side wall 24 of groove 23
l is the dimension that determines the channel length of the MOS transistor, and the width W1 of the trench 23 is at least 2 when the word line is formed using the sidewall forming technique.
The distance is such that the word lines of the book remain separated.

Next, field oxidation WA26 is formed on the surface 22a of the well region 22 and the surface of the trench 23 by selective oxidation. That is, a pad silicon oxide film is formed over the entire surface of the well region 22 in which the groove portion 23 is formed.

A silicon nitride film is formed and a mask is formed by selectively etching the silicon nitride film. Then, an oxidation process is performed using the silicon nitride film as a mask to form a field oxide film 26. This field oxide film 26 isolates the MOS transistor columns.

After forming the field oxide film 26, as shown in FIG. 6, a gate insulating film 27 is formed over the entire surface. This gate insulating film 27 covers not only the surface 22a of the well region 22 but also
It is also formed on the side wall 24 and bottom portion 25 of the groove portion 23.

After forming the gate insulating film 27 on the entire surface, ion implantation is performed to implant n-type impurities. This ion implantation
The dopant is implanted in a direction perpendicular to the main surface of the substrate, and the dopant is implanted into the surface 22a of the well region 22 and the groove 2.
Impurities are introduced at a low concentration into the bottom portion 25 of 3. As a result of this ion implantation, n-
type low concentration impurity diffusion regions 28a, 28c, 28e, 2
8g, 28i are formed. In addition, the bottom 25 of the groove 23
is an n-type low concentration impurity diffusion region 28b.

28d, 28f, and 28h are formed. No n-type impurity is introduced into the sidewall 24 of the trench 23, and p
The conductivity type of the type is left unchanged.

Next, a polysilicon layer 29 is formed on the entire surface of the gate insulating layer 27 on the well region 22. This polysilicon layer 29 is made of doped polysilicon containing impurities, and the gate insulating film 22 is also formed on the sidewall 24 of the trench 23.
7.

After forming the polysilicon layer 29 on the entire surface in this way, as shown in FIG. 6C, an etch bank is performed by RIH to leave the polysilicon N29 on the sidewalls 24 of the trench 23. The polysilicon layer 29 remaining on this side wall 24 is M
It functions as a gate electrode of an OS transistor, that is, a word line, etc. By using such sidewall forming technology, it is possible to form word lines etc. in a self-aligned manner on the sidewalls 24 of the groove portions 23. Therefore, even when miniaturizing a read-only memory device, word lines can be formed with sufficient accuracy. Can form lines. The memory cell portion is formed in self-alignment with the side wall 24 of the groove portion 23 as described above, but the peripheral circuit portion may be formed by normal patterning of a polysilicon layer.

After forming a polysilicon layer 29 that will serve as a word line or the like on the sidewall 24 of the trench 23, using the polysilicon layer 29 and the field oxide film 26 that is an element isolation region as a mask, a high concentration of n-type impurity is applied in a self-aligned manner. ion implantation into MOS
N° type high concentration impurity diffusion regions are formed to become the source/drain regions of the transistor. This n-type high-concentration impurity diffusion region is formed on the surface 22a of the well region 22 and the bottom 25 of the trench 23, similarly to the n-type low-concentration impurity diffusion region. By this ion implantation, n-type high concentration impurity diffusion regions 30a, 30c, and 30e are formed on the surface 22a of the well region 22.

30g and 30i are formed. In addition, the bottom 2 of the groove 23
5, n-type high concentration impurity diffusion regions 30b, 30d,
30f and 30h are formed. These n-type high concentration impurity diffusion regions 30a to 30i each have a diffusion depth of n.
It is made shallower than the - type low concentration impurity diffusion regions 28a to 28i. After forming the high concentration impurity diffusion regions 30a to 30i, as shown in FIG. ! Form 31.

Once the glabellar insulating film 31 has been formed, the user is in a state of waiting for information to be written. Once the information is obtained, a mask is formed according to that information. This mask is formed by forming the glabella insulating film 3 as shown in FIG. 6e.
A resist layer 32 is formed on 1, and the resist layer 32 is selectively exposed and developed. After forming a resist layer 32 serving as a mask, n-type impurities are ion-implanted into the sidewalls 24 of the grooves 23, which are the channel regions of predetermined MOS transistors, through the openings 33 provided in the resist layer 32. Driven into it.

Through this ion implantation, MOS transistors into which n-type impurities are implanted become depletion type, and MOS transistors into which other impurities are not implanted.
It is considered to be an enhancement type.

This structure in which depletion type and enhancement type are selectively formed allows information to be read out.

After the program ion implantation, the resist layer 32 is removed, a contact hole for a bit line is formed, and a bit line is formed from the aluminum-based wiring layer. Thereafter, the read-only memory device is completed according to a normal process.

In addition, during the above manufacturing process, the ion implantation program is
This can be done after the formation of the polysilicon layer. Further, even after the bit line is formed, program ion implantation can be performed depending on the material of the bit line, annealing conditions, etc.

Second Embodiment In this embodiment, the part sandwiched between the two grooves is connected to one MOS.
This is an example of a read-only memory device that functions as a transistor.

As shown in FIG. 7, the structure is that a plurality of mutually parallel grooves 43 are formed on the surface of a p-type well region 42 formed on an n-type silicon substrate 41. The longitudinal direction of these grooves 43 is perpendicular to the drawing. This groove 4
In the cross-sectional shape of No. 3, the width W2 of the surface of the well region 42 is shortened, and the distance between two adjacent grooves 43 is narrowed, as compared to the groove portion 3 of the first embodiment. By narrowing the distance between two adjacent grooves 430 in this manner, the distance between the side walls 44 of adjacent grooves 430 is also shortened.

A gate electrode 49 made of a polysilicon layer is formed on each of the side walls 44 arranged at a short distance between the adjacent trenches 43 with a gate insulating film 47 interposed therebetween. This gate electrode 49 functions as a word line 1 selection line,
It is formed by the sidewall forming technique as described above. At the bottom 45 of the groove 43 and the surface of the well region 42, source/drain regions 48 each having a double structure of an n-type low concentration impurity diffusion region and an n-type high concentration impurity diffusion region are formed. The n-type low concentration impurity diffusion region is offset by the amount of the gate electrode 49 at the bottom 45 of the trench 43 as in the first embodiment. These sources
The drain regions 48 are arranged substantially linearly in accordance with the pattern of the active region, and constitute a series-connected MOS transistor array. A glabellar insulating film 50 is formed to cover the gate electrode 49, field oxide film 46, and gate insulating film 49.

In the read-only memory device of this embodiment having such a structure, a pair of gate electrodes 49 sandwiching a region of width W2 between trenches 430 functions as a single word line. That is, in the first embodiment, two MOS transistors were formed per trench, but in this embodiment, only one MO3I-transistor is formed per trench 43. Therefore, information is written to the entire region sandwiched between the two grooves 43, and therefore, as in the case of the first embodiment, the convex portion sandwiched between the two grooves 43 is The occurrence of punch-through between two MOS transistors having channels at the same time does not pose a problem.

As shown in FIG. 7, the program ion implantation is performed using a resist layer 51 formed on interlayer insulation #50, and n-type impurities are introduced through an opening 52 formed in the resist layer 51. be done. This ion implantation is performed after the gate electrode 49 is formed, and the TAT is shortened. Here, the opening 52 is sized to span the pair of grooves 43, 43, and is formed by ion implantation.
An impurity diffusion region 53 is formed spanning the region between the pair of trenches 43, 43. With this impurity diffusion region 53,
The MOS transistors spanning the two trenches 43 and 43 are of the depletion type, and the other MOS transistors are of the enhancement type.

In a read-only memory device that uses two gate electrodes 49 for one MOS transistor as described above, the space between the two trenches 43 and 43 is used as a channel region of one MOS transistor.

Therefore, a significant reduction in TAT is achieved, and problems such as punch-through do not occur.

Third Embodiment This embodiment is an example in which one MOS transistor is constructed by two gate electrodes formed in one trench.

As shown in FIG. 8, the structure is such that a plurality of mutually parallel grooves 63 are formed on the surface of a p-type well region 62 formed on an n-type silicon substrate 61. The longitudinal direction of these grooves 63 is perpendicular to the drawing. This groove 6
3, the width of the surface of the well region 62 is longer than that of the groove 3 of the first embodiment, and the width of the bottom 6 of the groove 63 is longer than that of the groove 3 of the first embodiment.
5 is shortened.

A gate insulating film 6 is formed on each side wall 64 of this groove portion 63.
A gate electrode 69 made of a polysilicon layer is formed through the gate electrode 7 . This gate electrode 69 functions as a word line 9 selection line and is formed by the sidewall forming technique described above. The bottom 65 of the trench 63 and the surface of the well region 62 are provided with an n-type low concentration impurity diffusion region and an n
A source/drain region 68 having a double structure of 2-type high concentration impurity diffusion regions is formed. The n-type low concentration impurity diffusion region is offset by the amount of the gate electrode 69 at the bottom 65 of the trench 63 as in the first embodiment. These source/drain regions 68 are arranged substantially linearly in accordance with the pattern of the active region, and constitute a series-connected MOS transistor array. Then, a glabellar insulating film 70 is formed to cover the gate electrode 69, field oxide film 66, and gate insulating film 69.

In the read-only memory device of this embodiment in which the width of the bottom 65 of the trench 63 is shortened, two gate electrodes 69 formed in one trench 63 are used for one MOS transistor. Therefore, as shown in FIG. 8, when performing program ion implantation using the resist layer 71 as a mask, by making the opening 72 slightly wider than the width W3 of the groove 63, the side walls 64 of the groove 63 are Impurity diffusion region 73 can be formed throughout. and,
The MOS transistor in which impurity diffusion region 73 is formed is of a depletion type.

In a read-only memory device with such a structure, TAT
It has the advantage that it is possible to shorten the time period, and that programmed ion implantation can be easily performed in terms of mask alignment and the like.

Note that the gate electrode 69 may be a buried gate electrode instead of a sidewall.

〔Effect of the invention〕

The read-only memory device and its manufacturing method of the present invention include:
As mentioned above, a groove is formed on the surface of the semiconductor substrate, and a gate electrode that functions as a word line or the like is formed on the sidewall of the groove, so the positions of the channel formation region and the gate electrode on the plane are shifted. . Therefore, information can be written even after the gate electrode is formed, and TAT
can be significantly shortened. Furthermore, these gate electrodes are formed on the side walls of the groove portion in a self-aligned manner with an insulating film interposed therebetween.

Therefore, even when the read-only memory device is miniaturized, it can be adequately accommodated, and higher integration and density can be achieved.

[Brief explanation of drawings]

1 is a plan view of essential parts showing an example of a read-only memory device of the present invention, FIG. 2 is a cross-sectional view taken along the line ■-n in FIG. 1, and FIG. 3 is a cross-sectional view taken along the line ■-■ in FIG. Figure 4 shows rV-I in Figure 1.
5 is a sectional view taken along the line V--V in FIG. 1. FIGS. 6a to 6e are process cross-sectional views for explaining an example of the method for manufacturing the above-mentioned example according to the steps. Further, FIG. 7 is a sectional view of a main part showing another example of the read-only memory device of the present invention, and FIG. 8 is a sectional view of a main part showing still another example of the read-only memory device of the invention. 1.21, 41.61...Silicon substrate 2.22, 4
2.62... Well region 3.23, 43.63...
Groove portions 4.24, 44.64...Side walls 5.25, 45.65...Bottom portions 6.26, 46.66...Field oxide film 7.27
, 47.67...gate insulating films 8a to 8g, 48.6
8... Source/drain region 9.31.50.70.
...Interlayer insulating film 10...Contact hole 11...Bit lines WL, -WL,...Word lines SL, SLZ...Selection line

Claims (2)

[Claims] (1) In a read-only memory device in which a memory cell is constituted by a plurality of MOS transistors arranged in a straight line and connected in series on a semiconductor substrate, the direction in which the MOS transistors are arranged on the surface of the semiconductor substrate and A groove is formed with the longitudinal direction extending approximately perpendicularly, and the above-mentioned MOS
A read-only memory device characterized in that a gate electrode of a transistor is formed, and information is written by selectively introducing impurities into the sidewalls of the trench. (2) A step of forming a plurality of parallel grooves on the surface of a semiconductor substrate, a step of forming an insulating film on the surface of the semiconductor substrate having the grooves, and a step of forming an electrode layer on the entire surface and etching the grooves. a step of leaving the electrode layer on the sidewall of the groove; a step of introducing impurities into the semiconductor substrate using the remaining electrode layer as at least a part of a mask to form a source/drain region of the MOS transistor; 1. A method of manufacturing a read-only memory device, comprising the step of selectively introducing impurities into the memory to write information.