JPH03190251A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03190251A JPH03190251A JP1331607A JP33160789A JPH03190251A JP H03190251 A JPH03190251 A JP H03190251A JP 1331607 A JP1331607 A JP 1331607A JP 33160789 A JP33160789 A JP 33160789A JP H03190251 A JPH03190251 A JP H03190251A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor element
- semiconductor
- clip member
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/301—Assembling printed circuits with electric components, e.g. with resistors by means of a mounting structure
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
この発明は、半導体装置に係り、特にその実装構造に関
するものである。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application This invention relates to a semiconductor device, and particularly to its mounting structure.
（ロ）従来の技術
近年、半導体装置の集積度が向上し、その接続端子数も
増加する傾向にある。しかしながら、電子機器は、軽薄
短小の流れの中で、そこに実装される半導体装置にも高
密度実装が要求されている。(B) Prior Art In recent years, the degree of integration of semiconductor devices has improved, and the number of connection terminals has also tended to increase. However, as electronic devices become lighter, thinner, shorter, and smaller, the semiconductor devices mounted thereon are also required to be mounted at high density.
従来の半導体装置の実装構造の中で、高密度実装を実現
しているものに、フェースダウンボンディング方式があ
る（例えば、特公昭６３−６４０５５号公報参照）。フ
ェースダウンボンディング方式では、半導体素子の接続
端子に半田バンプを設け、リフローにより半田バンプを
溶融し、実装用の基板と接続している。Among conventional mounting structures for semiconductor devices, there is a face-down bonding method that achieves high-density mounting (see, for example, Japanese Patent Publication No. 63-64055). In the face-down bonding method, solder bumps are provided on the connection terminals of a semiconductor element, and the solder bumps are melted by reflow and connected to a mounting board.
（ハ）発明が解決しようとする課題
しかしながら、実装後、半導体装置と実装用基板との熱
膨張率の違いにより、熱衝撃で接続部に応力が加わり、
その結果クラックが発生したり、不良チップのりペア性
が悪い。また、リフロー時が高温加熱であるため、半導
体素子やその周辺素子の熱破壊の虞れもある。(c) Problems to be Solved by the Invention However, after mounting, stress is applied to the connection part due to thermal shock due to the difference in thermal expansion coefficient between the semiconductor device and the mounting board.
As a result, cracks may occur, or the bonding properties of defective chips may be poor. Furthermore, since high temperature heating is performed during reflow, there is a risk of thermal destruction of the semiconductor element and its peripheral elements.
本発明は、フリップチップの耐熱衝性、リペア性を向上
させ、しかも実装時に高温加熱することなく、高密度な
実装を得ることをその課題とする。An object of the present invention is to improve the thermal shock resistance and repairability of a flip chip, and to obtain high-density mounting without heating at high temperatures during mounting.
（ニ）課題を解決するための手段
本発明は、接続部に金属バンプを設けた半導体素子と、
この半導体素子と接続される導電性パターンを設けた基
板とを有する半導体装置であって、前記半導体素子の金
属バンプを有する面と反対面と、前記基板の半導体素子
との接続面と反対面と、をクリップ部材にて挟み、前記
半導体素子と基板とを保持し、電気的接続を行なうこと
を特徴とする。(d) Means for Solving the Problems The present invention provides a semiconductor element with metal bumps provided at the connection portion,
A semiconductor device comprising a substrate provided with a conductive pattern to be connected to the semiconductor element, the semiconductor element having a surface opposite to the surface having the metal bump, and a surface of the substrate opposite to the connection surface with the semiconductor element. , are sandwiched between clip members to hold the semiconductor element and the substrate and to perform electrical connection.
（ホ）作用
本発明は、クリップ部材により、半導体素子と実装用基
板とが保持され、金属バンプと基板の導電性パターンが
機械的に接触しているため、フェースダウンボンディン
グ方式のように熱膨張率の差による破壊が生じない。(E) Function In the present invention, the semiconductor element and the mounting board are held by the clip member, and the metal bumps and the conductive pattern on the board are in mechanical contact, so that thermal expansion is prevented unlike in the face-down bonding method. No destruction occurs due to rate difference.
また、半導体素子の不良時には、クリップ部材を外すこ
とにより、再度新しい半導体素子を実装できる。さらに
、実装が低温で行えるため、半導体素子やその周辺の素
子に熱影響を与えない。Furthermore, when a semiconductor element is defective, a new semiconductor element can be mounted again by removing the clip member. Furthermore, since mounting can be performed at low temperatures, there is no thermal effect on the semiconductor element or surrounding elements.
（へ）実施例
以下、本発明の一実施例を第１図ないし第４図に従い説
明する。(F) Example Hereinafter, an example of the present invention will be described with reference to FIGS. 1 to 4.
（１）はクリップ部材であり、本実施例においては、こ
のクリップ部材を形状記憶合金で形成されている。そし
て、このクリップ部材（１）は第１図に示す如く、クリ
ップ部材（１）が閉じた状態が記憶されている。(1) is a clip member, and in this embodiment, this clip member is made of a shape memory alloy. The clip member (1) is stored in a closed state as shown in FIG.
（２）は半導体素子としての半導体チップであり、この
半導体チップ（２）の電極上には金属バンプ（３）が形
成されている。(2) is a semiconductor chip as a semiconductor element, and metal bumps (3) are formed on the electrodes of this semiconductor chip (2).
（４）は実装用の基板であり、この基板（４）上には所
定の導電パターン（５）が形成されている。(4) is a mounting board, and a predetermined conductive pattern (5) is formed on this board (4).
さて、本実施例に用いるクリップ部材（１）は形状記憶
合金で構成されており、金属バンプ付半導体チップ（２
）を基板（４）の接続端子部にフェースダウンして、こ
の両サイドから両者をクツツブする形状が記憶されてい
る。形状記憶合金は、その弾性率が温度依存性をもち、
ある固有温度を境にしてその温度以下では弾性率は著し
く低下し、僅かな力で変形させることができる。その温
度以上になると、弾性率が高くなり、予め記憶させた形
状に復帰していく。Now, the clip member (1) used in this example is made of a shape memory alloy, and the semiconductor chip (2) with metal bumps is made of a shape memory alloy.
) is placed face down onto the connection terminal portion of the board (4), and a shape is memorized in which the two are pushed together from both sides. Shape memory alloys have a temperature-dependent elastic modulus,
Below a certain specific temperature, the elastic modulus decreases significantly, and it can be deformed with a small amount of force. When the temperature exceeds that temperature, the elastic modulus increases and the shape returns to the previously memorized shape.
而して、金属バンプ（３）を設けた半導体チップ（２）
は、基板（４）の導体パターン（５）上にフェースダウ
ンされ、半導体チップ（２）の金属バンプ（３）が形成
された面とは反対面と基板（４）の導体パターン（５）
が形成された面とは反対面の両サイドから形状記憶合金
からなるクリップ部材（１）にて挟み込まれる。前述し
たように、形状記憶合金からなるクリップ部材（１）は
、もともと第３図に示すようにクリップ部材（１）が閉
じた形状で記憶されている。それを−２０℃程度の低温
状態にして弾性力を低下させる。この状態で、第４図の
ように、クリップ部材（１）を開き、そこに半導体チッ
プ（２）をフェースダウンした実装用基板（４）を置（
。この状態で周辺温度を上げていくと、クリップ部材（
１）が第３図のような形状に復帰しようとするため、第
１図のように半導体チップ（２）と実装用基板（４）が
弾性力にて挟み込まれて、両者の電気的接続が行なわれ
、実装が終了する。Thus, a semiconductor chip (2) provided with metal bumps (3)
is face down on the conductor pattern (5) of the substrate (4), and the surface opposite to the surface on which the metal bumps (3) of the semiconductor chip (2) are formed and the conductor pattern (5) of the substrate (4)
It is sandwiched between clip members (1) made of shape memory alloy from both sides opposite to the surface on which is formed. As mentioned above, the clip member (1) made of a shape memory alloy is originally memorized in a closed shape as shown in FIG. It is brought to a low temperature of about -20°C to reduce its elastic force. In this state, as shown in Figure 4, open the clip member (1) and place the mounting board (4) with the semiconductor chip (2) face down there (
. If the ambient temperature is increased in this state, the clip member (
1) tries to return to the shape shown in Figure 3, the semiconductor chip (2) and the mounting board (4) are sandwiched by elastic force as shown in Figure 1, and the electrical connection between them is broken. The implementation is completed.
また、半導体チップの交換は、低温状態にして第４図の
ようにクリップ部材（１）を開くと簡単に行える。Furthermore, the semiconductor chip can be easily replaced by opening the clip member (1) in a low temperature state as shown in FIG.
次に、本発明を液晶表示装置の半導体装に応用した場合
につき、第５図に従い説明する。Next, a case where the present invention is applied to a semiconductor device of a liquid crystal display device will be explained with reference to FIG.
半導体素子（２）は形状記憶合金からなるクリップ部材
（１）にて、対向電極ガラス（７）と基板ガラス（６）
からなる液晶パネルの基板ガラス（６）側に保持固定さ
れる。A semiconductor element (2) is connected to a counter electrode glass (7) and a substrate glass (6) by a clip member (1) made of a shape memory alloy.
It is held and fixed to the substrate glass (6) side of the liquid crystal panel consisting of.
第６図は、本発明をパッケージドＩＣの実装に用いた場
合を示す。FIG. 6 shows a case where the present invention is used for mounting a packaged IC.
第６図に示すように、パッケージドＩＣ（２°）を形状
記憶合金からなるクリップ部材（１）にて挟み込み、両
者を保持して、実装用基板（１ｏ）にパッケージドＩＣ
（２°）を装着する。As shown in Fig. 6, the packaged IC (2°) is sandwiched between clip members (1) made of shape memory alloy, and both are held, and the packaged IC is mounted on the mounting board (1o).
(2°).
尚、本実施例においては、クリップ部材（１）として形
状記憶合金を用いたが、これに限らず樹脂等を用いるこ
ともできる。In this embodiment, a shape memory alloy is used as the clip member (1), but the present invention is not limited to this, and resin or the like may also be used.
（ト）発明の効果
以上説明したように、本発明によれば、基板と単導体素
子が機械的に接触しているので、ハンダ接合のように半
導体素子と基板との熱膨張率の差による接続破壊もな（
、耐熱衝撃特性が向上する。(G) Effects of the Invention As explained above, according to the present invention, since the substrate and the single conductor element are in mechanical contact, the difference in thermal expansion coefficient between the semiconductor element and the substrate is Even the connection is broken (
, thermal shock resistance properties are improved.
また、低温状態で簡単に半導体素子が交換できるため、
リペア性に優れている。In addition, semiconductor elements can be easily replaced at low temperatures.
Excellent repairability.
また、低温状態で実装できるので、半導体素子や周辺素
子に熱影響を与λな（てすむ。Furthermore, since it can be mounted at low temperatures, there is no thermal influence on the semiconductor element or peripheral elements.
さらに、半導体素子と基板の端子部を直接に接触させる
ため、フェースダウンボンディングで見られるハンダブ
リッジもな（、高精細ピッチの接続まで可能となる。Furthermore, since the semiconductor element and the terminals of the substrate are brought into direct contact, it eliminates the solder bridges seen in face-down bonding (and enables high-definition pitch connections).
第１図ないし第４図は本発明の一実施例を示し、第１図
は側面図、第２図は平面図、第３図はクリップ部材を示
す側面図、第４図は実装状態を示す側面図である。
第５図は本発明の異なる実施例を示す斜視図、第６図は
本発明の更に異なる実施例を示す斜視図である。
１・・・クリップ部材、２・・・半導体チップ。
３・・・金属バンプ、４・・・実装用基板、５・・・導
体パターン、６・・・基板ガラス、７・・・対向電極ガ
ラス。
第３図
第２図1 to 4 show one embodiment of the present invention, FIG. 1 is a side view, FIG. 2 is a plan view, FIG. 3 is a side view showing the clip member, and FIG. 4 is a mounting state. FIG. FIG. 5 is a perspective view showing another embodiment of the invention, and FIG. 6 is a perspective view showing still another embodiment of the invention. 1...Clip member, 2...Semiconductor chip. 3... Metal bump, 4... Mounting board, 5... Conductor pattern, 6... Substrate glass, 7... Counter electrode glass. Figure 3Figure 2
Claims (1)
半導体素子と接続される導電性パターンを設けた基板と
、を有する半導体装置であって、前記半導体素子の金属
バンプを有する面と反対面と、前記基板の半導体素子と
の接続面と反対面と、をクリップ部材にて挟み、前記半
導体素子と基板とを保持し、電気的接続を行なうことを
特徴とする半導体装置。(1) A semiconductor device comprising a semiconductor element provided with a metal bump at a connecting portion, and a substrate provided with a conductive pattern connected to the semiconductor element, which is opposite to the surface of the semiconductor element provided with the metal bump. 1. A semiconductor device, wherein the semiconductor element and the substrate are held and electrically connected by holding the semiconductor element and the substrate by sandwiching the surface and the surface of the substrate opposite to the connection surface with the semiconductor element between clip members.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1331607A JPH03190251A (en) | 1989-12-20 | 1989-12-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1331607A JPH03190251A (en) | 1989-12-20 | 1989-12-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03190251A true JPH03190251A (en) | 1991-08-20 |
Family
ID=18245550
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1331607A Pending JPH03190251A (en) | 1989-12-20 | 1989-12-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03190251A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05267998A (en) * | 1991-07-30 | 1993-10-15 | Storidge Technol Partners | Combined latch and shift register circuit |
| US5381316A (en) * | 1992-05-15 | 1995-01-10 | Rohm Co., Ltd. | Electronic part assembly using a shape memory alloy element |
| JP2015056466A (en) * | 2013-09-11 | 2015-03-23 | 三菱電機株式会社 | Electronic component and mounting method thereof |
| JPWO2015053356A1 (en) * | 2013-10-09 | 2017-03-09 | 学校法人早稲田大学 | Electrode connection method and electrode connection structure |
-
1989
- 1989-12-20 JP JP1331607A patent/JPH03190251A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05267998A (en) * | 1991-07-30 | 1993-10-15 | Storidge Technol Partners | Combined latch and shift register circuit |
| US5381316A (en) * | 1992-05-15 | 1995-01-10 | Rohm Co., Ltd. | Electronic part assembly using a shape memory alloy element |
| JP2015056466A (en) * | 2013-09-11 | 2015-03-23 | 三菱電機株式会社 | Electronic component and mounting method thereof |
| JPWO2015053356A1 (en) * | 2013-10-09 | 2017-03-09 | 学校法人早稲田大学 | Electrode connection method and electrode connection structure |
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