JPH031907B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention mainly relates to a stabilized power supply circuit that steps down a battery voltage to form a stabilized voltage, and an electronic timepiece using the same.

Electronic circuits such as battery-powered electronic watches are required to have low power consumption in order to extend battery life.

In general, in circuits such as electronic circuits (hereinafter referred to as CMOS circuits) constructed using complementary insulated gate field effect transistors, the current consumption can be reduced by lowering the power supply voltage supplied to the circuits. be able to.

Therefore, instead of supplying the battery voltage directly to the electronic circuit, it is possible to reduce the power consumption of the entire circuit by, for example, supplying the electronic circuit via a constant voltage circuit which itself has a low current consumption. Can be done.

However, in the above case, a voltage equal to the difference between the battery voltage and the power supply voltage supplied to the electronic circuit appears between the input terminal and the output terminal of the constant voltage circuit, and A current approximately equal to the consumption current flows.

As a result, relatively large power consumption occurs in the constant voltage circuit.

Accordingly, one object of the present invention is to provide a novel and practical stabilized power supply circuit including a step-down circuit.

Another object of the present invention is to provide a novel stabilized power supply circuit including a step-down circuit which itself consumes low power.

Another object of the present invention is to provide a novel stabilized power supply circuit including a step-down circuit and a startup circuit with a desirable configuration.

Another object of the invention is to provide a stabilized power supply circuit with low power consumption and low output impedance.

Another object of the invention is to provide a stabilized power supply circuit with small fluctuations in output voltage.

Another object of the present invention is to provide a stabilized power supply circuit that has reduced voltage characteristics, that is, can form a good output voltage even when the voltage of a power source such as a battery decreases.

Another object of the present invention is to provide a stabilized power supply circuit that uses fewer capacitor elements.

Another object of the present invention is to provide an electronic timepiece with low power consumption by incorporating the above-mentioned stabilized power supply circuit.

Another object of the present invention is to provide a stabilized power supply circuit suitable for a high electromotive force battery power source such as a lithium battery.

Further objects of the invention will become apparent from the following description and drawings.

Hereinafter, this invention will be explained in detail together with examples.

FIG. 1 shows a specific circuit diagram of a stabilized power supply circuit which is an embodiment of the present invention applied to a pointer type electronic wristwatch, and a block diagram of the pointer type electronic watch.

In this example, as the battery power supply _Vss ,
Lithium batteries are used because they can store more energy per unit volume than silver oxide batteries and the like.

Elements constituting each circuit shown in the figure are not particularly limited, but include a battery power supply V _ss , capacitors C ₁ , C ₂ , C ₁₀ ,
Except for C ₁₁ , crystal oscillator X _tal , switch SW and stepping motor, it is constructed on one semiconductor substrate using well-known CMOS (complementary metal oxide semiconductor) integrated circuit technology.

For example, n-type single crystal silicon is used as the semiconductor substrate. On the semiconductor substrate, a p-channel type insulated gate field effect transistor (hereinafter referred to as
MISFET) is formed. A p-type well region is also formed on the semiconductor substrate, and an n-channel MISFET is formed in the p-type well region.

A plurality of MISFETs of the same conductivity type are manufactured simultaneously using semiconductor integrated circuit device manufacturing technology, and therefore have substantially equal threshold voltages.

P1 to _P10 in FIG. ₁ are external terminals of the semiconductor integrated circuit device.

1 is a step-down circuit that utilizes capacitor charge division. As shown in the figure, this step-down circuit 1 includes a switching MISFET Q ₁ , a capacitor C ₁ , a switching MISFET Q ₃ and a capacitor C ₂ , and the capacitor C ₁ connected in series between a battery voltage terminal P 1 and a ground potential terminal P _{2 .} and switching
It consists of a switching MISFETQ ₂ connected in parallel to a series path consisting of MISFETQ ₃ , and a switching MISFETQ ₄ connected in parallel to a series path consisting of the switching MISFETQ ₃ and capacitor C ₂ .

Each of the above switching MISFETQ ₁ to Q ₄ is
In response to the negative polarity of the battery voltage supplied to terminal _P1 , it is of an n-channel type as shown in the figure, and each semiconductor integrated circuit is formed in an independent p-type well region (not shown). be done.

Switching MISFETQ ₁ has its base gate,
That is, the p-type well region is electrically connected to the power supply terminal _P1 , and the base gate of _Q2 is electrically connected to the terminal _P3 . Similarly, switching
MISFETQ ₃ has its base gate electrically connected to terminal _P5 .

A semiconductor substrate serving as a common base gate of the p-channel type switching MISFET _Q4 and various p-channel type MISFETs for configuring various circuits to be described later is electrically connected to a ground potential terminal _P2 .

The capacitors C ₁ and C ₂ can have relatively large capacitances, such as 0.001 μF to 0.1 μF, since the charging voltage therein is used as the power supply voltage to be supplied to the voltage regulator circuit 2 described later. Needed.
However, large capacitance capacitors are difficult to incorporate into semiconductor integrated circuits (ICs). Therefore, in this example, the above capacitor C ₁
and _C2 are externally connected to the IC via terminals _P3 , _P4 , and _P5 .

Output clock pulses φ 1 ′ to _{φ 3} ′ of the clock generation circuit 11 are supplied to the gates of the switching MISFETs Q ₁ to Q ₄ via a level shift circuit 12, which will be described later.

The switching MISFETs _{Q 1} and Q ₃ are simultaneously turned on by clock pulses φ ₂ and φ ₁ , and the switching MISFETs _{Q 2} and Q ₄ are turned on by clock pulses φ ₃ and φ ₁ .
MISFETs Q ₁ and Q ₃ are turned on at the same time in different periods of time.

FIGS. 2A and 2B are diagrams for explaining the operating principle of the voltage step-down circuit.

Capacitors C ₁ and C ₂ are switching
By turning on MISFETs Q ₁ and Q ₃ , they are connected in series as shown in FIG. 2A. In this condition, the above series connected capacitors C ₁ and C ₂
is charged by the voltage of the battery power supply _Vss .

The above capacitors C ₁ and C ₂ are switching
By turning on MISFETs Q ₂ and Q ₄ , they are connected in series as shown in FIG. 2B.

The output voltage of the step-down circuit 1 is
Obtained from between the terminals of _C2 .

By making the capacitances of capacitors C ₁ and C ₂ relatively large as described above, the output voltage of the step-down circuit 1 in the state shown in FIG _. The output voltage of the step-down circuit 1 in the state shown in FIG. _2B is determined by the parallel combined capacitance of capacitors _C1 and _C2 and their accumulated charges. The value is determined by

By making the capacitances of the capacitors _C1 and _C2 equal to each other, the output voltage of the step-down circuit 1 in the state shown in FIG. 2A and the output voltage of the step-down circuit 1 in the state shown in FIG. value, that is, approximately half the voltage of the battery power supply _Vss .

Due to the serial-parallel conversion operation of the capacitors C ₁ and C ₂ above, the current output from the battery power supply V _ss is
The current flowing from the step-down circuit 1 to the voltage regulating circuit used later is approximately half the value.

As is clear from the operation of the step-down circuit 1 above, switching MISFETQ ₁ and Q ₃ are
It only needs to be turned on in a complementary manner to MISFETQ ₂ and Q ₄ , so in principle switching
MISFETQ ₁ , Q ₃ and Q ₄ are driven by the same clock pulse, and switching MISFET _{Q 2} is driven by a clock pulse that is in opposite phase to the clock pulse for driving MISFETQ ₁ , Q ₃ and Q ₄ . can do.

However, in the above case, depending on the rising and falling speed characteristics of the clock pulse, switching MISFETs Q ₁ and Q ₂ and Q ₁ and Q ₄
and may be temporarily turned on at the same time, resulting in the following inconvenience.

First, if switching MISFETQ ₁ and Q ₂ are turned on at the same time, these
The battery power supply V _ss and the capacitor C ₂ will be coupled through MISFETQ ₁ and Q ₂ , so that
The charging voltage of capacitor C ₂ is the voltage of capacitor C ₁ and C ₂
This will increase the value determined by the partial pressure ratio.

As the charging voltage of the capacitor _C2 increases, the voltage applied to the voltage regulating circuit 2 increases, and power loss in the voltage regulating circuit 2 increases.

Similarly, if the switching MISFETs _{Q 1} and Q ₄ are turned on at the same time, the charging voltage of the capacitor C ₁ increases, and this charging voltage of the capacitor C ₁ causes the capacitor C during the parallel conversion operation to increase. ₂ charging pressure is increased. As a result, power loss in the voltage regulating circuit 2 increases.

In this embodiment, in order to prevent the above-described increase in power loss, the timings of clock pulses φ ₁ ' to φ ₃ ' are set as shown in FIGS. 5G to 5I.

The output voltage of the step-down circuit 1 is supplied to the next voltage regulating circuit 2.

The voltage regulator circuit 2 receives the output voltage of the step-down circuit 1 on its input line _l2 , and outputs, on its output line _l3 , a voltage lowered to near the lower limit voltage for operation of each electronic circuit, which will be described later.

The nominal electromotive voltage of a lithium battery is approximately 3V,
Accordingly, the output voltage of the step-down circuit 1 is approximately
It is assumed to be 1.5V. Therefore, the above operating lower limit voltage is
For example, it is set to 1.2V.

The voltage regulator circuit 2 is a p-channel type control circuit whose drain is coupled to the input line _l2 and whose source is coupled to the output line _l3 as shown in the figure.
MISFETQ ₁₄ , a differential amplifier circuit 20 for supplying a control voltage to the gate of the control MISFETQ ₁₄ ,
It is comprised of a reference voltage circuit 21 and a level shift circuit 22 for supplying a reference voltage to the differential amplifier circuit 20.

The reference voltage circuit 21 is composed of MISFETs Q ₅ to Q ₈ and a resistor R ₇ as shown in the figure, although this is not particularly limited.

In the reference voltage circuit 21, the above
Since the gate and drain of MISFETQ ₈ are connected, a constant voltage approximately corresponding to the threshold voltage is generated between the drain and the source. The constant voltage is supplied to the gate of _MISFETQ7 . The MISFET Q ₇ produces a drain current at its drain determined by the constant voltage supplied to its gate and the resistor R ₁ connected to its source.

With the circuit connection shown in the diagram, the drain current of MISFETQ 7 above flows through MISFETQ ₅ , one of which constitutes the current mirror circuit, and the drain current of MISFETQ ₇ is applied accordingly.
A drain current for biasing the MISFETQ ₈ is output from the drain of the MISFETQ ₆ .

The output voltage of the reference voltage circuit 21, i.e.
The drain voltage of MISFETQ ₈ is the differential amplifier circuit 2
0 differential MISFETQ ₁₁ , constant current MISFETQ ₁₃ , and constant current MISFETQ ₁₆ of the level shift circuit 22 .

In the reference voltage circuit 21, immediately after the battery power is turned on, that is, the battery power supply _Vss is connected to the terminals _P1 and _P2.
Immediately after being connected to MISFETQ ₆ , its gate electrode potential is kept at a potential similar to ground potential for a predetermined period of time due to the stray capacitance of the circuit. The MISFETQ ₆ is rendered conductive by its gate-source voltage. As a result, the reference voltage circuit 21 is activated when the battery power is turned on.

The level shift circuit 22 has the constant current
It consists of a MISFETQ ₁₆ and _a diode-connected MISFETQ ₁₅ for level shifting.
Outputs a voltage lowered by the threshold voltage of MISFETQ ₁₅ .

The differential amplifier circuit 20 includes differential MISFETQ ₁₁ , Q ₁₂ ,
Consisting of a constant current MISFETQ ₁₃ provided at the commonly connected sources of the above differential MISFETQ ₁₁ and Q ₁₂ , and MISFETs _{Q 9} and Q ₁₀ forming a current mirror circuit provided at the drains of the above MISFETQ ₁₁ and Q ₁₂ . has been done.

In the differential amplifier circuit 20, the differential
Gates of MISFETQ ₁₁ , Q ₁₂ , and the above differential
The drains of MISFETQ ₁₂ constitute a non-inverting input terminal, an inverting input terminal, and an output terminal, respectively.

This is the non-inverting input terminal of this differential amplifier circuit.
A constant voltage using the threshold voltage of MISFETQ ₈ is applied to the gate of MISFETQ ₁₁ , and the stabilized output voltage V _CL on output line l ₃ is applied to the gate of MISFETQ ₁₂ , which is an inverting input terminal.
The level is shifted according to the threshold voltage of MISFETQ ₁₅ and applied.

The above-mentioned differential amplifier circuit 20 includes the above-mentioned MISFETQ ₈
The MISFETQ ₁₅ for a constant value voltage formed by
The impedance of MISFETQ ₁₄ is controlled so that the level-shifted voltage is equal to the threshold voltage of .

As a result, the stabilized output voltage V _CL outputted to the output line l ₃ is set to a value equal to the sum of the drain-source voltage of the MISFETQ ₈ and the level shift voltage by the MISFETQ ₁₅ .

The above-mentioned regulated output voltage V _CL is set to a value close to the operating lower limit voltage of the circuit as described above by appropriately designing the respective sizes of the above-mentioned MISFETs _{Q 8} and Q ₁₅ and setting their bias current values. .

Note that each of the above-mentioned MISFETs and each of the MISFETs constituting each circuit described later have similar threshold voltages, so that the above-mentioned stabilized output voltage V _CL is
Regardless of variations in the absolute value of the threshold voltage of the MISFET, it will be set to an appropriate value as the power supply voltage for the circuit described later.

The circuits 20 to 22 are each
By appropriate design of MISFETs Q ₅ to Q ₁₆ and resistor R ₁ it is possible to operate with very small bias currents, such as 10 _oA each.

In this embodiment, the power supply for operating the differential amplifier circuit 20 is constituted by the step-down circuit 1, while the reference voltage circuit 21 is operated by the circuit connection as shown in the figure. The power source for this is constituted by a battery power source _Vss .

As mentioned above, the reference voltage circuit 21 is connected to the battery power supply.
If you configure it to operate directly with _Vss , even when the battery voltage drops due to battery exhaustion, etc.
This reference voltage circuit 21 can output a constant voltage as a good reference voltage. Note that the reference voltage circuit 21 may output a constant voltage having a relatively low voltage value corresponding to the threshold voltage of the MISFETQ ₈ . Therefore, in order to further reduce the power consumption of the reference voltage circuit 21, its power supply voltage may be obtained from the step-down circuit 1 in the same way as the differential amplifier circuit 20.

In addition, in Figure 1, the capacitor C ₄ installed between the ground point of the gate circuit of MISFETQ ₁₄
In addition to preventing oscillation in the voltage regulator circuit 2, the overlap capacitance (drain-gate capacitance) existing between the drain and gate of the MISFETQ ₁₄ prevents voltage fluctuations in the step-down voltage formed in the step-down circuit 1 as described above. This is to prevent the regulated output voltage V _CL from being transmitted to the gate of MISFETQ ₁₄ and resulting in fluctuations.
The capacitance value is set to, for example, 20 pF to 40 pF.

The stabilized output voltage V _CL is used as a power supply voltage for each circuit described below.

3 is an oscillation circuit which outputs, for example, a reference frequency signal of 32768 Hz.

The oscillation circuit 3 includes an inverter circuit IV ₁ as an amplifier circuit, an oscillation stabilizing resistor R ₃ , and a bias resistor.
It consists of R ₂ , a crystal oscillator X _tal , and capacitors C ₁₀ and C ₁₁ .

The inverter circuit IV ₁ includes, for example, an n-channel type MISFETQ 20 and a p-channel type MISFETQ ₂₀ as shown in FIG.
It is operated by the power supply voltage V _CL supplied from the voltage constant circuit 2 composed of the channel type MISFETQ ₂₁ .

Although not particularly limited, the above capacitor C ₁₀ is used to determine the oscillation frequency along with the crystal oscillator X _tal
and C ₁₁ are selected from those whose capacitance values have a predetermined temperature coefficient in order to reduce the temperature coefficient of the oscillation frequency, and are therefore configured as external components of the IC.

In the inverter circuit as shown in FIG. 7 above, the power consumption is approximately
It is determined by the charging/discharging current to the capacitor C ₀ existing or coupled to N ₀ and the through current flowing to MISFET _{Q 20} and Q ₂₁ .

That is, the inverter circuit has an input voltage V _i vs. output voltage characteristic as shown by curve A in FIG.

The p-channel type MISFETQ ₂₁ is made conductive by making the input voltage V _i larger than its threshold voltage V _thp , and the n-channel type
MISFETQ ₂₁ is rendered conductive by causing the input voltage V _i to be less than the voltage V _CL on line l ₃ minus its threshold voltage V _tho . Therefore, the above MISFETQ ₂₀ and
The source-drain path of Q ₂₁ has the above input voltage V _i
According to the change in the current, a through current is caused to flow as shown by the solid curve A in FIG.

Further, for example, following a state in which the potential of the output node N ₀ is set to approximately the ground potential due to the conduction state of the MISFETQ ₂₁ and the non-conduction state of the MISFETQ ₂₀ , the conduction and non-conduction of the MISFETQ ₂₁ and Q ₂₂ occur. If the conduction state is reversed, from wire l ₃ above
A charging current will flow through the MISFETQ ₂₀ to the capacitor C ₀ .

According to this embodiment, as the voltage V _CL on the line l ₃ is lowered, the range of the input voltage V _i through which the through current flows is narrowed, and the magnitude of the through current is also reduced.

Furthermore, since the variation range of the output voltage V ₀ is reduced in accordance with the voltage V _CL on the line l ₃ , the charging/discharging current flowing through the capacitor C ₀ is also reduced.

As a result, the inverter circuit shown in FIG. 7 has low power consumption.

In addition, curve B in FIG. 8 has battery power supply V _ss on line _l
The broken line curve B in FIG. 9 shows the through current when the inverter circuit has the characteristics shown in curve B in FIG. 8. It shows the waveform.

The output reference frequency signal of the oscillation circuit 3 in FIG.
It is supplied to an inverter circuit 4 serving as a waveform shaping circuit which receives the voltage _VCL on the line _l3 as a power supply voltage.

Therefore, the inverter circuit 4 outputs a reference frequency signal waveform-shaped as a pulse signal in response to the sinusoidal reference frequency signal output from the oscillation circuit 3.

The output signal of the inverter circuit 4 is fed to the input of the frequency divider circuit ₅ via line l5.

The frequency dividing circuit 5 is composed of 16 flip-flop circuits FF1 to FF16 and an inverter circuit IV7 connected in series as shown in FIG.

The output signal at the output terminal Q of each flip-flop circuit FF1 to FF16 is inverted in synchronization with the falling edge of the clock signal applied to the respective clock input terminal φ.

Therefore, for a reference pulse signal of 32768 Hz supplied via line _l5 , the flip-flop circuit FF
A 16384Hz pulse signal is output to the output terminal of 1, and a pulse signal of 16384 Hz is output to the output terminal of flip-flop circuit FF2.
A pulse signal of 8192Hz is output. Similarly, a 0.5 Hz pulse signal is output to the output terminal of the final stage flip-flop circuit FF16.

The output pulse signals of each frequency from the frequency dividing circuit 5 are supplied to the waveform shaping circuit 6 via lines _l13 to _l14 .

The waveform shaping circuit 6 is provided to form a pulse signal for driving the bipolar stepping motor M, and the waveform shaping circuit ₆ is provided to form a pulse signal for driving the bipolar stepping motor M.
It consists of an appropriate gate circuit that receives V _CL as the power supply voltage.

The waveform shaping circuit 6 outputs pulse signals to the lines _l15 and _l16 which are alternately brought to a high level approximately at the voltage _VCL every second. Although not particularly limited, in order to reduce the drive current flowing through the bipolar stepping motor M, the 2-second period pulse signals on the lines _l15 and _l16 are set at a high level for, for example, 15.6 ms in one period.

In addition, in this embodiment, since the power supply voltage supplied to the terminal _P1 has negative polarity, the signal level that is approximately the ground voltage level of the circuit is regarded as a high level, and the signal level that is approximately the ground voltage level of the circuit is The signal level set to the power supply voltage level is regarded as a low level.

The output pulse signal of the waveform shaping circuit 6 is supplied to output buffer circuits 8 and 9 via a level shift circuit 7.

The output pulse signals of the output buffer circuits 8 and 9 are supplied to the drive coil L of the bipolar stepping motor M via external terminals P ₈ and P ₉ .

The output voltage of the output buffer circuits 8 and 9 is 1
The drive coil L is changed from high level to low level for the above 15.6ms every second.
A drive current whose polarity is reversed every second is applied.

Therefore, the rotor R is rotated by a predetermined rotation angle every second.

The rotor R drives a clock train (not shown) once every second.

The bipolar stepping motor M normally requires a relatively large drive current compared to the operating current of each circuit.

In this embodiment, the output buffer circuits 8 and 9 are configured to operate using the battery power source _Vss as a direct power source through circuit connections as shown.

With the above connection, the load current of the voltage regulating circuit 2 can be reduced, and since the driving current of the stepping motor M is not supplied from the voltage regulating circuit 2, the driving current can be reduced intermittently. The voltage V _CL on the line l ₃ can be made sufficiently stable regardless of the occurrence of such problems.

Further, by the above connection, the power supply voltages of the output buffer circuits 8 and 9 are prevented from being affected by the voltage drop that occurs in the voltage regulating circuit 2. Therefore, even in a state where the voltage of the battery power supply _Vss is relatively reduced, a sufficiently large driving current is supplied to the stepping motor M via the output buffer circuits 8 and 9. You will be able to do this.

The output buffer circuits 8 and 9 are each constructed from complementary inverter circuits as shown in FIG. 7. When the inverter circuit of FIG. 7 is operated by the battery power supply V _ss , the input voltage V _i is at the voltage level of the battery power supply V _ss in order to sufficiently turn off the n-channel type MISFETQ ₂₀ .
is required.

Here, as mentioned above, the line from the waveform shaping circuit 6 is
The low level of the pulse signals output to the lines _l15 and _l16 is set to the level of the stabilizing constant voltage _VCL .

Therefore, in this embodiment, the level shift circuit 7 is provided in order to level shift the low level output signal of the waveform shaping circuit 6 to a low level signal at the voltage level of the battery power supply _Vss .

Although not particularly limited, the level shift circuit 7 is
As shown in FIG. 6, MISFETQ ₂₀ to Q ₂₃ that can be operated with the voltage _Vss as the power supply voltage,
To form an inverted signal for the input voltage V _i ,
Can be operated using voltage V _CL as power supply voltage
Consists of MISFETQ ₂₄ and Q ₂₅ .

Reference numeral 13 denotes a time adjustment circuit which receives a signal from the key switch SW via an external terminal _P10 and outputs a signal to the line _l12 to reset the frequency dividing circuit. This time adjustment circuit 1
3 is the key switch SW when the battery power is turned on.
The configuration is such that a high level signal is output to line _l12 for a predetermined period of time regardless of the operation of.

The clock generating circuit 11 generates clock pulses φ ₁ ' to φ ₃ ' for operating the step-down circuit 1, as described above.

Instead of the configuration of this embodiment, the clock generation circuit 11 includes an oscillation circuit that generates a reference clock by operating with the battery power source _Vss as a direct power source, and a logic circuit that receives the output of the oscillation circuit. can do.

However, in this embodiment, the reference clock is provided from the frequency divider circuit 5 by means of circuit connections as shown in FIG. This eliminates the need to provide the above-mentioned oscillation circuit in the clock generating circuit 11, making it possible to prevent an undesirable increase in the power consumption of the circuit and the number of circuit elements in the semiconductor integrated circuit device.

Further, the clock generation circuit 11 is powered by a battery.
Instead of receiving the voltage of _Vss , it is configured to receive a voltage stepped down by the constant voltage circuit as the power supply voltage.

The low level of the output clock signal of the clock generation circuit 11 is applied to the step-down circuit 1.
A level shift circuit 12 is provided because the level is not sufficient to switch MISFETs Q ₁ and Q ₂ .

The level shift circuit 12 has the same structure as the level shift circuit 7 shown in FIG. Since the level shift circuit 12 has a relatively simple configuration, its power consumption is relatively low.

On the other hand, the clock generating circuit 11 has a relatively complicated structure, as is clear from the specific circuit example shown in FIG. 4, and therefore consumes relatively large amount of power.

Therefore, a configuration in which the power supply voltage of the clock generation circuit 11 is lowered by the step-down circuit 1 and the constant voltage circuit 2 as described above is preferable because the clock generation circuit 11 is operated directly with the voltage of the battery power supply _Vss . As a result, power consumption can be lowered than in the case of a configuration in which the level shift circuit is not used.

In this embodiment, as is clear from the above configuration, when the output voltage of the step-down circuit 1 is 0, the oscillation circuit 3 is not operated, and therefore, the oscillation circuit 3 is not operated. No clock pulses are formed.

In order to cause the voltage necessary for the operation of the oscillation circuit 3 to appear on the line _l3 when the battery voltage _Vss is applied, the step-down circuit 1 supplies the necessary voltage even if the oscillation circuit 3 is not activated. voltage must be output.

Although not particularly limited, in this embodiment, the battery power source
When V _ss is applied, switching MISFETs _{Q 1} to Q ₃ of the step-down circuit 1 are made conductive at the same time.

Therefore, the step-down circuit 1 outputs a voltage approximately equal to the voltage of the battery power supply _Vss , and the voltage regulator circuit 2 outputs a predetermined voltage accordingly.

The above startup state, i.e. switching
The state in which MISFETs Q ₁ to Q ₃ are simultaneously rendered conductive continues for a period of time until the oscillation circuit 3 is brought into a sufficient oscillation state. As a result, activation of each circuit shown in FIG. 1 is guaranteed.

A relatively simple configuration for setting the startup state is such that it is set by the rise of the power supply voltage when the battery power is turned on, and is reset by the rise of the output signal of a predetermined output stage of the frequency divider circuit 5. A configuration can be adopted in which a latch circuit is provided, and the switching MISFETs _Q1 to _Q3 are made conductive at the same time based on the output signal of this latch circuit.

However, in the oscillation circuit 3 that is operated at a relatively low voltage as in this embodiment, it takes a relatively long time to reach a sufficiently stable oscillation state after the power is turned on, and the oscillation circuit 3 operates at a relatively low voltage. It must be noted that this becomes relatively unstable due to fluctuations in the power supply voltage.

When the start-up state ends, the output voltage of the step-down circuit 1 begins to decrease from a voltage approximately equal to the voltage of the battery power supply _Vss as described above. The actual voltage regulating circuit 2 is not a completely ideal circuit. Therefore, the output voltage of the voltage regulator circuit 2 decreases slightly in accordance with the decrease in the output voltage of the step-down circuit 1, and the switching
It begins to fluctuate as the output voltage of the step-down circuit 1 changes with the start of the switch operation of MISFETQ ₁ to Q ₄ .

As a result, the oscillation operation of the oscillation circuit 3 may become unstable immediately after the activation state ends. When the clock pulse time applied to the step-down circuit 1 is changed according to the instability of the oscillation described above, the width of change in the output voltage of the step-down circuit 1 is increased accordingly, and as a result, the oscillation circuit 3 oscillates. The operation may stop.

By stopping the oscillation operation of the oscillation circuit 3, the sequential switching operations of the switching MISFETs _Q1 to _Q4 of the step-down circuit 1 are stopped, and as a result, the voltage on the line _l2 is lowered.
Here, in a complementary MISFET circuit as shown in FIG. 6 that constitutes the level shift circuit 12,
When MISFETQ ₂₂ is made conductive
If the complementary inverter circuit consisting of MISFETQ ₂₄ and Q ₂₅ is disabled, the above
MISFETQ ₂₃ connected in series with MISFETQ ₂₂
It will remain non-conducting no matter what level the input voltage V _i is brought to. Accordingly,
The MISFETQ ₂₂ is kept conductive regardless of the level of the input voltage _Vi . That is, when the output voltage of the voltage regulator circuit ₂ is lowered below the operating lower limit voltage of the complementary inverter circuit due to a voltage drop in the line l2, the level shift circuit 12 performs switching.
It will no longer output clock pulses at a level that would make MISFETQ ₁ to Q ₃ conductive at the same time.

Therefore, if only a latch circuit is simply provided as described above, in order to restart the oscillation operation after the oscillation operation has stopped as described above, the latch circuit must be returned to its initial state by, for example, removing the battery power supply. At the same time, the latch operation between MISFETQ ₂₂ and Q ₂₀ in the level shift circuit 12 must be released.

In this embodiment, an oscillation detection circuit 10 is provided in order to automatically continue the oscillation operation of the oscillation circuit 3.

As shown in FIG. 1, the oscillation detection circuit 10 includes inverter circuits IV ₂ to IV ₆ operated by the power supply voltage on line l ₃ , exclusive OR circuit EOR, resistors R ₄ , R ₅ , Capacitors C ₁₂ and C ₁₃
It consists of

The oscillation detection circuit 10 is supplied with a predetermined output of the frequency dividing circuit 5, for example, the inverted output of the flip-flop circuit _FF5 shown in FIG.

Hereinafter, the operation of the oscillation detection circuit 10 will be explained based on the operation waveform diagram of FIG. 3.

At time t ₀ , battery power source V _ss is turned on.
At this time, the exclusive OR circuit EOR receives a low level signal of approximately the power supply voltage V _CL as shown in FIG. It will start outputting. MISFETQ ₁₇ is the above exclusive OR circuit
It is rendered non-conductive by the low level output signal of EOR. The signal at the input end of the inverter circuit IV ₅ as a waveform shaping circuit is connected to the capacitor
As shown in FIG. 3E, C ₁₃ brings the voltage to a high level, almost the ground potential. Correspondingly, the output signal of the inverter circuit _IV6 is set to a high level as shown in FIG. 5F.

Depending on the vibration start characteristics of the crystal resonator X _tal , the oscillation circuit 3 starts outputting a reference frequency signal from time t ₁ as shown in FIG. 3A.

At time t ₂ , the amplitude of the output reference frequency signal of the oscillation circuit 3 is made sufficiently large, so that the frequency dividing circuit 5 responds to the reference pulse signal supplied via the waveform shaping circuit 4. start.

By applying a predetermined number of reference pulse signals from the above time _t2 , the third pulse signal is applied to the line _l9 from the frequency dividing circuit 5.
As shown in FIG. B, a signal set to low level is output at time _t3 .

The exclusive OR circuit EOR includes an inverter circuit
The mismatched input signals are supplied for a delay time determined by a delay circuit consisting of IV ₂ , IV ₃ , resistor R ₄ , and capacitor C ₁₂ . As a result, the exclusive OR circuit EOR outputs a signal kept at a high level for a time corresponding to the delay time.

By the high level signal of the exclusive OR circuit EOR, MISFETQ ₁₇ is made conductive, and the output signal of the inverter circuit IV ₄ is made low level. Therefore capacitor C ₁₃ has the above
The low level signal of the inverter circuit IV ₄ is supplied via MISFETQ ₁₇ . Above MISFETQ ₁₇
is made non-conductive in response to the output signal of the exclusive OR circuit EOR being returned to low level. Therefore, the above-mentioned low level signal is held in the above-mentioned capacitor _C13 . Similarly, time
After _t4 , each time the signal level supplied from the frequency dividing circuit 5 to the line _l9 is changed, a low level signal is supplied to the capacitor _C13 . Therefore, a signal as shown in FIG. 3E is output on line _l21 .

Corresponding to the low level signal on line l ₂₁ above,
A low level signal as shown in FIG. 3F is output from the inverter circuit IV ₆ to the line l ₂₂ .

The output low level signal of the inverter circuit IV ₆ is regarded as an oscillation operation detection signal of the oscillation circuit 3.

In this embodiment, the output voltage of the voltage regulator circuit 2 is changed to the clock generation circuit 11 and the level shift circuit 1 by stopping the oscillation operation of the oscillation circuit 3.
A resistor _R5 is connected in parallel to the capacitor _C13 in order to change the oscillation operation detection signal from a low level to a high level before the voltage is lowered to the lower limit of operation of the second circuit. .

As a result, when the oscillation operation of the oscillation circuit 3 is stopped, for example immediately after the starting state is ended, the voltage step-down circuit 1 is automatically returned to the starting state.

FIG. 4 shows the frequency dividing circuit 5 and the clock generating circuit 11.
shows a detailed circuit.

The clock generating circuit 11 is composed of latch circuits LA ₁ to LA ₄ , NAND circuits ND ₁ to ND ₇ , and an inverter circuit IV ₈ .

Each of the latch circuits LA ₁ to LA ₄ is composed of two NOR circuits as shown in the figure.

The latch circuits LA ₁ , LA ₂ , NAND circuit ND ₁ and inverter circuit IV ₈ constitute a start-up control circuit.

By means of the latch circuit _LA1 , a high level signal on line _l9 is regarded as a set signal, and a high level signal on line _l10 is regarded as a reset signal. Similarly, the latch circuit LA ₂ treats the high level signal on line l ₂₃ as a set signal and
A high level signal at _l22 is considered a reset signal.

When the battery power supply _Vss is turned on, each flip-flop circuit FF1 to FF constituting the frequency divider circuit 5
16 are each put into a reset state by a high level signal supplied from the time correction circuit 13 via line _l12 .

The latch circuit _LA1 is set by a high level signal supplied from the flip-flop circuit FF5 via line _l9 .

The latch circuit _LA2 is reset by a high level signal supplied from the oscillation detection circuit 10 via line _l22 . Therefore, the signal output from the latch circuit LA ₂ to line l ₂₄ is as shown in FIG.
As shown in , it is set to low level at time t ₀ .

As mentioned above, when the signal on the line _l22 is brought to a low level by the oscillation detection by the oscillation detection circuit 10, the reset state of the latch circuit _LA2 is released.

At time t5, one second after the frequency dividing circuit ₅ starts the frequency division operation, the non-inverted output of the flip-flop circuit FF16 in the frequency dividing circuit 5 changes from low level to high level as shown in FIG. 3C. In response to this, the latch circuit _LA1 is brought into a reset state.

The NAND circuit _ND1 receives, at its two input terminals, signals that are set to high level simultaneously for the delay time of the NOR circuit _NR2 in the latch circuit _LA1 .

As a result, a high level signal as shown in FIG. 3G is outputted to the line _l23 from the inverter circuit _IV8 receiving the output of the NAND circuit _ND1 .

The latch circuit _LA2 is set to a high level signal on line _l23 and outputs a high level signal on line _l24 as shown in FIG. 3H.

The low level signal on the line _l24 is considered an activation state indication signal.

The clock pulses φ ₁ ′ to φ ₃ ′ output from the NAND circuits ND ₅ to ND ₇ are simultaneously set to high level in response to the activation state instruction signal.

The clock pulses φ ₁ ' to φ ₃ ' are supplied to the switching MISFETs _{Q 1} to Q ₄ in the step-down circuit 1 via the level shift circuit 12.

When steady state operation is indicated by the signal on line _l24 going high, the clock pulses φ ₁ ' to φ ₃ ' will be as follows.

5A to 5C show output signal waveforms at the non-inverting output terminals of flip-flop circuits FF3 to FF5 in the frequency dividing circuit 5, respectively.

By connecting as shown in FIG. 4, the NAND circuit _ND5 outputs a clock signal having the same phase as the output signal of the flip-flop circuit _FF5 , as shown in FIG. 5G.

The latch circuit LA ₃ is the flip-flop circuit mentioned above.
By receiving the non-inverted output signal of FF3 and the inverted output signal of FF5, a signal as shown in FIG. 5D is output.

NAND circuit ND ₂ is flip-flop circuit FF
By receiving the non-inverted output signals of FF3 and FF4, a signal as shown in FIG. 5F is output.

The output signals of the latch circuit LA ₃ and NAND circuit ND ₂ are supplied to _the NAND circuit ND 3, and the NAND circuit
Since the output signal of the NAND circuit _ND3 is supplied to _ND6 , the clock signal _φ2 ' as shown in FIG. 5H is outputted from the NAND circuit _ND6 .

Similarly, latch circuit _LA4 outputs a signal as shown in FIG. 5E by receiving the non-inverted output signals of flip-flop circuits FF3 and FF5.

The NAND circuit _ND7 outputs a clock signal _φ3 ' as shown in FIG. 5I in response to the output signals of the latch circuit _LA4 and the NAND circuit _ND2 .

By the clock signal shown in FIG. 5 above, the switching MISFETQ ₃ in the step-down circuit 1 shown in FIG.
Time in one period _t10 to _t16 of the clock signal
It is kept conductive from t ₁₀ to t ₁₃ .

The switching MISFET Q ₁ is brought into a conductive state after a time Z ₁ has elapsed from the above-mentioned time t ₁₀ and is brought into a non-conductive state from a time t ₁₂ earlier than the above-mentioned time t ₁₃ by a time Z ₂ .

Switching MISFETQ ₄ starts from time t ₁₃ above.
It is made conductive during the period _t16 .

The switching MISFET Q ₂ is made conductive from time t ₁₄ , which is a time Z ₃ elapsed from time t ₁₃ , and made non-conductive from time t ₁₅ , which is earlier than time t ₁₆ by time Z ₄ .

Therefore, in this embodiment, it is possible to prevent an undesirable increase in the output voltage of the step-down circuit 1 as described above.

As is well known, battery capacity is determined by the product of its discharge current (output current) and time. For the same battery capacity, a battery with a larger electromotive force will have more stored energy. While the electromotive force of a silver oxide battery is approximately 1.5V, a lithium battery has an electromotive force of approximately 3V.
Therefore, lithium batteries have a larger stored energy per unit volume than silver oxide batteries and the like.

If the step-down circuit 1 is removed from this embodiment, the voltage regulating circuit 2 will be directly supplied with the voltage of the battery power supply. In this case, by using the voltage regulator circuit 2, the current consumption based on the above-mentioned through current and charge/discharge current to the capacitor in each circuit that receives the output voltage of the voltage regulator circuit 2 is reduced. can be done. However, in this case, a current approximately equal to the current flowing through the voltage regulator circuit 2 is passed through the battery power source, and as a result, the characteristics of the lithium battery, which has a high stored energy, cannot be fully utilized.

According to this embodiment, by providing the step-down circuit 1 and the voltage regulating circuit 2, if the current flowing from the voltage regulating circuit 2 to the electronic circuit side is I, the current supplied from the lithium battery is approximately I. /2. Further, the voltage applied to the voltage regulating circuit 2 is stepped down to V _ss /2 of the battery voltage V _ss .
Therefore, power loss in the voltage regulating circuit 2 can be reduced. Further, each electronic circuit is operated by the constant voltage circuit 2 under a low voltage near the operating lower limit voltage. Therefore, it is possible to reduce each power consumption.

That is, according to this embodiment, it becomes possible to fully utilize the characteristics of a lithium battery, which is a high storage energy.

In other words, it is possible to obtain an electronic timepiece that can have a significantly longer battery life compared to a case where the power source is a silver oxide battery or the like.

In this embodiment, in the start-up state as described above, predetermined switching MISFETs in the step-down circuit 1 are made conductive at the same time.
There is no need for a special switching MISFET.

FIG. 10 shows a circuit of another embodiment of the invention.

In this embodiment, as shown in the figure, a relatively large capacitor _C3 is connected to the output side of the voltage regulating circuit 2 via an external terminal _P11 . Note that the other circuits in the figure have the same configuration as the embodiment circuit in FIG. 1.

The capacitor _C3 in this embodiment is provided for the following reasons.

That is, in the voltage regulating circuit 2 shown in the figure, the control MISFETQ ₁₄ has a relatively small current flowing through it, and therefore has a relatively high impedance. Further, signals generated at each circuit node of the level shift circuit 22 and the differential amplifier circuit 20 that constitute the constant voltage circuit 20 are connected to the circuits 22 and 20.
can be changed only at a relatively low speed because each of the circuit nodes is operated with a minute current as described above, and a capacitance such as a parasitic capacitance exists or is coupled to each of the circuit nodes.

On the other hand, the circuits such as the frequency dividing circuit 5 and the waveform shaping circuit 6 are supplied with a consumption current determined by the through current and the charging/discharging current to the capacitor. This current consumption is periodically changed comparatively greatly depending on the operating state of the circuits 5, 6, etc.

As mentioned above, the constant voltage circuit 2 operates at a relatively low speed and has a relatively high output impedance, so that the voltage on the line _l3 can be changed relatively largely depending on the operating state of the circuits 5, 6, etc. described above. Voltage fluctuations in the line _l3 cause undesirable interference of the circuits coupled to the line _l3 with each other.

Providing the capacitor C ₃ as in the embodiment makes it possible to sufficiently reduce the impedance in the line l ₃ , thereby making it possible to prevent the above-mentioned undesired interference.

FIG. 11 shows another embodiment of a stabilized power supply circuit that can reduce the output impedance without increasing the number of external terminals and external capacitors of the IC. In this embodiment, the circuits other than the step-down circuit 1 and the voltage regulator circuit 2 are
This embodiment is the same as the embodiment shown in FIG. Therefore, description of circuits other than the circuits 1 and 2 described above will be omitted below.

In this embodiment, a step-down circuit 1 and a voltage regulator circuit 2 are used.
are integrally constructed. That is, the capacitor C ₃ corresponding to the capacitor C ₂ provided on the ground voltage side of the step-down circuit 1 is connected to the external terminal P ₁₁ as shown in the figure.
For control, which constitutes the voltage regulator circuit 2 via
Provided on the output side of MISFETQ ₁₄ . In other words, the circuit of this embodiment is equivalent to the circuit of the embodiment of FIG. 10 from which capacitor C ₂ and terminal P ₅ are removed.

The operation of this embodiment circuit will now be described in detail with reference to the operational principle diagrams shown in FIGS. 12A and 12B.

FIG. 12A shows a state in which MISFETs Q ₁ and Q ₃ are turned on. In other words, the switch
SW ₁ is connected to the E side, and switch SW ₂ is connected to the H side. Capacitors C ₁ and C ₃ are for control
They will be connected in series via MISFETQ ₁₄ and will therefore be charged from the battery power supply _Vss . In this charging operation, the control circuit
MISFETQ ₁₄ is substantially turned off by the output of differential amplifier circuit 20 when the charging voltage of capacitor C ₃ reaches the reference voltage. Therefore, the capacitors C ₁ and C ₃ are charged with the same amount of charge.

Further, B in the same figure shows a state in which MISFETQ ₂ and Q ₄ are turned on. That is, the switch SW ₁ is connected to the F side, and the switch SW ₂ is connected to the G side, and the capacitor C ₁ is disconnected from the battery power supply V _ss accordingly. In this state, capacitors C ₁ and C ₃ are substantially connected in parallel with the same polarity via MISFETQ ₁₄ . In this parallel connection, capacitor C ₁ is connected in parallel to capacitor C ₃ via MISFETQ ₁₄ , so the charging voltage of capacitor C ₃ is maintained at a constant voltage regardless of the current consumption on the electronic circuit side. be done.

The states of FIG. 12A and B are alternately repeated in response to the application of clock pulses φ ₁ to φ ₃ to switching MISFETs Q ₁ to Q ₄ .

In this embodiment, since the capacitor _C3 is provided on the output side of the voltage regulator circuit 2, the output impedance of the power supply circuit can be sufficiently lowered, and the circuit is similar to the embodiment shown in FIG. It is possible to suppress fluctuations in the output constant voltage to a small level.
Moreover, since only two external capacitors are required for the IC, it can be extremely useful especially for products with limited mounting space, such as thin electronic wristwatches.

In this embodiment, similarly to the previous embodiment, the timing pulses φ ₁ to φ ₃ are set to a high level by the high level of the oscillation detection signal supplied to the line l ₂₂ at the time of startup, and this high level By level timing pulse φ ₁ to φ ₃
MISFETQ ₁ , Q ₂ and Q ₃ are simultaneously turned on and MISFETQ ₄ is turned off. As a result, the battery voltage _Vss is directly applied to the constant voltage circuit 2, and the capacitor _C3 is charged to a predetermined constant voltage.
In this case, capacitor _C1 is
Charging does not occur because MISFETQ ₂ is turned off.

Therefore, the circuit operation after the start-up state ends is as follows. Note that FIGS. 12A to 12E show the signals and clock pulses on line _l24 (see FIG. 4) in the clock generation circuit when the battery power is turned on at time t0 and the starting state is terminated at time t5. φ ₁ to φ ₃ and the output voltage waveform of the voltage regulating circuit 2 are shown.

First, when the clock φ ₂ is set to high level at time t6, the line l ₃ has MISFETQ ₁ and a charge amount of 0.
The voltage of the battery power supply _Vss is supplied through the capacitor _C1 and _MISFETQ3 .

At time t8, when MISFETQ 4 is made conductive by setting the clock pulse φ ₁ to a low level, the source of MISFETQ _{2 is grounded by the MISFETQ 4 and the} capacitor C ₁ whose charge amount is approximately 0. It will be brought to a potential. At this time, the output voltage of the capacitor _C3 is applied to the drain D of the MISFETQ ₂ through the control MISFETQ ₁₄ and the line _l2 , so the pn junction between the drain D and the base gate SUB is applied to the MISFETQ 2. A directional bias will be given.

When the clock pulse φ ₃ is set to a high level at time t9, the MISFET Q ₂ is rendered conductive by forming a channel region on the surface of the p-type well region (not shown) under the gate electrode.

As a result, from the above time t8, the above capacitor C ₃
The charge at is distributed to the capacitor C ₁ via the control MISFETQ ₁₄ , the line l ₂ and the MISFETQ ₂ . As a result, the charging voltage of the capacitor _C3 , ie, the voltage on the line _l3 , is reduced as shown in FIG. 13E.

When the clock pulse φ ₂ is brought to a high level again at time t10, the line l 2 is connected to the line l ₂ via MISFETQ ₁ , the capacitor C ₁ charged by the charge distribution, and MISFETQ _3, in the same way as the operation at time t6. As a result, the charging voltage of the capacitor _C3 rises again to the voltage determined by the characteristics of the voltage regulator circuit 2, as shown in FIG _. 13E. I come to do it.

The fluctuation in the charging voltage of the capacitor _C3 is reduced as shown in FIG. 13E as the capacitor _C1 is gradually charged.

When the voltage at line l ₃ decreases as above,
The oscillation circuit 3 will stop operating.
Further, if the voltage drop is significant, a problem arises in that it becomes impossible to bring the device into the starting state again.

Therefore, in the embodiment shown in FIG. 11, instead of making the capacitance values of the capacitors C ₁ and C ₃ the same, the capacitance value of the capacitor C ₁ is changed to the capacitance value of the capacitor C ₃ .
By making it smaller than , the voltage drop in the capacitor _C3 at the end of the start-up is reduced. In this case, the charging voltage of capacitor _C1 will be increased, so that during normal operation after the start-up condition ends,
When MISFETs Q ₂ and Q ₄ are brought into conduction, there is also the advantage that charge distribution from capacitor C ₁ to capacitor C ₃ is facilitated. That is, the first
In the state shown in Figure 2B, when the holding voltage of capacitor _C3 drops, the voltage from capacitor _C1 charged to a relatively high voltage is
This is because the charge is quickly distributed to the capacitor _C3 via the _MISFETQ14 . However, since capacitor C ₃ needs to be charged to the reference voltage (stabilized output voltage) during charging operation by connecting it in series, capacitors C ₁ and C ₃ are set to a large capacitance ratio that exceeds this voltage. It is not possible.

In the circuit shown in FIG. 11, instead of setting all of the clock pulses φ ₁ to φ ₃ to the high level as described above in the starting state, the clock pulse φ ₁ is set to the low level,
The clock pulses φ ₂ and φ ₃ can be modified to be high, and such a modification can cause the capacitor C ₁ to be charged during the start-up condition. However, even if the capacitor C ₁ is charged in advance as described above, it is difficult to eliminate fluctuations in the charging voltage of the capacitor C ₃ after the start-up state ends.

That is, when the above change is made, the capacitor C ₁ will be charged to the voltage of the battery power supply V _ss in the startup state, and accordingly, the capacitor C ₁ will be charged to the 12th voltage after the startup state ends. This is because if the connection is made as shown in Figure A, the voltage on the line _l2 will be reduced to almost zero due to the charging voltage of the capacitor _C1 .

FIG. 14 shows a circuit of still another embodiment of the invention.

In this embodiment, it is considered that the impedance at the output end of the voltage regulator circuit 2 is sufficiently reduced by the capacitor _C3 , which is externally connected to the IC via the terminal _p11 . It is considered that the two capacitors C ₁ and C ₃ can be equal to each other.

As a result, when assembling electronic watches, etc.,
This eliminates the hassle of having to distinguish between capacitors _C1 and _C3 and connect them to each terminal of the IC.

In this embodiment, as shown in the figure, a MISFET Q ₃₀ is provided between the common connection point of switching MISFETs _{Q 1} and Q ₂ and the terminal P ₃ , and a MISFET Q ₃₁ is provided between the terminal P ₃ and the line l ₃ . provided.

The gate of the MISFETQ ₃₁ is supplied with an activation control signal A having a level amplitude of _-Vss , as shown in FIG. 15A. This activation control signal is established in a level shift circuit such as that in FIG. 6 by applying the signal provided on line l ₂₄ of the circuit of FIG.
MISFETQ ₂₀ can be obtained from the drain.

The gate of MISFETQ ₃₀ above has a battery power supply V _ss
Inverter circuit operated directly by
The activation control signal A is supplied via IN.

Incidentally, level-shifted signals having mutually opposite phases to be supplied to the gates of the two MISFETs Q ₃₀ and Q ₃₁ may be generated from the drains of the MISFETs _{Q 20} and Q ₂₂ in the level shift circuit shown in FIG. 6. In this way, the above inverter circuit
IN can be omitted.

In this embodiment, in the start-up state, clock pulse φ ₁ is set to a low level, and clock pulses φ ₂ and φ ₃ are set to a high level.

In order to obtain the above clock pulse _φ1 , for example, the NAND circuit _ND5 in _FIG . The signal obtained by

The operation of the circuit of this embodiment is as follows.

First, as shown in FIG. 15A, from the time when the battery power is turned on at time t0 until the start-up control signal A is set to low level at time t5, that is, in the start-up state, the high level of the above-mentioned start-up control signal A causes the above-mentioned MISFETQ ₃₁ is turned on and the MISFETQ ₃₀ is turned off.

In the startup state described above, the timing pulse φ ₁ is set to low level and the timing pulses φ ₂ and φ ₃ are set to high level as described above, so that the switching MISFETs _{Q 1} , Q ₂ and Q ₄
is turned on and _Q3 is turned off.

Therefore, in the start-up state, the line _l2 has the above switching _MISFETQ1 turned on.
The voltage of the battery power supply V _ss is supplied through Q 2 and Q ₂ . At this time, since MISFETQ ₃₁ is turned on, capacitor C ₁ is
It will be connected in parallel to capacitor C ₃ via MISFETQ ₃₁ . Note that by turning off MISFETQ ₃₀ , the above capacitor
A direct current path is not formed between C ₁ and the battery power supply V _ss .

In the above startup state, the above capacitor C ₁
and C ₃ are both charged to the voltage V _OL determined by the voltage regulator circuit 2.

At time _t5 , the activation control signal A is brought to a low level, thereby ending the activation state.
After this start-up is completed, the MISFET Q ₃₀ is turned on and Q ₃₁ is turned off.

As mentioned above, capacitor C ₁ is charged to voltage V _CL during start-up conditions. Therefore, no charge dispersion from capacitor C ₃ to C ₁ occurs after the start-up state is terminated, and the 15th
As shown in Figure F, the voltage of the capacitor _C3 , ie, the voltage on the line _l3 , can be made constant regardless of whether it is in the starting state or not.

In addition, for control in the voltage regulator circuit 2
The voltage on the line _l2 to which the drain of MISFETQ ₁₄ is connected is changed as shown in FIG. 15E in normal operation after the start-up condition has ended.

That is, the voltage on the line _l2 is set to the value obtained by subtracting the charging voltage of the capacitor _C1 from the voltage of the battery power supply _Vss by turning on the switching MISFETs _Q1 and _Q3 at time t6. .
At this time, the charging of the above capacitors C ₁ and C ₃ is as follows:
As mentioned above, the line l ₃ i.e. the above capacitor C ₃
When the voltage at is set to the constant voltage _Vss determined by the voltage regulating circuit 2, the voltage is substantially stopped. Correspondingly, the charging voltage on the capacitor _C1 is made relatively small, so that the voltage on the line _l2 is given a relatively large value.

On the other hand, at time t9, switching
By turning on MISFETs _Q4 and _Q2 , the charging voltage of the capacitor _C1 is supplied to the line _l2 . As a result, the voltage on the line _l2 is made relatively small as shown.

FIG. 16 shows a circuit of still another embodiment of the invention.

According to this embodiment, in order to enable the battery to be used for a relatively long time, that is, to extend the battery life, the stabilized power supply is used even when the voltage of the battery power supply _Vss is relatively reduced. A stabilized output voltage of a sufficient value is outputted from the circuit 2.

In this embodiment, the voltage step-down circuit 1 and the voltage regulator circuit 2 are integrally constructed, but in the following description, it is assumed for convenience that they are separated. In this case, the voltage supplied from the step-down circuit 1 to the line _l2 is approximately half the voltage of the battery power supply _Vss , and therefore, with respect to a change in the voltage of the battery power supply _Vss ,
It is changed as shown by curve l ₂ in the characteristic diagram of FIG.

Since the voltage regulator circuit 2 is adapted to receive the output voltage of the step-down circuit 1, it outputs a stabilized voltage if the output voltage of the step-down circuit 1 is substantially equal to or higher than the stabilized voltage.

When only the step-down voltage formed by the step-down operation of the step-down circuit 1 is supplied to the voltage regulator circuit 1, the step-down voltage becomes lower than the stabilized voltage due to a slight decrease in the voltage of the battery voltage _Vss . If the voltage is also lowered, the output voltage of the voltage regulator circuit 1 will be lowered accordingly. That is, the output voltage of the voltage regulator circuit 1 is lowered from point D in FIG. 17 in accordance with the output voltage of the step-down circuit 1. As a result, it becomes necessary to replace the battery power supply even though the battery power supply _Vss is still outputting a relatively high voltage.

According to this embodiment, in order to improve the voltage reduction characteristics, in other words, to extend the battery life, the step-down voltage output from the step-down circuit 1 is adjusted approximately according to the decrease in the voltage of the battery power supply _Vss . If the voltage is lowered to the above regulated voltage, the battery power supply
The voltage of _Vss is directly supplied to the voltage regulating circuit 2. Accordingly, the output voltage of the voltage regulator circuit ₂ is reduced to point _C in FIG. stabilized.

The configuration of this embodiment will be explained in detail below.

The step-down circuit 1 has a similar structure to the circuit shown in FIG. 14 above. In the starting state, clock pulse _φ1 is set to low level and clock pulses _φ2 and _φ3 are set to high level. In response, switching MISFETQ ₁ , Q ₂ and Q ₄ are rendered conductive, and switching MISFET Q ₃ is rendered non-conductive. Also, MISFETQ ₃₀ is a level shift circuit 29
MISFETQ 31 is made non-conductive by a low-level control signal supplied from MISFETQ ₃₁ , and made conductive by a high-level control signal.

The voltage regulator circuit 2 is composed of a control MISFET Q ₁₄ , a differential amplifier circuit 20, a reference voltage circuit 21, and a level shift circuit 22, as in each of the embodiments described above.

Inside the clock circuit 31, a plurality of power supply wirings are formed according to the idea of the present invention, and a level shift circuit is formed as necessary, but basically it is composed of various known circuits. Ru. Although not particularly limited, this clock circuit 31 may include, for example, an oscillation circuit that forms a reference frequency signal, a frequency divider circuit that forms a second clock signal by receiving the reference frequency signal output from the oscillation circuit, and the frequency divider circuit described above. 1 for 10 seconds by receiving the output signal of
Various time counter circuits that output time data such as minutes, 10 minutes, 1 hour, 10 hours, 1 day, 10 days, etc., display decoder circuits that convert the output signals of the various time counter circuits to display signals, and the above an output buffer circuit that receives the output signal of the display decoder circuit;
Stopwatch circuit, alarm circuit, external terminal
Switch SW ₁ and connected via P ₁₀ and P ₂₂
A mode selection circuit for selecting various watch modes such as normal watch operation mode, time adjustment mode, stopwatch mode, and alarm mode by detecting the operating order of SW ₂ ; Output signal and above switch SW ₁ or
It is comprised of a control circuit for controlling the operations of the various circuits described above in accordance with the combination with the signals from SW ₂ , an output buffer circuit that receives the output signal of the alarm circuit, and the like.

The clock circuit 31 includes an oscillation circuit, a timing pulse generation circuit, a random access memory in which time data, operation mode data, stopwatch data, alarm data, etc. are written, and a read-only memory (in which microinstructions are written). It can also be constructed from a known ROM-RAM type circuit comprising a ROM), a program counter, an arithmetic logic unit, various decoder circuits, and the like.

From the clock circuit 31, for example, as shown in the figure, a display decode signal for driving a display device DSP having liquid crystal display segments arranged in a date shape for each digit, and an alarm sound are provided. Acoustic exchange means SP composed of piezoelectric elements etc.
, and various clock signals and control signals to be supplied to various circuits to be described later.

The output buffer circuit provided in the clock circuit 31 for driving the acoustic transducer SP requires a relatively large drive current, so it is powered by a battery.
Operated by direct voltage of _Vss .

In this embodiment, in order to detect the voltage of the battery power supply _Vss , a voltage comparator circuit 25 is used as shown in the figure.
is provided.

The voltage comparator circuit 25 has its non-inverting input terminal supplied with the constant voltage formed by the reference voltage circuit 21, and its inverting input terminal supplied with a resistor.
The voltage of the battery power supply _Vss is supplied through a voltage dividing circuit composed of _R2 and _R3 .

When the voltage of the battery power supply _Vss is lowered to the value to be detected (detection level), the divided voltage output from the voltage divider circuit is set by appropriately setting the voltage dividing ratio. That is, when the voltage is lowered to approximately V _ss ' in FIG. 17 or a slightly larger value, it is made equal to the output voltage of the reference voltage circuit 21.

Therefore, when the voltage of the battery power source _Vss is lowered below the detection level, the output voltage of the voltage comparison circuit 25 is set to a high level in response.

Although not particularly limited, in this example,
The voltage divider circuit and voltage comparison circuit 25 are operated intermittently to reduce their average current consumption. In order to operate the voltage dividing circuit intermittently, a switching MISFET Q ₃₂ is provided which is turned on by a clock pulse φ ₀ as shown in the figure. Further, the voltage comparison circuit 25 is supplied with the same clock pulse φ ₀ supplied to the switching MISFETQ ₃₂ .

Note that the voltage comparison circuit 25 has a configuration similar to, for example, the differential amplifier circuit 20 in FIG. 1. For the above intermittent operation, the constant current shown in Figure 1 above is required.
The clock pulse φ ₀ is supplied to the gate of a MISFET similar to MISFETQ ₁₃ .

In order to form a continuous signal based on the intermittent output signal output from the voltage comparison circuit 25, a latch circuit 26 is provided as shown.

Since the voltage comparison circuit 25 is activated by the clock pulse φ ₀ , the same clock pulse as the clock pulse φ ₀ supplied to the voltage comparison circuit 25 is supplied to the data input terminal of the latch circuit 26 . .

The clock pulse φ ₀ can be obtained from a waveform shaping circuit 30 that receives reference clock signals of various frequencies output from a clock circuit 31, as shown. By obtaining the clock pulse φ ₀ with such a configuration, it becomes possible to synchronize the change timing of the output signal of the latch circuit 26 with the change timing of the clock pulses φ ₁ to φ ₃ . .

The output signal of the latch circuit 26 is supplied to the activation control circuit 28 via the NOR gate circuit 27.

Note that the gate circuit 27 is used in an electronic watch.
This is provided in response to the provision of an alarm circuit and a display means requiring a relatively large drive current, such as the acoustic transducer SP driven by the output of this circuit, as described above.

The remaining input terminals of the gate circuit 27 are connected to
From the control circuit in the clock circuit 31 via l ₄₁ ,
A control signal φ _C that is set to a high level is supplied in synchronization with the timing at which a drive current is applied to the display means.

Here, the battery power supply V _ss usually has a relatively large internal resistance, and therefore, when a large current is passed in accordance with the large drive current as described above, its output voltage is relatively significantly reduced. It turns out. This drop in the voltage of the battery power supply _Vss is detected by the voltage comparator circuit 25. However, there will be some time delay before the voltage drop mentioned above is detected.

When the gate circuit 27 and the control signal φ _C are used, there is no need to wait for the voltage drop detection output based on the output signal of the voltage comparison circuit 25.

As a result, as will become clear from the explanation below, the voltage of the battery power source V _ss is supplied to the voltage regulator circuit 27 before the voltage of the battery power source V _ss is lowered, and the line l ₃ This makes it possible to prevent undesired voltage drops in the

In the drawings of this embodiment, the start control circuit 28 is shown independently of the clock generation circuit 11' for ease of understanding.

The details of this activation control circuit 28 are shown in FIG. As is clear from the drawing, this activation control circuit 28 has a configuration in which a NAND circuit ND ₁₀ and an inverter circuit IV ₂₀ are added to the activation control circuit of FIG. 4.

One input terminal of the above NAND circuit ND ₁₀ has a wire
A signal is supplied from the NOR gate circuit 27 via _l43 to a low level when a drop in battery power supply voltage is detected and when an alarm is displayed. Therefore, the startup control circuit 28 outputs a low level signal to the line _l24 not only in the startup state but also when the output of the NOR gate circuit 27 is set to low level.

In addition, in FIG. 18, the clock generation circuit 11'
Some of them are also shown. The clock pulse φ ₁ ' outputted from the illustrated NOR circuit NR ₁₀ is set to a low level in response to the signal on the line _l24 being set to a low level.

FIGS. 19A to 19G show operational waveform diagrams of the circuit shown in FIG. 16. In addition, in FIG. 19, V _DD (+) means the ground potential of the circuit,
V _ss (-) indicates a potential corresponding to the output potential of the battery power supply V _ss .

According to this embodiment, even if the step-down voltage falls below the stabilized output voltage, the stabilized output voltage at a predetermined level can be obtained by the above operation switching.
Effective use of the battery voltage _Vss is achieved, and by improving the voltage reduction characteristics, the battery life can be extended. In particular, lithium batteries have a high internal resistance of several hundred ohms, and in operating modes with large current consumption, the voltage drop is large. It is particularly suitable when

This invention is not limited to the above embodiments. For example, a circuit as shown in FIG. 20 can be used instead of circuits 1 and 2 in FIGS. 14 and 16. Incidentally, in FIG. 20, the same symbols are attached to elements corresponding to the respective elements of the above-mentioned embodiment.

In the circuit of FIG. 20, in the startup state and when the battery power supply voltage drops, the clock pulses φ ₁ to φ ₃ and the control signal A are set to high level, and the control signal is set to low level. Depending on the signals at each level, switching MISFETQ ₁ to Q ₃ and MISFETQ ₃₁ are rendered conductive, and switching MISFETQ ₄ and MISFETQ ₃₀ are rendered non-conductive. Therefore, capacitor C ₁ is substantially connected to battery power supply V _ss and capacitor C ₃ . By connecting the capacitors C ₁ and C ₃ in series, the capacitor C ₃ becomes
It is charged not only from the control MISFET Q ₁₄ but also through the capacitor C ₁ mentioned above. As a result, when the battery power is turned on, the voltage output to the line _l3 can rise quickly. At the same time, the capacitor _C1 is charged within a relatively short time.

After the startup state ends, the control signal A is set to low level and high level, respectively, and
Clock pulses φ ₁ to φ ₃ are varied sequentially as in the previous embodiment.

The above circuits 1 and 2 in FIGS. 14 and 16 above
can be further modified as shown in FIG.

In the circuit shown in FIG. 21, in the startup state and when the battery power supply voltage drops, the clock pulses φ ₁ to φ ₃ are set to low level and the control signal A is set to high level, so that switching is performed.
MISFETQ ₁ to Q ₃ are rendered nonconductive, and switching MISFETQ ₄ , MISFETQ ₃₀ and Q ₃₁ are rendered conductive. As a result, MISFETQ ₁₄ for control
The battery voltage will be supplied to the drain of the battery via MISFETQ ₃₀ . Also, capacitor _C1 has
A constant voltage output to line l ₃ will be supplied via MISFETQ ₃₁ .

After the start-up state ends, the control signal A is set to low level, and the clock pulses φ ₁ to φ ₃
are sequentially changed as in the previous embodiment.

According to the circuit configuration shown in FIG. 21 above, the charging and discharging path of the capacitor C ₁ after the start-up state ends is as follows:
Only configured by switching MISFETQ ₁ to Q ₄ . Therefore, it is possible to prevent voltage loss and power loss from occurring when the MISFETQ ₃₀ is inserted in series in the charging/discharging path of the capacitor _C1 . Also, the above MISFETQ ₃₀
and Q ₃₁ are operated in phase, so that only one control signal A needs to be generated.

The timing pulse supplied to the step-down circuit 1 may be a two-phase timing pulse. However, when starting or improving voltage reduction using the switching means in this step-down circuit, it is convenient to use eight-phase timing pulses that can easily turn on MISFETQ ₁ and Q ₂ at the same time.

In addition, the improvement in voltage reduction characteristics is shown in Figures 1 and 10.
The same applies to the embodiment circuits shown in FIG. 1, FIG. 11, and FIG. 14. Furthermore, the differential amplifier circuit 20 in the voltage regulating circuit 2 may be driven by a clock to further reduce its current consumption. In this case, the capacitor
C ₄ will hold the gate control voltage of MISFETQ ₁₄ .

Moreover, the specific circuit of each circuit block in the embodiment may be any circuit as long as it performs the operation described above.

Furthermore, the present invention can be widely used in small-sized electronic devices that are mainly powered by batteries, such as pointer type electronic watches and digital type electronic watches.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention;
Figures 2A and B are diagrams of its operating principle, and Figure 3 is:
4 is a concrete logic circuit diagram of blocks 5 and 11 in FIG. 1, FIG. 5 is an operating waveform diagram of the circuit in FIG. 4, and FIG. Figure 7 is a circuit diagram of a level shift circuit, Figure 7 is a circuit diagram of an inverter circuit, Figures 8 and 9 are characteristic curve diagrams of the circuit shown in Figure 7, and Figure 10 is another embodiment of the present invention. 11 is a circuit diagram of still another embodiment of the present invention, FIGS. 12A and B are operational principle diagrams of the circuit shown in FIG. 11, and FIG. 13 is a circuit diagram of another embodiment of the invention. FIG. 14 is a circuit diagram of another embodiment of the present invention, FIG. 15 is an operating waveform diagram of the circuit shown in FIG. 14, and FIG. 16 is a diagram of still another embodiment of the present invention. The circuit diagram, Fig. 17 is a characteristic curve diagram of the circuit shown in Fig. 16 above, and Fig. 18 is a characteristic curve diagram of the circuit shown in Fig. 1 above.
Specific logic circuit diagram of block 28 in Fig. 6, 1st
Figure 9 is an operating waveform diagram of the circuit in Figure 16 above, and Figure 20
21 and 21 are circuit diagrams of still other embodiments, respectively. 1... Step-down circuit, 2... Constant voltage circuit, 3...
Oscillation circuit, 4... Waveform shaping circuit, 5... Frequency dividing circuit, 6... Waveform shaping circuit, 7... Level shift circuit, 8, 9... Output buffer circuit, 10... Oscillation detection circuit, 11... Clock generation circuit, 12...
Level shift circuit, 20...Differential amplifier circuit, 21
...Reference voltage circuit, 25...Voltage comparison circuit.

Claims (1)

[Scope of Claims] 1. A power supply voltage supply point; a first and second connection point; a constant voltage circuit having an input coupled to the first connection point and an output coupled to the second connection point; a first capacitor and a second capacitor provided between the two connection points and a reference potential point of the circuit; and at a first timing, the first and second capacitors connect to the power supply voltage supply point via the constant voltage circuit. The second capacitor is connected between the power supply point and the first connection point so as to be connected in series with a reference potential point of the circuit, and the charging voltage of the second capacitor is set at a second timing. a switch circuit that connects the second capacitor between the first connection point and a reference potential point of the circuit so that the second capacitor is supplied to the first connection point; A stabilized power supply circuit characterized in that the output voltage is obtained from the second connection point in accordance with the alternating repetition of the above. 2 The constant voltage circuit includes a differential amplifier circuit that forms a control voltage by inputting and receiving the potential at the second connection point and a desired reference potential, and the first connection point and the second connection. 2. The stabilized power supply circuit according to claim 1, further comprising a variable impedance element provided between a point and a variable impedance element whose impedance is controlled by the control voltage. 3. The stabilized power supply circuit according to claim 1 or 2, wherein the differential amplifier circuit and the variable impedance element are composed of MISFETs. 4 The switch circuit is a switch that, when the power is turned on, causes the second capacitor to supply the voltage of the power supply voltage supply point to the first connection point, and charges the second capacitor with the output of the constant voltage circuit. One of claims 1 to 3, characterized in that the invention comprises an element.
The stabilized power supply circuit described in .