JPH03191435A - Vertical parity bit deleting device - Google Patents

Abstract

PURPOSE:To replace a recorded error with a horizontal parity and to send the replaced parity by allowing a vertical parity deleting part to delete a vertical parity byt from data whose vertical parity error is inspected and send the parity bit-deleted data. CONSTITUTION:A vertical parity inspection part 2 inspects the presence of a vertical parity error in character data received from a data receiving part 1. At the time of deciding the presence of an error, the error is recorded in a vertical parity error recording part 3. The vertical parity deleting part 4 deletes the vertical parity bit from the character data inspected by the inspection part 2 and sends the parity bit-deleted data. A horizontal parity calculating part 5 checks the presence of a vertical parity error in the character data in a block by referring the recording part 3, and when no error is recorded, horizontal parity data to be successively received are sent as they are. When an error is recorded, the inversion of inputted horizontal parity data having no error is sent to a data transmission part 6 as a new horizontal parity data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the conversion of communication data, and relates to a vertical/measured tipit deletion device in error control capable of replacing vertical parity errors with horizontal parity errors.

[Conventional technology]

Conventionally, this kind of vertical parity bit removal device.

It only has a data receiving section, a vertical tip deleting section, and a data transmitting section, and only deletes vertical and spear tip pits from the received data.

[Problem to be solved by the invention]

The conversion of the data string by the conventional vertical t4 I) tipit deletion device described above simply deletes the vertical a41) tipit, so pit errors that occur during transmission are eliminated by horizontal parity checking after conversion. It was detected only when Therefore, types of pit errors that cannot be detected by the Mizuko Nocriti test, e.g.

If an error occurs such as a double error of pits in the same position of a different character or a mixture of two characters of the same character, there is a drawback that it cannot be detected. The present invention was made to solve these problems.

An object of the present invention is to provide a vertical parity bit deletion device capable of detecting vertical parity errors without overlooking them by horizontal parity inspection.

[Means to solve the problem]

In order to achieve the above object, the vertical parity bit deletion device of the present invention includes a data receiving section, a vertical parity checking section for inspecting the vertical/chillity of data inputted from the data receiving section for the presence or absence of an error, and When the vertical parity checking unit determines that there is an error in the vertical matrix, a vertical parity error recording unit records the error, and the vertical parity checking unit records the error in the vertical matrix. A vertical parity deletion section that inputs data that has been inspected for the presence or absence of data and deletes its vertical parity bit, and a vertical parity error recording section that checks whether there is an error in the vertical parity of data within one block. The horizontal/grity calculation unit is provided with a horizontal/grity calculation unit that replaces the data with horizontal/9-quality and sends the data when it is recognized, and a data transmission unit that transmits the data input from the horizontal/grity calculation unit.

[For production]

The data receiving section sequentially receives data strings forming the Glock. The vertical parity checking unit checks whether there is an error in the vertical parity of the data input from the data receiving unit. When an error is detected in vertical/yelty,
It is recorded in the vertical no-criticity error recording section. The vertical notality deletion unit deletes the vertical parity bits of the data that has been checked for errors in vertical noity and transmits the data. When the horizontal parity calculating section finishes receiving the data in the block, it refers to the parity error recording section and records whether there is an error in the vertical t4 parity of the data in the block. If no error is recorded, the horizontal/yelty is sent as is. If an error is recorded, it is replaced with horizontal parity and sent. On the receiving side, the presence or absence of an error in data within a block is recognized by the horizontal parity transmitted with K of 1 or more.

〔Example〕

Next, one embodiment of the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a vertical parity pit deletion device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of the structure of one block of data string before conversion of character data to be transmitted.

FIG. 3 is a diagram showing the structure of the data string in FIG. 2 after conversion.

In FIG. 1, 1 is a data receiving section, 2 is a vertical nonity checking section for checking whether there is an error in the vertical parity of character data input from the data receiving section 1, and 3 is a vertical/
When it is determined that there is an error in the vertical parity of character data by the parity checking section 2, a vertical/parity error recording section 5 records it; A vertical parity bit deletion unit 5 inputs data and deletes its vertical parity pit, and a vertical parity bit deletion unit 5 refers to the vertical/measurement error recording unit 3 and detects that there is an error in the vertical parity of r-unit in the block. When recognized, a horizontal/spicy tee calculation section replaces it with a horizontal/9 lity and sends it out. 6 is a data transmitting section that sends the data input from the horizontal nocrity calculating section.

Next, the operation of this embodiment will be explained.

The data receiving section 1#'i sequentially receives character data consisting of data blocks configured as shown in FIG. 2, and the vertical parity checking section 2 checks whether there is an error in the vertical parity of the character data. Test results.

If it is determined that there is an error in the vertical/9-quality, it is recorded in the vertical/9-quality error recording section 3.

The vertical parity deletion unit 4 deletes the vertical parity bits of the character data that has been checked for vertical and medium parity errors by the vertical parity checking unit 2, and sends it out. Each of the character data received in the above manner is sequentially inspected for vertical/yariness errors, recorded whether or not there are any errors as a result of the inspection, and deleted vertical/yariness pits. Then, when the data receiving unit 1 receives the termination code of the data block after finishing receiving each character data in the block, the horizontal/9 parity calculating unit 5 refers to the parity error recording unit 3 and Checks whether there is an error in the vertical parity of the character data, and if no error is recorded, sends the next received horizontal parity data (if there is no error, set it to 1, for example, bit "0") as is. However, if an error is recorded, the inverted horizontal/matrix data (according to the above example, 2's complement ``1'') of the input horizontal/matrix data when there is no error is used as the new horizontal/matrix data.
4' Send to the data transmitter 6 as IJT data.

As described above, the data transmission section 6 sequentially sends out a data string having the configuration shown in FIG. 3.

〔Effect of the invention〕

As explained above, according to the present invention, when a vertical/matrix error due to a bit error during transmission is detected,
After deleting the vertical/yarity pit, change it to horizontal/4' I
It becomes possible to send it as a J-tier error.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a vertically extending tibit deletion device according to an embodiment of the present invention. FIG. 2 is a diagram showing an example of the structure of one block of data string before conversion of character data to be transmitted. FIG. 3 is a diagram showing the structure of the data string in FIG. 2 after conversion. 1...Data receiving section, 2...Vertical parity checking section, 3...Low parity error recording section, 4...Vertical parity deletion section, 5...Horizontal/1 parity calculation section , 6...
Data transmission section.

Claims (1)

[Scope of Claims] A data receiving unit; a vertical parity checking unit that checks whether there is an error in the vertical parity of data input from the data receiving unit; and the vertical parity checking unit determines that there is an error in the vertical parity. a vertical parity error recording unit that records the vertical parity error when a vertical parity error occurs, and a vertical parity bit deletion unit that inputs the data that has been checked for vertical parity errors from the vertical parity checking unit and deletes the vertical parity bit. and a horizontal parity calculation unit that refers to the vertical parity error recording unit and recognizes that there is an error in the vertical parity of the data in the block, replaces it with horizontal parity and sends it, and from the horizontal parity calculation unit. 1. A vertical parity bit deletion device for error control, comprising: a data transmitting section that transmits input data.