JPH03192576A - Information recording and reproducing device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information recording and reproducing apparatus that records and reproduces information using a recording medium such as an optical disk or a magneto-optical disk.

[Prior Art] FIGS. 7 and 8 are block diagrams of a signal processing system of a general digital information recording/reproducing device. FIG. 7 is a block diagram of the recording system, and FIG. 8 is a block diagram of the reproduction system.

As shown in FIG. 7, the recording system includes an encoding circuit 1, a synchronization pattern adding circuit 2, an amplifier 3. It consists of a recording transducer 4. Recorded data is encoded by an encoding circuit 1, a sync pattern is added by a sync pattern adding circuit 2, and then amplified by an amplifier 3. The amplified data is sent to a recording transducer 4 where it is recorded on a recording medium 5. As the recording medium 5, various media can be used, such as a disc-shaped one such as an optical disc or a magneto-optical disc, a tape-shaped one, or a card-shaped one.

On the other hand, the reproduction system is as shown in FIG. In addition, when the PLL 9 is regenerated by the self-clocking regeneration method, the discriminator circuit 10 is a circuit that creates a synchronized clock from the regenerated signal and converts it into a binary signal. This is a circuit that synchronizes data and creates synchronous data.

The sector mark detection circuit 11 is a circuit that detects sector marks recorded on the recording medium 5 and outputs a sector mark detection signal (SM flaw signal. This SM flaw signal is sent to the synchronization pattern detection circuit 12, The synchronization pattern added by the synchronization pattern adding circuit 2 is detected as a flaw signal reference, and a synchronization pulse is output based on this.The synchronization pattern indicates the reading start position of the code data, and the decoding circuit 12 Based on this, the encoded data is decoded to the original data.The encoding methods include FM, MF
Various types are known, such as M, Miller'', EFM, (2, 7), etc.

FIG. 9 shows an example of the recording format of the recording medium 5.
In the figure, SM is a sector mark and Sync is a synchronization pattern. In this example, the sector mark is 5B (byte),
Synchronous Bakun is 3B. Synchronous pattern detection circuit 12
As described above, the synchronization pattern is detected using the sector mark as a reference.

Note that the VFO is a constant cycle pattern for locking the PLL 9.

An example of the discrimination circuit 10 is shown in FIG. 1O. In this example, the discrimination circuit 10 includes two D-type flip-flop circuits C.
(hereinafter referred to as an FF circuit).

One signal is always input to the DM terminal of the FF circuit 14, and the CK
Binary data is input to the (clock) terminal. Also,
The output signal of the FF circuit 14 is input to the D terminal of the FF circuit 15, and the synchronous clock is input to the CK terminal.

Next, the operation of the discrimination circuit 10 will be explained with reference to the time chart shown in FIG.

Fig. 11 (al is the reproduction signal read out by the reproduction transducer 6, Fig. 11 (bl is binary data obtained by binarizing this reproduction signal by the binarization circuit 8, Fig. 11 fc) is the PLL.
This is the synchronous clock generated in 9. Also, Figure 11 f
dl is the output signal of the FF circuit 14. One period t of the synchronization clock is determined as a detection window for a rising edge of binary data. In other words, the discrimination circuit 10
When binary data rises during ±1/2t of the synchronization clock, the binary data is determined as a pulse.

Therefore, in FIG. 11, since the binary data rises in the window period of ±1/2t, the FF circuit 15
Synchronous data is output as shown in Figure (el).

[Problems to be Solved by the Invention] By the way, if the synchronization pattern cannot be detected correctly, the reading start position of the code data will become unknown, making it impossible to reproduce the data.

Therefore, if the synchronization pattern recording area of the recording medium is defective or scratched, it will be difficult to reproduce the data6.Normally, an information recording/reproducing device reproduces the data after recording is completed to ensure that it is correctly recorded. It has a verification function to check whether the data is correct or not.

However, recording media change over time, and devices also have unstable factors such as changes in environmental conditions and variations in characteristics between devices. Therefore, if the defect or scratch on the recording medium is small, even if the synchronization pattern is accidentally detected correctly during verification, it may not be detected correctly during subsequent playback due to the unstable factors described above. In such a case, it becomes difficult to reproduce the data, and there is a problem in that the data cannot be reproduced.

The present invention has been made to solve these problems, and its purpose is to provide an information recording and reproducing device that can correctly reproduce synchronization patterns and stably reproduce data. .

[Means for Solving the Problems] In order to achieve the above object, in an information recording/reproducing apparatus that binarizes data read from a recording medium and discriminates the signal using a pulse discrimination detection window of a predetermined period, the recording medium An information recording and reproducing apparatus is provided, comprising means for narrowing the pulse discrimination detection window when detecting a synchronization pattern indicating a reading start position of data recorded in the information recording apparatus than when reproducing other data. .

[Operation] In the present invention, when detecting a synchronization pattern indicating the read start position of data recorded on a recording medium, the pulse discrimination detection window is made narrower than when reproducing other data. This allows the synchronization pattern to be detected under stricter conditions, making it possible to discover and repair the cause of the synchronization pattern abnormality at an early stage. Therefore, if there is a small defect or scratch in the synchronization pattern recording area of the recording medium, it is possible to prevent a situation in which playback becomes impossible in the future due to this.

[Examples] Examples of the present invention will be described in detail below with reference to the drawings. First, the basic idea of the present invention will be explained.

Due to defects or scratches near the sync pattern recording area of the recording medium, it is currently only possible to correctly detect the sync pattern. However, it is assumed that there is a possibility that accurate detection may not be possible in the future due to changes in the recording medium over time. In such a case, if defects, scratches, etc. are found during recording verification, they should be processed as verification NG at that time. Therefore, in the present invention, when detecting a synchronization pattern, the pulse discrimination detection window is made narrower than when reproducing other data. The operation of narrowing the pulse discrimination detection window is most preferably performed during recording verification performed immediately after the recording operation, but it may of course also be performed during normal reproduction.

Therefore, specific embodiments of the present invention will be described. FIG. 1 is a block diagram showing an embodiment of the information recording/reproducing apparatus of the present invention. In FIG. 1, the same parts as those of the conventional device are designated by the same reference numerals, and the explanation thereof will be omitted.

In FIG. 1, a first discrimination circuit 16 and a second discrimination circuit 1
Reference numeral 7 denotes a pulse discrimination circuit that detects the rising edge of the binary data output from the binarization circuit 8 in each predetermined pulse discrimination detection window. As the first discrimination circuit 16, the circuit shown in FIG. 10 is used in this embodiment. On the other hand, as the second discrimination circuit 17, a circuit configuration shown in FIG. 2 is used. The discrimination circuit shown in FIG. 10 has a pulse discrimination detection window of ±1/2t as described above, but the second
The pulse discrimination detection window of the discrimination circuit 16 is ±1/4 of that half.
It is set to t.

The selector 18 includes a first discrimination circuit 16 and a second discrimination circuit 17.
This circuit selects one of them according to a select signal. This select signal is transmitted to the sector mark detection circuit 11.
The SM signal detected by the master clock of the device,
and a recording verify signal. The mask clock is a constant frequency clock that serves as a reference for the operation of the device, and is generated by a reference frequency oscillator (not shown). As will be described later, during recording verification, the select signal selects the second discrimination circuit 17 when a synchronization pattern is detected, and otherwise selects the first discrimination circuit 16.
In other words, when reproducing the synchronization pattern during recording verification, the pulse discrimination detection window is narrowed and the synchronization pattern abnormality is repaired at an early stage.

Next, a specific example of the second discrimination circuit 17 will be explained with reference to FIG. The second discrimination circuit 17 includes three FF circuits 22 to 24.
and a delay circuit 25. Delay circuit 2
Reference numeral 5 denotes a circuit that delays 174 cycles of the synchronous clock, and the delayed output is input to the R (reset) terminal of the FF circuit 22. D type circuits are used as the FF circuits 22 to 24. C of the first stage FF circuit 22
Binary data is input to the K (clock) terminal, and the FF
The output of the circuit 22 becomes high level when the binary data rises, and is inverted to low level when the delay circuit 25 falls. Further, the output of the FF circuit 22 is input to the CK terminal of the FF circuit 23, and the FF circuit 23 is reset by the inverted output of the FF circuit 24. Furthermore, the synchronous clock is input to the CK terminal of the FF circuit 24, and the output signal of the FF circuit 23 is input to the D terminal, and as a result, synchronous data is obtained from the FF circuit 24 at the final stage. Note that the D terminals of the FF circuits 22 and 23 are
°°1” signal is always input.

FIG. 3 shows signal waveforms at various parts of the second discrimination circuit 17. The specific operation will be described below with reference to the same figure.

Figure 3 (al is the reproduction signal of the synchronization pattern recorded on the recording medium, and the peak in A is the signal that was correctly reproduced. On the other hand, the peak in B is where the peak should originally be, as shown by the broken line) However, this is a signal that has become abnormal due to scratches or dirt on the recording medium, media defects, noise, etc. In this example, a part of the reproduced signal is missing,
The peak of the reproduced signal has a phase that is 3/8 ahead of the normal state.

Figure 3 [b] shows the 2-value signal obtained by binarizing the reproduced signal by the binarizing circuit 8.
It is value data. Binary data is designed to rise at the timing of the peak of the reproduced signal, and abnormal reproduced signal B
Since the phase of the peak is advanced by 8/3, the phase of the binary data is also advanced by the same amount. Figure 3 fc) is P
The synchronization clock generated by the LL9, FIG.
I'm behind on 4. Here, in FIG. 3 Fdl, the high level period of the output of the delay circuit 25 is shown as W.
This W is the pulse discrimination detection window (window period) of the second discrimination circuit 17. Since the FF circuit 22 is reset by the inverted signal of the output of the delay circuit 25, the delay circuit 2
Binary data is detected only within the detection window, which is the high level period of the output of 5. Therefore, binary data is determined only when there is a rising edge of binary data within the detection window. There is. In contrast, the period t of one cycle of the synchronization clock is the pulse discrimination detection window of the first discrimination circuit 16 and is twice as wide as the detection window W of the second discrimination circuit 17.

The rising edge of the binary data to the normal reproduction signal is the second
It is located within the pulse discrimination detection window W of the discrimination circuit 17.

Therefore, as shown in FIG. 3 te+, the output of the FF circuit 22 becomes high level at the rising edge of the binary data, and becomes low level at the falling edge of the delay circuit 25. In response to this pulse signal, the FF circuit 23 outputs a pulse signal that rises to a high level at the rising edge of the FF circuit 22 and becomes low level at the rising edge of the synchronous clock, as shown in FIG. 3+f). Upon receiving this signal, the FF circuit 24 operates as shown in FIG.
Output the synchronous data as shown in .

That is, if the reproduced signal is normal, the rising edge of the binary data is in the detection window W, so the second discrimination circuit 17 discriminates the pulse of the binary data and outputs synchronized data.

On the other hand, the rising edge of the binary data of the abnormal reproduction signal B is shown in FIG. 3(a). (As shown in bl, the second discrimination circuit 1
It is located at a position slightly away from the pulse discrimination detection window W of No. 7. In this case, the second discrimination circuit 17 does not discriminate 2 (direct data and does not output synchronous data).

Furthermore, since the pulse discrimination detection window of the first discrimination circuit 16 is twice as wide as that of the second discrimination circuit,
) are located within the detection window t. Therefore, the first discrimination circuit 16 discriminates both reproduced signals A and B, and outputs synchronized data for each.

Next, the first discrimination circuit 16. Generation of the select signal for selecting the second discrimination circuit 17 will be explained.

In FIG. 1, a sector mark detection circuit 11 detects a sector mark recorded on a recording medium and outputs it to an SM multiplied signal first counter 19. The sector mark is shown in Figure 4(a).
As shown in FIG. 4, the mark is recorded at the beginning of the preformat section of the recording medium, and the sector mark detection circuit 11 detects this and outputs the SM multiplied signal shown in FIG. 4 fc). A mask clock is also input to the first counter 19, and the first counter 19 counts a predetermined number of mask clocks using the SM multiplication signal as a starting point. That is, by counting a predetermined number of mask clocks, the starting point of the storage area of the synchronization pattern on the recording medium is detected. FIG. 4(d) shows the output of the first counter 19, and when a predetermined number of master clocks have been counted, the beginning of the synchronization pattern recording area of the recording medium is reached. When the first counter 19 finishes counting a predetermined number of master clocks, the second counter 20 starts counting a predetermined number of master clocks starting from when the first counter 19 finishes counting. do. This count corresponds to the time for reproducing the synchronization pattern, and while the second counter 20 is counting a predetermined number of mask clocks, the synchronization pattern is being reproduced.

In this way, the recording area of the synchronization pattern on the recording medium is detected, and the output signal of the second counter 20 is outputted to the AND circuit 21 as a synchronization pattern area detection signal. That is, the second
The period in which the output of the counter 20 is at a high level is when the synchronization pattern is being reproduced, and this signal and
The recording verify signal shown in b) is input to the AND circuit 21. The recording verify signal becomes high level during recording verifying performed immediately after the recording operation, and remains at low level at other times. Therefore, when the output of the second counter 20 and the recording verify signal are ANDed, the AND circuit 21
The output becomes high level only when a synchronization pattern is detected during recording verification.

This high level signal is output to the selector 18 as a select signal for selecting the second discrimination circuit 17. Also,
When the output of the AND circuit 21 is at a low level, the selector 18 selects the first discrimination circuit 16. This results in
Since the second discrimination circuit 17 is selected when a synchronization pattern is detected during recording verification, as shown in FIG. 4(f),
The synchronization data b of the second discrimination circuit 17 is outputted to the synchronization pattern detection circuit 12 and the decoding circuit 13 via the selector 18. Further, when reproducing other data, the first discrimination circuit 16 is selected, and the output synchronization data a is sent to the synchronization pattern detection circuit 12 and the decoding circuit 13. Note that since the output of the second counter 2o becomes high level when a synchronization pattern is detected, it is sent to the synchronization pattern detection circuit 12 as a synchronization pattern area detection signal. Thereby, the synchronization pattern detection circuit 12 detects the synchronization pattern only during the designated period, thereby preventing erroneous detection of the synchronization pattern.

In this way, when detecting a synchronization pattern during recording verification, the second discrimination circuit 17 having a narrow pulse discrimination detection window is selected, and the synchronization pattern is detected using a detection window narrower than the detection window during data reproduction. Thereby, it is possible to effectively detect an abnormal reproduction signal as shown in FIG. 3, and to treat abnormalities caused by small defects or scratches on the recording medium that are likely to cause errors in the future as recording errors. Therefore, it is possible to prevent a situation in which future playback becomes impossible due to a small defect or scratch in the synchronization pattern portion of the recording medium, and the reliability of recorded information can be further improved.

Next, other embodiments will be described. FIG. 5 is a schematic block diagram of a recording system device, and FIG. 6 is a schematic block diagram of a reproduction system device.

The recording system device includes an error correction code adding circuit 26 that adds an error correction code to record data, and a recording system 27 that records the record data to which the error correction code has been added by this circuit onto a recording medium.
It consists of There are various error correction codes such as Hamming codes, BCH codes, Reed-Solomon codes, and Fire codes.

Next, the reproduction system device includes a drive controller 28 that controls the selector 18, a reproduction system 29 shown in FIG. 1, and an error correction circuit 30 that corrects errors in data reproduced by the reproduction system 29. In this embodiment, the second discrimination circuit 17 is selected not only during recording verification but also during normal reproduction, and the synchronization pattern is discriminated using a narrow pulse detection window. At this time, if there are many playback errors (or if playback is not possible, the detection window is widened) and playback is performed again.
It is necessary to have functions such as (error detection code) or ECC (error detection and correction code). The error detection and correction circuit 3o is a circuit that detects errors in reproduced data and performs correction processing, and when there are many errors in the data and exceeds the error correction capability of the circuit, it outputs an error correction impossible signal to the drive controller 28. . During normal reproduction, when the synchronization pattern is reproduced with a narrow pulse discrimination window, when the drive controller 28 receives the above-mentioned error correction impossible signal, it instructs the selector 18 to widen the pulse detection window. When the number of synchronization patterns increases, the pulse discrimination window is widened and the synchronization pattern is reproduced again as described above.

In this embodiment, the synchronization pattern is detected under stricter conditions each time data is reproduced, so data may become unplayable due to deterioration of characteristics due to aging of the recording medium, new scratches or dirt on the synchronization pattern, etc. Situations can be prevented. Therefore, in this example as well, it is possible to further improve the storage reliability of recorded information.

[Effects of the Invention] As explained above, according to the present invention, when detecting a synchronization pattern, the pulse discrimination detection window is made narrower than when reproducing other data, so the synchronization pattern can be discriminated under stricter conditions. The cause of the synchronization pattern abnormality can be repaired at an early stage. Therefore, it is possible to prevent the situation in which the synchronization pattern cannot be reproduced in the future due to unstable factors such as small defects or scratches in the synchronization pattern part of the recording medium, and the data cannot be reproduced. This has the effect of further improving storage stability.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the information recording and reproducing apparatus of the present invention, FIG. 2 is a circuit diagram showing a specific example of the second discrimination circuit, and FIGS. 3(a) to fg) are the second discrimination circuit. FIG. 4 is a time chart showing the operation of generating the select signal, FIG. 5 is a schematic block diagram of the recording system, FIG. 6 is a schematic block diagram of the reproduction system, and FIG. FIG. 8 is a block diagram showing the configuration of a recording system of a general information recording/reproducing device, FIG. 8 is a block diagram similarly showing the configuration of a reproduction system, FIG. FIG. 10 is a circuit diagram of a discrimination circuit used in the reproduction system shown in FIG. 8, and FIG. 11 is a time chart showing the operation of the discrimination circuit. 5...Recording medium 8...2 Value conversion circuit 9-・
・PLL 11... Sex mark detection circuit 12... Synchronization pattern detection circuit 13... Decoding circuit 16... First discrimination circuit 1
7... Second discrimination circuit 18... Selector 19...
・First counter 20...Second counter 21...
AND circuit 22.24...FF circuit 25...Delay circuit.

Claims (2)

[Claims] (1) In an information recording and reproducing apparatus that binarizes data read from a recording medium and discriminates the signal using a pulse discrimination detection window of a predetermined period, a synchronization pattern indicating a read start position of data recorded on the recording medium. An information recording and reproducing apparatus characterized in that the information recording and reproducing apparatus comprises means for making the pulse discrimination detection window narrower when detecting the pulse than when reproducing other data. (2) The information recording/reproducing apparatus according to claim 1, wherein the means for narrowing the pulse detection window narrows the pulse discrimination detection window during a recording verify check immediately after a recording operation than during other data reproduction.