JPH03192890A - Signal string conversion circuit - Google Patents

Abstract

PURPOSE:To eliminate a memory for generating an address by generating a read address of an equal speed call memory while being split into a high-order read counter and a low-order read counter. CONSTITUTION:A signal series conversion circuit consists of an equi-speed readout memory (RAM) 1 to write a signal string, a write counter 2 generating a write address at that time, a high-order read counter 3 and a low-order read counter 4 generating a read address to read a written signal string. The high- order read counter 3 inputs a read clock pulse and a read frame pulse and outputs counts 0-3 for each 4-bit to the equi-speed call memory 1 as a high-order read address and outputs one clock pulse to the low-orer read counter 4. Thus, the low-order read counter 4 advances the count for each 4-bit and outputs the result to the equi-speed call memory 1 as a high-order read address.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a signal string conversion circuit using a constant speed access memory (RAM) in digital data signal processing, among signal string conversion circuits in data transmission equipment. .

[Conventional technology]

Conventionally, this type of signal string conversion circuit uses an address generation memory separate from the RAM to generate a read address for reading a signal string written in the RAM, as shown in FIG. A read counter sequentially reads out an address string written in advance in the memory, and the signal string is converted by using this read address as the read address of the RAM.

FIG. 3 is a block diagram showing an example of the conventional system, and FIG. 4 is a frame format showing an example of the main person output data in FIG. According to FIG. 3, the circuit has a constant speed access memory (RAM) 31, a write counter 32, a read counter 33, and an address generation memory 34.

The signal conversion function of this circuit will be explained with reference to FIGS. 3 and 4.

The write counter 32 inputs the write clock pulse and the write frame pulse, sends the write address 0°1.2... to the constant speed recall memory 31, and writes a series of write data a,
Write b, c, etc. sequentially.

The read counter 33 inputs the read lock pulse and the read frame pulse and outputs a read count value of 0° 1.2 . . . for each frame. The address generation memory 34 stores the chronological order in which a series of data stored in the constant speed access memory 31 is read. According to FIG. 4, the address generation memory 34 receives count values 0, 1, 2.3, .
When the output of ... is received, read address 0, 4, 8.1
2... is output. Therefore, the constant speed recall memory 31 has read addresses 0, 4, 8, 12, . . . outputs read data a, e, i, m, . . .

[Problem to be solved by the invention]

The conventional signal string conversion circuit described above has an address generation memory for generating read addresses in addition to the memory for signal string conversion, so the scale of the circuit is relatively large. There was a problem in that the read address string had to be written in advance.

An object of the present invention is to provide a signal string conversion circuit that solves the above problems.

[Means to solve the problem]

The signal string conversion circuit according to the present invention sequentially writes a series of data signal strings into a constant speed access memory (RAM), and then reads the written contents by changing the time series. A write counter that receives and generates and outputs a write clock pulse and a write frame pulse, and a write counter that receives a read clock pulse and a read frame pulse and generates and outputs an upper read address, and clocks each predetermined count value. It has an upper read counter that outputs a pulse, and a lower read counter that receives the output clock pulse and read frame pulse of the upper read counter and generates and outputs a lower read address.

[For production]

The signal string conversion circuit according to the above-mentioned means can realize time-series conversion of the signal string according to the rule in the above example by setting a predetermined count value in the upper reading counter.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. According to FIG. 1, the signal string conversion circuit includes a constant speed reading ratio memory (RAM) 1 for writing the signal string, a write counter 2 for generating the write address at that time, and a write counter 2 for reading the written signal string. It is composed of an upper read counter 3 that generates a read address and a read counter 4 described below.

FIG. 2 is a format showing an example of the data and addresses of the main part of FIG. 1.

This embodiment will be described with reference to FIG. 1 and FIG. 2.

The write counter 2 receives write clock pulses and write frame pulses, and writes write data a.

Write addresses 00, 01, 02, . . . for writing b, c, . . . to the constant speed access memory 1 are output. Write address 0
0,01. . . . converts the centrally arranged input data signal from count values 0, 1.2, . . . to distributed arrangement in units of 4 bits.

The upper read counter 3 inputs the read lock pulse and the read frame pulse, and outputs the count value O to 3 for each bit every 4 bits as an upper read address to the constant speed recall memory 1, and also outputs the count value 0 to 3 to the lower read counter 4 by 1 every 4 bits. Outputs clock pulse. Therefore, the lower read counter 4 advances the count value every 4 bits and outputs it to the constant speed access memory 1 as the upper read address. That is, read address 0
0.10.20... are sequentially input to the constant speed recall memory 1, so the read data a, e; i... are read in order and output.

〔Effect of the invention〕

As explained above, the signal string conversion circuit of the present invention generates the read address of the constant speed access memory by dividing it into the upper read counter and the lower read counter, so that the memory for address generation can be deleted. This has the effect of saving the effort of creating the circuit in advance and reducing the circuit scale at the same time.

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[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the signal string conversion circuit of the present invention, FIG. 2 is a format showing an example of data and addresses in the circuit of FIG. 1, and FIG. 3 is a block diagram showing an example of the conventional circuit. The configuration diagram, FIG. 4, is a format showing an example of a conventional circuit. 1... Constant speed recall memory, 2... Write counter, 3
... Upper reading counter, 4... Lower reading counter. soil'? prisoner

Claims (1)

[Claims] In a signal string conversion circuit that sequentially writes a series of data signal strings into a constant-speed access memory (RAM) and then reads the written contents by changing the time series, an address for sequentially writing the signal string is set using a write clock pulse and a write clock pulse. a write counter that receives and generates and outputs frame pulses; an upper read counter that receives read clock pulses and read frame pulses, generates and outputs upper read addresses, and outputs clock pulses every predetermined count value; A signal string conversion circuit comprising a lower read counter that receives the output clock pulse and read frame pulse of the upper read counter and generates and outputs a lower read address.