JPH03196565A - input/output protection device - Google Patents

Abstract

PURPOSE:To obtain high strength against a latchup and an electrostatic breakdown by providing a plurality of other electrodes of a protective diode at positions having different resistance values from one electrode of the diode, and adding a current path. CONSTITUTION:N-wells 42-44 are formed on a P-type semiconductor substrate 41, and a P<+> type diffused high concentration impurity region 46 connected to a pad 45 to become one electrode of a protective diode D5 is formed in a protective diode exclusive use N-well 42. N<+>-sub high concentration impurity regions 47, 48 to become other electrodes of the diode D5 and having different parasitic resistances from P<+> type region 46 are formed in the well 42, and connected to a power source VDD. Further, a P<+> type diffused high concentration impurity region 49 to be supplied with a potential different from the well potential such as a ground VSS is formed between the regions 47 and 48. Thus, a high strength against a latchup and an electrostatic breakdown is obtained.

Description

[Detailed Description of the Invention] [Purpose of the Invention (Field of Industrial Application) The present invention relates to an input/output protection device used in semiconductor integrated circuits, and in particular to a device used in complementary field effect integrated circuits. be.

(Prior art) Conventionally, complementary field-effect integrated circuits (hereinafter referred to as rcMO3I)
It is abbreviated as CJ. ) The input/output protection devices used in
A diode type as shown in Figures 3 and 4,
MOS type devices as shown in FIGS. 5 and 6 are known.

3 and 4 show a diode type input/output protection device. The operation of the diode type input/output protection device will be described below with reference to the same figure.

When a high potential surge is input from pad lla, a forward voltage is applied to diode D on the P channel side, and N5. . ,1
A forward current IIs flows toward the terminal 2.

This current 13. is the emitter-base current of the parasitic bipolar PNP transistor Tri. Along with this, the transistor Trl is turned on, and the transistor Trl is turned on toward the substrate 13, which is the collector side (parasitic resistance R of the P-type substrate 13).
A current I2 flows toward P"-, b14 through the P type substrate I3. On the N channel side, a reverse voltage is applied to the diode D2, and a current I2 flows toward the substrate II3 (parasitic resistance R1 of the P type substrate I3). (toward P''-, , , 15) through reverse current I9. flows.

This allows high potential surges to escape.

Further, when a low potential surge is input from the pad lla, a reverse voltage is applied to the diode D1 on the P channel side, and a reverse current 11b flows from the N well 16 toward the P+ diffusion 17. Furthermore, on the N-channel side, a forward voltage is applied to the diode D2, and the N-channel voltage is applied through the resistor R5.
A forward current I 3b flows toward the diffusion 18. This current 13b becomes the base-emitter current of the parasitic bipolar NPN transistor Tr2. Along with this, the transistor Tr2 is turned on, and the transistor Tr2 is turned on, and the transistor Tr2 is turned on from the N well 19 on its collector side toward the substrate I3 (N well 19
A current (4) flows toward the N+ diffusion 18 via the parasitic resistance R4 of the P-type substrate 13 and the parasitic resistance R7 of the P-type substrate 13. This allows low potential surges to escape.

5 and 6 show a MOS type input/output protection device. The operation of the MOS type input/output protection device will be described below with reference to the same figure.

When a high-potential surge is input from the pad 21a, a forward voltage is applied to the parasitic diode D on the P channel side, and the voltage is applied to the parasitic diode D through the parasitic resistance R1 of the N well 24.
, forward current towards 25! 6. flows. This current 1
6m is a parasitic bipolar PNP transistor Tr3.
This becomes the emitter-base current of Tr4. Accordingly, the transistors Tr3°Tr, 4 are turned on, and the transistors Tr3 and Tr4 are connected to the P1 diffusion 23 on the power supply VDD side, which is the collector side of the transistor Tr3, and to the substrate 26 (the parasitic resistance R6 of the P-type substrate 26, which is the collector side of the transistor Tr4). via P”
-, , b27), respectively, with a current of 17. I, flows. Furthermore, on the N channel side, a reverse voltage is applied to the parasitic diode D4, and a reverse current 1.a flows from the N+ diffusion 30 to P''-, b2g via the parasitic resistance R7 of the P type substrate 2B. Accordingly, MO3I-transistor M
The potential of the substrate 26 in the vicinity of 2 becomes high, and a forward current 110 flows from the substrate 26 to the N' diffusion 29 on the ground VSS side.

This current I,. are the base-emitter (collector in the figure) current of the parasitic bipolar NPN transistor Tr5. Accordingly, the transistor Tr5 is turned on, and the N+ diffusion 30 on the pad 21a side, which is the collector (emitter in the figure) side of the transistor Tr5, is connected to the ground v5. A current III flows through the N+ diffusion 29 connected to the N+ diffusion 29. This allows high potential surges to escape.

Furthermore, when a low potential surge is input from the pad 21a, a reverse voltage is applied to the parasitic diode D on the P channel side, and the parasitic resistance from the N well 24 to (N"-, , , 25 to the N well 24) A reverse current 1 (, flows through R6) to the P diffusion 22 on the pad 21a side.As a result, the potential of the MO3I-transistor M and the nearby N well 24 becomes low, and the P diffusion 23 on the power supply Vpp side A forward current 112 flows from the N well 24 to the N well 24. This current 112 becomes the emitter (collector in the figure)/base current of the parasitic bipolar PNP transistor Tr3.Accompanyingly, the transistor Tr3 turns on, and the power supply VDD A current of 1.3 flows from the P+ diffusion 23 connected to the transistor Tr3 to the P+ diffusion 22 on the pad 21a side, which is the collector (emitter in the figure) side of the transistor Tr3.
A forward voltage is applied to the parasitic diode D4, and the substrate 26
A forward current of 19% flows from the resistor R7 to the N+ diffusion 30. This current 19b becomes the base-emitter current of the parasitic bipolar NPN transistors Tr5 and Tr6. Along with this, transistor Tr5. Tr
5 is turned on, from the N+ diffusion 29 on the ground VSS side, which is the collector side of the transistor Tr5, to the N+ diffusion 30 on the pad 21a side, and from the N well 31, which is the collector side of the transistor Tr6, to (N'-, , , 32 Parasitic resistance R1o of P type substrate 26 and parasitic resistance R of N well 31 from
8) to the N+ diffusion 30 on the pad 21 side, respectively. .

! +6 flows. This allows low potential surges to escape.

However, in the diode-type input protection device shown in FIGS. 3 and 4, when a surge is applied from the pad lla, the operation of the parasitic transistors Trl and Tr2 causes a current I2. I4 is played. Therefore, inside the integrated circuit, this current causes the potentials of the substrate, well, etc. to float, causing latch-up.

Further, in the MOS type input/output protection device shown in FIGS. 5 and 6, the potential is released by parasitic transistors T r 3 and T r 5 in addition to the parasitic diodes D9 and D4. Therefore, the current Ig, 116 flowing into the integrated circuit due to the operation of the parasitic transistors Tr4 and Tr6 is smaller than that in a diode-type input/output protection device, and the possibility of latch-up occurring is reduced. However, the distances from the parasitic diode D, to N"-, , 25 and from the parasitic diode D4 to P", , 2g become longer, and the resistors R5 and R7 become longer than the resistors R and R of the diode-type input protection device. The resistance value is higher than that of Ri (see FIGS. 3 and 4). This results in resistors R5 and R
7 generates heat, and under the influence of this heat, the diode D,
, D4's PN junction may be thermally destroyed. Also, if a surge is input from the pad 21a, the MO
S transistor M, , gate of M2 and P+ diffusion 23,
There is a drawback that a large potential difference occurs between the N+ diffusion 30 and the thin gate oxide film at the gate portion due to this large potential difference.

(Problem to be solved by the invention) As described above, conventional diode type input/output protection devices
The disadvantage is that current flows into the integrated circuit due to the operation of parasitic transistors, causing latch-up.

In addition, in a MOS type input/output protection device, the diode's PN
There were drawbacks such as thermal breakdown of the junction and electrostatic breakdown of the thin gate oxide film due to the large potential difference.

Therefore, an object of the present invention is to provide a reliable input/output protection device that has high strength against latch-up and electrostatic discharge damage.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, an input/output protection device of the present invention is formed in a first conductivity type semiconductor region and the first conductivity type semiconductor region, a second conductivity type high concentration impurity region that serves as one electrode of the protection diode; and a second conductivity type semiconductor region that is formed in the first conductivity type semiconductor region and serves as the other electrode of the protection diode, and
a plurality of first conductivity type high concentration impurity regions each having a different parasitic resistance from the second conductivity type high concentration impurity region; a pad connected to the second conductivity type high concentration impurity region; and a plurality of first conductivity type high concentration impurity regions; and a potential supply source connected to the conductivity type high concentration impurity region.

Further, a first conductivity type semiconductor region and a first conductivity type semiconductor region formed in the first conductivity type semiconductor region and serving as one electrode of a protection diode are provided.
The second conductivity type high concentration impurity region is formed in the first conductivity type semiconductor region, serves as the other electrode of the protection diode, and has a different parasitic resistance from the second conductivity type high concentration impurity region. first and second first conductivity type high concentration impurity regions; a second second conductivity type high concentration impurity region formed between the first and second first conductivity type high concentration impurity regions; a pad connected to the first second conductivity type high concentration impurity region; a first potential supply source connected to the first and second first conductivity type high concentration impurity regions; and a second potential supply source connected to the second conductivity type high concentration impurity region.

(Function) According to such a configuration, the second conductivity type high concentration impurity region serving as one electrode of the protection diode and the second conductivity type high concentration impurity region serving as the other electrode of the protection diode and the second conductivity type high concentration impurity region serving as the other electrode of the protection diode. A plurality of first conductivity type high concentration impurity regions each having a different parasitic resistance from the region are provided.

Further, the first second conductivity type high concentration impurity region serving as one electrode of the protection diode and the first second conductivity type high concentration impurity region serving as the other electrode of the protection diode have different parasitic resistances. First and second first conductivity type high concentration impurity regions are provided. In addition, the first and second
A second high concentration impurity region of the second conductivity type is formed between the high concentration impurity regions of the first conductivity type.

As a result, the number of current paths in the input/output protection circuit can be increased, and the current flowing into the integrated circuit and the current flowing out from the integrated circuit can be reduced. Therefore, it is possible to obtain an input/output protection device that has high strength against latch-up and also has high strength against electrostatic discharge damage because it does not have an MO3 structure.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings. In this description, common reference numerals are used for common parts throughout all the figures to avoid redundant explanation.

FIG. 1 shows an input/output protection device according to a first embodiment of the present invention.

P-type semiconductor substrate (semiconductor region) 41 has an N well 42
~44 are formed. In the N well (semiconductor region) 42 dedicated to the protection diode, a P+ diffusion (high concentration impurity region) 46 is formed which becomes one electrode of the protection diode D and is connected to the pad 45. Furthermore, within the N well 42, there is a N+-1° (high concentration impurity region) 47. which has a different parasitic resistance from the P+ diffusion 46 and serves as the other electrode of the protection diode D. , Hl are formed, respectively. N"-,, b47.4B is connected to the power supply vDD.Furthermore, between N"---h47 and 48,
A P" diffusion (high concentration impurity region) 49 is formed to which a potential different from the well potential, for example, the ground VSS potential is supplied. Note that the P1 diffusion 46, N"-, , , 47 and P
A lateral PNP transistor Tr7 is formed by the first diffusion 49. Further, in the board 41, for example, a ground v
P''-, , b50 to which the s5 potential is supplied is formed.

Further, in the P-type substrate 41, an N+ diffusion (high concentration impurity region) 51 is formed which becomes one electrode of the protection diode D6 and is connected to the pad 45. Further, in the substrate 41, P''-hubs (high concentration impurity regions) 52 and 53 are formed, which have different parasitic resistances from the N'''' diffusion 51 and serve as the other electrode of the protection diode D6. P”-, , 52, 53 are, for example, grounded V55
It is connected to the. Furthermore, P+-6°, 52 and 53
A potential different from the substrate potential, for example, a power supply VDD potential, is supplied to the N well 44 between N''-sum (
A high concentration impurity region) 54 is formed. In addition, N+
Diffusion 51. P"-,, b52 and N"-ai+b54
A lateral NPN transistor Tr8 is formed. Also, in the N well 43, a power supply V DD7!
! The supply position is N+-1. ．． b55 formation is complete.

Next, the operation of the input/output protection device according to the first embodiment will be explained in detail with reference to the same figure.

If a high potential surge enters from Bad 45,
On the P-channel side, a forward voltage is applied to diode D. Therefore, a forward current i, a, i2. flows respectively. Current i3.
becomes the emitter-base current of transistor Tr7, transistor Tr7 is turned on, and current i3 flows toward P+ diffusion 49 on its collector side.

Also, the current 12. is the emitter-base current of the parasitic PNP transistor Tr9, so the transistor Tr9
is turned on, and the current flows toward the substrate 41, which is its collector side (toward P''-, , , 50 via the parasitic resistance r of the N-well 42 and the parasitic resistance r4 of the P-type substrate 41).
Current i4 flows. Further, on the N-channel side, a reverse voltage is applied to the diode D6. For this reason, from the N+ diffusion 51 which is the electrode on the cathode side, P
” -, , , 52, 53 respectively. Reverse currents i11 and i6. flow to them. This allows high potential surges to escape.

If a low potential surge is input from the pad 45, P
On the channel side, a reverse voltage is applied to diode D5. For this reason, the cathode side electrode N” −
--Reverse current i31.1 from b47.48 to P+ diffusion 46, which is the anode side electrode, via resistor rl+r2
2. flows respectively. Further, on the N-channel side, a forward voltage is applied to the diode D6. For this reason, forward currents igb and ibb flow from the anode side electrodes P''- and b52.53 to the cathode side electrodes N+ diffusion 51 via the resistance r%+r6, respectively.

The current 15b becomes the base-emitter current of the transistor Tr8, so the transistor Tr8 is turned on, and the current 15b becomes the base-emitter current of the transistor Tr8.
A current 17 flows toward the N+ diffusion 51 on the 5 side. Also,
Since the current ibb becomes the base-emitter current of the parasitic NPN transistor TrlO, the transistor TrlO is turned on, and the parasitic resistance r of the N-well 43 is
A current 18 flows toward the N+ diffusion 51 on the side of the pad 45 (via the parasitic 7 and the parasitic 8 of the P-type substrate 41).This allows low potential surges to escape.

According to such a configuration, on the P channel side, the parasitic transistors Tr7. N”, which becomes the base electrode of Tr9, −
, , 47, and 48 are provided at positions having different resistance values from the P+ diffusion 4B. For this reason, the substrate and N
The conventional current path (I
r-1I +- (see Figure 4)), a new current path has been added (1 jar ilb + 12m + 12b)
has been done. Furthermore, if the resistance value of the resistor r1 is set to be lower than the resistance value of the resistor r2, the currents i+m and i+b flowing through the resistor r1 increase, while the current 12a+121k flowing through the resistor "2" decreases.

Additionally, a P+ diffusion 49 is additionally formed between N"-1147 and 48, thereby causing the lateral PNP transistor Tr.
7 is formed. Therefore, an additional current path for the current i is added, and the currents i2a and j2b flowing at the interface between the substrate 41 and the N-well 42 can be significantly reduced.

By the way, the current flowing into or out of the integrated circuit is
Current! 2@+12, and therefore it is possible to provide an input/output protection device that is resistant to latch-up compared to conventional devices.

Furthermore, since the input/output protection device of the present invention does not include a MO3 structure transistor, there is no possibility of gate oxide film breakdown.

Furthermore, the parasitic resistance "1" of the N-well 42 is almost the same as the parasitic resistance R3 of the N-well 16 of the diode type input/output protection device (see FIG. 4 above). Flowing current 12.

12. MO3 type input/output protection device (see Figure 6 above)
The current ib*rl flowing through the parasitic resistance R1 of the N well 24 of
It is less than bb. Accordingly, the amount of heat generated by the resistors r1 and r2 decreases, and the diode P
It is possible to prevent thermal damage to the N junction. Furthermore, a reduction in the current i2a+f2b means that the current flowing into the integrated circuit due to the parasitic transistor Tr9 is also reduced, providing a reliable input/output protection device with high resistance to latch-up and electrostatic discharge damage. can.

FIG. 2 shows an input/output protection device according to a second embodiment of the present invention.

An N well (semiconductor region) 42 dedicated to a protection diode is formed in a P-type semiconductor substrate (semiconductor region) 41 . A P+ diffusion (high concentration impurity region) 4B is formed in the N well 42 and serves as one electrode of the protection diode D and is connected to the pad 45. Further, in the N well 42, N'''-1, (high concentration impurity region) 47.48, which has different parasitic resistance from the P+ diffusion 46 and becomes the other electrode of the protection diode D, is formed. .N
"-, , , 47, 48 are connected to the power supply VDD. Further, in the substrate 41, P+-6°, 50 is formed to which, for example, the ground VSg potential is supplied.

In such a configuration, N"-, , 47, 48, which becomes the other electrode of the protection diode D, is located at a position where the resistance value from the P+ diffusion 46, which becomes one electrode of the protection diode D, is different.
is provided. Therefore, an additional current path is required compared to the conventional method.

Furthermore, by setting the resistance value of the resistor r1 lower than the resistance value of the resistor r2, the current i3. increases, while the current 12 flowing through the resistor r2 decreases. Therefore, an input protection device that is resistant to latch-up can be provided. Furthermore, since there is no MO5 structure transistor, there is no possibility of gate oxide film breakdown.

[Effects of the Invention] As described above, the input/output protection device of the present invention provides the following effects.

A plurality of other electrodes of the protection diode are provided at positions having different resistance values from one electrode of the protection diode,
A current path is added. Furthermore, a base electrode is provided between these other electrodes to form a lateral transistor, and a current path is further added. Therefore, the current flowing into the integrated circuit and the current flowing out from the integrated circuit can be reduced. Therefore, it is possible to provide a reliable input/output protection device that has high strength against latch-up and electrostatic damage.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing an input/output protection device according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view showing an input/output protection device according to a second embodiment of the present invention, and FIG. A circuit diagram showing a conventional diode type input/output protection device, Fig. 4 is a sectional view showing a conventional diode type input/output protection device, Fig. 5 is a circuit diagram showing a conventional MO3 type input/output protection device, Fig. 6 1 is a sectional view showing a conventional MO3 type input/output protection device. 41...P type semiconductor substrate, 42-44...N well, 45...pad, 48.49...P+ diffusion, 47
．． 4g, 54.55...N” -,,,50,5
2,53...P''-amb, 51...N+diffusion,
D,, D6...Protection diode, Tr7 to Tr10.
... Parasitic transistor, r, ~r8... Parasitic resistance.

Claims (3)

[Claims] (1) A first conductivity type semiconductor region and a second conductivity type semiconductor region formed in the first conductivity type semiconductor region and serving as one electrode of a protection diode.
a conductivity type high concentration impurity region; and a plurality of first conductivity regions formed in the first conductivity type semiconductor region, serving as the other electrode of the protection diode, and each having a different parasitic resistance from the second conductivity type high concentration impurity region. type high concentration impurity region,
An input/output protection device comprising: a pad connected to the second conductivity type high concentration impurity region; and a potential supply source connected to the plurality of first conductivity type high concentration impurity regions. (2) a first conductivity type semiconductor region and a first conductivity type semiconductor region formed in the first conductivity type semiconductor region and serving as one electrode of a protection diode;
The second conductivity type high concentration impurity region is formed in the first conductivity type semiconductor region, serves as the other electrode of the protection diode, and has a different parasitic resistance from the second conductivity type high concentration impurity region. first and second first conductivity type high concentration impurity regions; a second second conductivity type high concentration impurity region formed between the first and second first conductivity type high concentration impurity regions; a pad connected to the first second conductivity type high concentration impurity region; a first potential supply source connected to the first and second first conductivity type high concentration impurity regions; An input/output protection device comprising: a second potential supply source connected to a two-conductivity type high concentration impurity region. (3) a first conductivity type semiconductor substrate, a second conductivity type well region formed in the first conductivity type semiconductor substrate, and one electrode of a first protection diode formed in the first conductivity type semiconductor substrate; a first second conductivity type high concentration impurity region formed in the first conductivity type semiconductor substrate, serving as the other electrode of the first protection diode, and the first second conductivity type high concentration impurity region first and second first conductivity type high concentration impurity regions having different parasitic resistances;
a second high concentration impurity region of the second conductivity type formed between the high concentration impurity regions of the first conductivity type; and a third high concentration impurity region formed in the well region of the second conductivity type and serving as one electrode of the second protection diode. is formed in the first conductivity type high concentration impurity region and the second conductivity type well region, serves as the other electrode of the second protection diode, and is free from parasitic interference from the first conductivity type high concentration impurity region. third and fourth second conductivity type high concentration impurity regions having different resistances; and a fourth first conductivity type high concentration impurity region formed between the third and fourth second conductivity type high concentration impurity regions. a pad connected to the first second conductivity type high concentration impurity region and the third first conductivity type high concentration impurity region; and the first, second and fourth first conductivity type high concentration impurity regions. It is characterized by comprising a first potential supply source connected to the impurity region, and a second potential supply source connected to the second, third and fourth second conductivity type high concentration impurity regions. I/O protection device.