JPH03200074A - Detection circuit for narrow pulse width - Google Patents

Abstract

PURPOSE:To prevent a malfunction caused by the pulse having reverse polarity of extremely narrow width and to accurately decide a comparison time by using a delay line which is hardly affected by environments. CONSTITUTION:By a variable delay element 20 capable of setting a delay time (comparison time) from outside data, the input signal is delayed for a specified time and outputted. The signal becoming LOW level at the rise edge of input signal and HIGH level at the fall is generated by an edge detecting part 21, and when the input signal falls down from the rise within the comparison time, the HIGH level state is kept during the input signal rises after the finish of comparison time. The state of edge detecting signal at the time after the comparison time is elapsed from the rise edge of input signal is latched by a narrow pulse detecting part 22. Since the edge detecting signal is in the HIGH state when the pulse having the width narrower than the comparison time exists, the output OUT is also in the HIGH state.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a circuit for detecting a pulse narrower than an arbitrary set time (referred to as a narrow pulse), a so-called narrow pulse width detection circuit.

<Prior Art> A narrow pulse width detection circuit using a delay element is described in detail in Japanese Patent Application No. 1983-54275 ``Narrow Pulse Width Detection Circuit'' by the applicant of the present invention.

A brief explanation of this narrow pulse width detection circuit is as follows. FIG. 5 is a configuration diagram thereof, and FIG. 6 is a time chart for explaining the operation. Delay time setting data DATA is given to the variable delay element 10 to delay the input signal IN by a necessary time (this time is referred to as comparison time). The comparison time generating section 11 generates a signal FT that is at a HIGH level from the rise of the input signal IN to the rise of the delayed input signal. The narrow pulse detection section 12 latches the signal FT at the rising edge of the input signal that has passed through the delay element for after-sound delay compensation.

With this configuration, when the input signal rises during the comparison time T (j) from the rise of the input signal IN, the output (
Output of latch 121 of chivalry pulse detector 12) OUT is H
Becomes IGH level. That is, when a pulse whose width is narrower than the comparison time is input, the output signal OUT becomes HIGH at the timing of its rise.

<Problem to be solved by the invention> However, as explained below, such conventional circuits may malfunction when extremely narrow pulses of opposite polarity (negative polarity) are input. .

FIG. 7 is a time chart showing the situation in that case.

In this circuit, the residual delay of the signals FT and EG is compensated for by the variable delay element 112, or if this compensation is not performed extremely accurately, a malfunction as shown by the dotted line in the figure will occur. This compensation is extremely difficult, as it is necessary to take into account variations in delay of each element due to temperature changes.

The object of the present invention has been made in view of the above points, and is capable of detecting narrow pulses with high precision by using a delay element without causing the malfunctions described in the conventional example. An object of the present invention is to provide a narrow pulse width detection circuit.

Means for Solving the Problem> In order to achieve such an object, the present invention delays the input signal (IN) by a predetermined time ('I'd) set by external data and outputs the delayed signal. The delay element (20) generates a signal that becomes LOW level at the rising edge of the input signal (IN) and becomes HIGH level at the falling edge, and the input signal (IN) is connected to the delay element (20). ), the output signal is held at the HTGH level until the input signal (IN) rises again after the input signal is sent out from the delay element (20). an edge detection section (21) configured as follows; and a narrow pulse detection section that latches the state of the output signal of the edge detection section (21) at the rising edge of the input signal (IN) via the variable delay element (20). (22) It is characterized by having the following.

<Function> The edge detection section (21) generates a signal that becomes LOW level at the rising edge of the input signal (IN) and becomes HIGH level at the falling edge, or
If the input signal falls while the input signal (N) is delayed by the delay element (20), the output signal remains until the input signal (IN) rises again after the input signal is sent from the delay element (20). is maintained at a HIGH level state to prevent an input signal having an extremely narrow pulse width of opposite polarity from affecting the output.

<Example> The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing the principle configuration of a narrow pulse width detection circuit according to the present invention. In the figure, numeral 20 is a variable delay element whose delay time (comparison time) can be set using external data, and outputs the input signal after delaying it by a predetermined set time.

Reference numeral 21 denotes an edge detection unit, which generates a signal that goes to LOW level at the rising edge of the input signal and goes to HIGH level at the falling edge. When falling, the HIGHfl: state is maintained until the input signal rises after the end of the comparison time.

A narrow pulse detection section 22 receives the output of the edge detection section 21 and the output of the variable delay element 20, and latches the state of the edge detection signal after a comparison time has elapsed from the rising edge of the input signal. Note that if there is a rising edge during the comparison time, that is, if there is a pulse whose width is narrower than the comparison time, the edge detection signal becomes HI.
Since it is GH, the output OUT is also HIGH.

In the edge detection section 21 whose detailed configuration is shown in FIG.
- The non-inverted output of the input hack 723 is input to the tarlock input terminal of the -FF 211, and the inverted output of the input filter 23 is input to the clock input terminal of the second D-FF 212.
There is a delay element 2 at the tarock input terminal of the third D-FF 213.
The non-inverted output of the input buffer 23 via 0 is input.

In addition, a second D-FF is connected to the D input terminal of the first D-FF 211.
The inverted output Q of FF212 is input, and the second D-FF2
12, the non-inverted output Q of the first D-FF 211 is input.

Furthermore, the first D-FF is connected to the D input terminal of the third D-FF 213.
The non-inverted output Q of the FF 211 is input.

Note that the three D-FFs are commonly reset by a clear signal.

214 is the Exclusive Noah Gate, the first
The exclusive OR of the outputs of the second D-FF and the second D-FF is obtained, and logic No. 12 ED, which is the inverted result, is output.

A D-FF is used as the narrow pulse detection section 22, and the output of the delay element 20 is input to its tarock input terminal, and an exclusive NOR gate 214 is input to its D input terminal.
The output of is input.

The operation in such a configuration will be explained next with reference to the time chart of FIG. In the initial state, each D-FF21
1, 212, and 213 have been reset. The variable delay element 2o generates a delayed signal DL by delaying the input signal IN by the comparison time Td.

The operation of the edge detection section 21 is as follows. Input signal I
The state of the output Q of the DFF 211 is reversed at the rising edge of the input signal IN (at times ①, ②, and ② shown in FIG. 3). Note that when the next rising edge occurs between the rising edge and Td, the output Q
The state of is not reversed (■).

D-FF213 has such Q of I)-FF211.
The output signal is launched at the falling edge of the input signal IN. Then, in the exclusive Noah game 1-21, 4, the exclusive OR of the outputs of the I)-FFs 211 and 213 is taken, and it is inverted and output. As a result, an edge detection signal ED as shown in (f> in FIG. 3) can be obtained.

This ED signal becomes LOW at the rising edge of the input signal IN as shown at time points ■, ■, and ■ in FIG.
As shown in the figure, it becomes HIG to I at the falling edge. Tatashi,
If there is a fall between the rise and Td, the HIGH level is maintained until the rise of the input signal IN after the comparison time Td has elapsed (time point ■ in FIG. 3). That is, even if the input signal IN rises again during Td, the edge detection signal ED does not become LOW.

The edge detection signal ED becomes HI at the rise of the delay signal DL.
If it is GH, this means that IN has risen during the comparison time Td from the rise of input signal IN.

In other words, a pulse with a width narrower than the comparison time Td has arrived.

Therefore, the signal OUT that launches the edge detection signal ED at the rising edge of the delay signal DL is as follows. Since there is no falling edge between the rising edge of the input signal IN at time point ■ in FIG. 3 and Td, the delayed signal DL at time point ■
At the rising edge of , the edge detection signal ED is at LOW level. That is, at the time point (3), the output OUT remains at the LOW level. However, if the input signal IN falls during the elapse of time Td from the rise of the input signal IN at time point ■ (time point ■), the edge detection signal ED becomes HIGH level, and the subsequent delay time DL
At the rising edge ■, the edge detection signal ED is HIG.
Since the H level is maintained, the output at point ■ is OUT.
becomes HIGH level. This allows narrow pulses to be detected.

FIG. 4 shows a time chart when an extremely narrow pulse of opposite polarity is input. The output Q of the D-FF213 is not inverted at the time of inputting the narrow pulse of the input signal IN;
Therefore, the LOW level continues. Then, at the subsequent rise of the delay signal DL, the edge detection signal ED
is at a LOW level, so even if there is a narrow pulse in the input signal IN, the output OUT remains at a LOW level.

In this way, it is possible to realize a pulse detection circuit that does not malfunction when a narrow pulse of opposite polarity is input.

<Effects of the Invention> As explained in detail above, according to the present invention, malfunctions caused by extremely narrow pulses of opposite polarity, which occur in conventional circuits, do not occur, and the circuit is not easily affected by the environment. This has the effect of not impairing the advantage that the comparison time can be determined with high precision by using the delay line.

[Brief explanation of drawings]

FIG. 1 is a basic configuration diagram of a narrow pulse width detection circuit according to the present invention, FIG. 2 is an embodiment configuration diagram showing the detailed configuration of each part, and FIG.
5 and 4 are time charts for explaining the operation, FIG. 5 is a configuration diagram showing an example of a conventional narrow pulse width detection circuit, and FIGS. 6 and 7 are for explaining the operation of the circuit in FIG. 5. This is a time chart for 20... Variable delay element, 21... Edge detection section, 2
2... Narrow pulse detection section, 23... Input buffer, 2
11.212,213...D type flip-flop, 2
14...Exclusive Noah Gate.

Claims (1)

[Claims] A delay element (20) that delays an input signal (IN) by a predetermined time (Td) set by external data and outputs the delayed signal; , which generates a signal that becomes HIGH level at the falling edge, and if the input signal (IN) falls while being delayed by the delay element (20), the input signal is output from the delay element (20). An edge detection section (21) configured to hold the output signal at a HIGH level state until the input signal (IN) rises again after the input signal is sent out; and the output of this edge detection section (21). It is equipped with a narrow pulse detection section (22) that latches the signal state at the rising edge of the input signal (IN) via the variable delay element (20), and the output of the narrow pulse detection section (22) is used to detect the signal state from the delay time width. A narrow pulse width detection circuit is characterized in that it is capable of detecting a short narrow pulse input.