JPH03200080A - Testing device for integrated circuit - Google Patents

Abstract

PURPOSE:To measure the time of response delay for an integrated circuit in a short time by automatically and successively delaying the supply timing for a comparative timing pulse given to a comparator without rewriting the timing data stored in a control memory. CONSTITUTION:The delay time at initial stage of comparative timing pulse is stored in a timing data storing device 62 and also the generating cycle of comparative timing pulse is detected by a detecting means 61 for comparative timing pulse generating cycle. By a timing data selecting device 64, the delay time which is stored in the storing device 62 for every time when the generating cycle of comparative timing pulse is detected by the detecting means 61, is supplied to a timing generator 20. By an increment means 63, the delay time of storing device 62 is incremented each time when the set value of the delay time of comparative timing pulse is selected by the selecting device 64. Consequently, the delay time of comparative timing pulse can be extended successively without rewriting the timing data in the control memory; therefore, the delay time of response for the integrated circuit to be tested can be measured in a short time.

Description

Detailed Description of the Invention: Industrial Application Field J This invention relates to an integrated circuit testing device for testing integrated circuit devices such as LSIs, and in particular to an integrated circuit testing device that can measure response delay times of integrated circuits at high speed. The purpose is to provide a circuit testing device.

"Prior Art" When testing whether an integrated circuit has been manufactured to have the intended characteristics, a DC test to test the DC characteristics of the integrated circuit and a functional test to check whether the circuit operates normally are performed. It will be done.

Functional tests include tests in which a test pattern signal is applied to the integrated circuit under test, and pass/fail is determined by checking whether the response output matches a predetermined expected value; There is a test in which pass/fail is determined by measuring the time until a response signal is output and checking whether the delay time required for the response is within a predefined time range.

This invention relates to an improvement in a test device that operates when testing whether the response delay time of an integrated circuit falls within a specified time range, and its purpose is to shorten the response delay time of an integrated circuit. The present invention aims to provide an integrated circuit testing device that can measure time and perform high-speed processing.

FIG. 5 shows the configuration of a conventional integrated circuit testing device.

Circular 10 shows a pattern generator. pattern generator 10
In general, the sequence controller 11 and the control memory 1
2 and a pattern memory 13, access to the control memory 12 and pattern memory 13 is controlled by address information output from the sequence controller 11, and timing data for test pattern generation is read from the control memo IJ12. memory 13
The pattern data and expected value pattern data are read out.

Timing data read from control memory 12 is provided to timing generator 20. timing generator 20
generates a timing pulse that defines the timing of the rise and fall of the actual waveform of the test pattern signal given to the integrated circuit under test 40 based on the timing data sent from the control memory 12, and uses this timing pulse as a waveform generator. Give to container 30.

The waveform generator 30 generates a test pattern signal to be applied to each terminal of the integrated circuit under test 30 according to the timing pulse applied from the timing generator 20 and the pattern data applied from the pattern memory 13, and
Give a test pattern signal to each terminal of 0.

On the other hand, the timing pulse output from the timing generator 20 is also given to the comparator 50. The comparator 50 outputs the expected value pattern data given from the pattern memory 13 and the response signal of the integrated circuit under test 4o to the timing generator 2.
The timing pulses given from 0 are compared, and if a mismatch is detected, the integrated circuit under test 40 is determined to be defective.

The tests up to this point are tests to determine whether or not the system operates normally, among the functional tests described above.

A test for measuring the response delay time of the integrated circuit under test 40 is conducted as shown in FIG.

The test pattern DiN shown in FIG. 6A is applied to the integrated circuit under test 4.
Input to data input terminal 0. Test pattern I)tN
is given to the data input terminal, and the timing generator 2
The clock CLK shown in FIG. 6B outputted from 0 is applied to the clock input horn terminal of the integrated circuit under test 40.

The test pattern Di11 shown in FIG.
LK is applied to the clock input terminal of the integrated circuit under test 40.

FIG. 6C shows the response signal D o u of the integrated circuit under test 40.
Indicates t. Timing L of the rising edge of the clock CLK shown in the figure. Response signal from. ut rising timing 1
, to indicate the response delay time TPd of the integrated circuit under test 40.

In order to measure this response delay time TPd, conventionally, a timing generator 20 generates a comparison timing pulse CMP as shown in FIG.
P is applied to the comparator 50, and a response signal corresponding to the test pattern D8.4 is input to the integrated circuit under test 40 at the timing when the comparison timing pulse CPM is applied. 0. is output by comparing it with the expected value pattern.

In the comparator 50, a comparison operation using the comparison timing pulse CMP is performed once every cycle of the clock CLK. In other words, the comparison timing pulse CMP is the clock CL.
Also the timing of K's rise.

is applied to the comparator 50 while sequentially extending the delay time each time the same pattern, for example, pattern A, is generated starting from
The comparison timing pulse C is applied to the comparator 50 until the response output of the integrated circuit under test 40 matches the expected value pattern.
The delay time of M P is successively extended, and when a match is detected, a response signal is generated from the delay time of comparison timing pulse CMP. The response signal of the integrated circuit under test 40 is determined by matching the delay time of uL. Define the delay time of ut.

"Problem to be Solved by the Invention" As described above, the response signal D ou of the integrated circuit under test 40
To measure the delay time of t, use the comparison timing pulse CM
The comparator 50 repeats sequentially extending the delay time of P.
A response signal is generated at the supply timing of the comparison timing pulse CMP. This operation is repeated until uL matches the expected value.

In conventional test equipment, comparison timing pulse CMP
In order to change the generation timing of , it is necessary to rewrite the timing data stored in the control memory 12.

For this purpose, it is necessary to generate a test pattern for one test cycle and rewrite the timing data in the control memory before entering the next pattern initial delay time. Figure 7 shows the situation. The period XX shown in the figure indicates the time required to rewrite the timing data in the control memory 12.

In this way, the period X during which the timing data of the comparison timing pulse CMP is rewritten every initial delay time of the test pattern
This method has the drawback that the test time is long because X is required.

"Means for Solving the Problem" In the present invention, timing data for pattern generation is successively output from the control 0 memory constituting the pattern generator, this timing data is given to the timing generator, and the timing generator generates a test pattern. The signal is converted into a timing signal necessary for generating the actual waveform, and this timing signal and pattern data output from the pattern memory are fed to a waveform generator to generate a test pattern signal, and this test pattern signal is used as the test pattern signal. The response signal of the integrated circuit under test is given to the comparator, the response signal of the integrated circuit under test is read by the comparison timing pulse in the comparator, this response signal is compared with the expected value pattern, and the response signal of the integrated circuit under test is In an integrated circuit paper testing device, the response delay time from the time when a test pattern signal is applied to the circuit until a response signal is obtained is measured by the delay time of a comparison timing pulse applied from the timing generator to the comparator. , a timing data storage device for storing an initial delay time of a comparison timing pulse; a comparison timing pulse initial delay time detection means for detecting an initial delay time of a comparison timing pulse; and a comparison timing pulse initial delay time detection means for detecting an initial delay time of a comparison timing pulse. A timing data selector provides the delay time stored in the timing data storage to the timing generator each time the initial delay time of the timing pulse is detected. An integrated circuit testing device is constructed by providing an incrementing means for incrementing the delay time of the data storage device.

According to the configuration of the present invention, the delay time of the comparison timing pulse can be extended sequentially without rewriting the timing data in the control memory. Therefore, the response delay time of the integrated circuit under test can be measured in a short time.

"Embodiment" FIG. 1 shows an embodiment of the present invention. In the figure, 10 is a pattern generator, 20 is a timing generator, 30 is a waveform generator, 40 is an integrated circuit under test, and 50 is a comparator, as described above.

In this invention, a pattern generator 10 and a timing generator 2
a comparison timing pulse initial delay time detection means 61 for detecting the initial delay time of the comparison timing pulse between 0 and 0; a timing data storage 62 storing the delay time of the comparison timing pulse; and a comparison timing pulse initial delay time detection means 61 detects the initial delay time of the comparison timing pulse, the incrementing means 63 increments the stored value of the timing data storage 62, and the comparison timing pulse initial delay time detection means 61 detects the initial delay time of the comparison timing pulse. The structure is characterized by a timing data selector 64 that switches the timing data given to the timing generator 20 to the delay time stored in the timing data storage 62 at each time.

In this embodiment, the initial delay time of the comparison timing pulse is stored in the timing data storage device 62, and the comparison timing pulse is generated by a coincidence detection circuit that detects that timing data corresponding to this initial delay time is output from the control memory 12. The initial delay time detection means 61 is constituted by a counter 63A and an adder 63B that count the number of times the comparison timing pulse initial delay time detection means 61 detects the initial delay time of the comparison timing pulse. A case where the increment means 63 is configured is shown.

That is, timing data for pattern generation is read from the control memory 12. The main part of the timing data read from the control memory 12 is directly given to the timing generator 20, converted into timing pulses, and sent to the waveform generator 30.

On the other hand, comparison timing data that defines the generation timing of the comparison timing pulse sent to the comparator 50 is provided to the timing generator 20 through the timing data selector 64.

The timing data selector 64 is normally switched to a state in which the comparison timing data read from the control memory 12 is input directly to the timing generator 20, but the comparison timing pulse initial delay time detection means 61 detects the initial delay time of the comparison timing pulse. Every time a delay time is detected, the timing data selector 64 selects the comparison timing data stored in the timing data storage 62 and inputs the selected comparison timing data to the comparator 50.

The comparison timing pulse initial delay time detecting means 61 detects the comparison timing pulse when the comparison timing data in the timing data read from the control wholesale memory 12 matches the initial delay time of the comparison timing pulse stored in the timing data storage device 62. It is regarded as the initial delay time and a period detection signal of the comparison timing pulse is output.

When the comparison timing pulse initial delay time detection means 61 detects the initial delay time of the comparison timing pulse, first,
The timing data selector 64 switches to select the timing data stored in the timing data storage 62 and provides it to the timing generator 20.

That is, in this embodiment, the addition output of the adder 63B constituting the incrementing means 63 is selected. At the time of the first detection of the initial delay time of the comparison timing pulse, the count value of the counter 63A is still O, so the adder 63B adds timing data corresponding to the initial delay time of the comparison timing pulse read from the control memory 12. It is taken in as is and sent to the timing generator 20.

At the same time as the timing data selector 64 sends the added data of the adder 63B to the timing data selector 64, the counter 63A counts the detection signal output from the comparison timing pulse initial delay time detection means 61 and stores .

When the first test is completed and the comparison timing pulse initial delay time detection means 61 detects the second initial delay time, the adder 63B adds the initial delay time value read from the control memory 12 to the counter 63A. The stored 1 is added to the timing generator 20 to set the initial delay time to I.
Input the comparison timing data with N seconds added.

In this way, each time the initial delay time of the comparison timing pulse is detected, the count value stored in the incrementing means 63 is incremented by 1, and this count value is added to the initial delay time value by the adder 63B, and the timing generator 20 are input sequentially.

This situation will be explained using FIGS. 2 and 3.

In the example shown in the figure, in the control memory 12, when the address A is read, the timing data B of the comparison timing pulse is
The case where is read is shown.

Each time the timing data B is read, the count value of the counter 63A increases by +1, and the timing data given to the timing generator 20 is B for the first time and B+1 for the second time.
．． The third time changes to B+2. The fourth time changes to B+3. In this way, the timing data given to the comparator 5° is sequentially increased by +1, and the delay time of the comparison timing pulse is gradually extended, for example, by IN seconds, and this operation causes the comparator 5° to output a coincidence detection signal. repeated until.

This example shows a case where the comparator 5o can read the response output of the integrated circuit under test 40 using the comparison timing pulse in the fourth test cycle, and the read response signal matches the expected value.

The timing data B+3 applied to the timing generator 2o at this time corresponds to the response delay time of the integrated circuit under test 4°.

FIG. 4 shows another embodiment of the invention. In this example, a case is shown in which the comparison timing pulse initial delay time detection means 61 is constituted by a pattern number storage 61A, a pattern counter 61B, and a -number calculation circuit 61C.

Therefore, in this example, the number of occurrences of the pattern is detected by counting the signals output from the sequence controller 11, and each time the number of occurrences of the pattern reaches the pattern in which the timing data of the comparison timing pulse is written, the coincidence detection circuit 61C It is configured to generate a period detection signal.

That is, the signal output from the sequence controller 11 is counted by the pattern counter 61B to count the number of times the pattern has occurred.

When the number of pattern occurrences matches the number of patterns set in the pattern number storage 61A, the match detection circuit 61C outputs a match detection signal. In other words, the number from the first pattern of the test cycle to the pattern in which the comparison timing data is written is set in the pattern number memory 61, A, and each time the number of patterns is reached, the initial delay time detection signal of the comparison timing pulse is detected as a match. It is output from the circuit 16C.

The timing data selector 64 is switched and controlled by outputting the period detection signal of the comparison timing pulse from the coincidence detection circuit 16C, and the timing data given from the incrementing means 63 is selected, and the timing generator 20
Output to.

In this example, the incrementing means 63 uses a counter that can be preset to pre-present data corresponding to the initial delay time of the comparison timing pulse set in the timing data storage 62, and in this state, the comparison timing pulse initial delay time detection means 61, the incrementing means 63 adds 1 to its preset value. Therefore, when the second period is detected, the delay data incremented by +1 is given to the timing data selector 64, and the delay time of the comparison timing pulse is sequentially extended.

"Effects of the Invention" As explained above, according to the present invention, the control memo IJ12
The structure is such that the supply timing of the comparison timing pulse given to the comparator 50 is automatically and sequentially delayed for each test count without rewriting the timing data stored in the comparator 50.
The time required for rewriting can be reduced. Therefore, the response delay time of an integrated circuit can be measured in a short time.
High-speed processing becomes possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram for explaining one embodiment of this invention, FIGS. 2 and 3 are diagrams for explaining the operation of the main parts of this invention, and FIG. 4 is a block diagram for explaining another embodiment of this invention. FIG. 5 is a block diagram showing an example, and FIG. 5 is a block diagram for explaining the conventional technique. FIGS. 6 and 7 are diagrams for explaining the operation of the conventional technique. lO: pattern generator, 20: timing generator, 30
: waveform generator, 40: integrated circuit under test, 50: comparator,
61: Comparison timing pulse initial delay time detection means, 6
2: Timing data storage device, 63: Increment means, 64: Timing data selector.

Claims (3)

[Claims] (1) A. Timing data for pattern generation is read from the control memory that constitutes the pattern generator, this timing data is given to the timing generator, and the timing data is used to generate the actual waveform of the test pattern signal. The timing signal and the pattern data output from the pattern memory are converted into a timing signal, and the timing signal and the pattern data output from the pattern memory are applied to a waveform generator to generate a test pattern signal, and this test pattern signal is applied to the integrated circuit under test. The response signal of the integrated circuit under test is applied to the comparator, the response signal of the integrated circuit under test is read by the comparison timing pulse in the comparator, this response signal is compared with the expected value pattern, and the test pattern signal is applied to the integrated circuit under test. In an integrated circuit testing apparatus, the response delay time until a response signal is obtained from the timing generator is measured by the delay time of the comparison timing pulse given from the timing generator to the comparator, wherein: B. the initial delay of the comparison timing pulse; a timing data storage device for storing time; C. comparison timing pulse generation cycle detection means for detecting the generation cycle of the comparison timing pulse; and D. the comparison timing pulse generation cycle detection means detects the generation cycle of the comparison timing pulse. E. a timing data selector that supplies the delay time stored in the timing data storage device to the timing generator each time E. An integrated circuit testing device comprising: incrementing means for incrementing the delay time of a data storage device. (2) The comparison timing pulse generation period detecting means according to claim (1) is connected to a timing data storage device and detects that the same timing data as the timing data stored in the timing data storage device is read out from the control memory. An integrated circuit testing device configured with a coincidence detector. (3) The comparison timing pulse generation cycle detecting means according to claim (1) comprises a pattern number memory that stores the number of patterns generated within a predetermined cycle, and a pattern counter that counts the number of test patterns applied to the integrated circuit. An integrated circuit testing device comprising: a coincidence detector for detecting coincidence between the number of patterns stored in the pattern number storage device and the counted value of the pattern counter.