JPH03200081A - Skew adjusting circuit for waveform containing jitter - Google Patents

Abstract

PURPOSE:To accurately perform a skew correction for high speed devices by leading out a center of jitter from the number of fails with the use of fail counter. CONSTITUTION:Each output of test signal generators 1A-1C are connected to skew circuits 2A-2C and these outputs are connected to drivers 3A-3C. The output of a multiplexer 4, to which the outputs of drivers 3A-3C are inputted, is inputted to a reference comparator 5, then this output and a decision strobe 6A are inputted to a decision circuit 6. By a selector 7 in which the output 6B of decision circuit 6 is made as the input, the output is forwarded to lines 7B and 7A in accordance with a jitter correcting mode signal 7C. The output of a fail counter 8 connected to the line 7B and the output of line 7A are connected to a CPU 9. The center of jitter is obtained by the use of fail counter 8, then by means of transferring the skew data resulted from the calculation in the CPU 9 to the skew circuits 2A-2C through a skew register 10, the skew is corrected for the center of jitter area.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a skew adjustment circuit for waveforms containing jitter.

[Prior Art] Skew is a deviation from an expected value in phase or time that occurs between signals when the same signal is transmitted in a plurality of transmission systems, and includes skew between drivers.

Next, the reason why skew adjustment is necessary will be explained with reference to FIG.

In Fig. 5, 1A to 1C are test signal generators, 2A to 2C are skew circuits, 3A to 3C are drivers, 4 is a multiplexer, 5 is a reference comparator, 6 is a judgment circuit, and 9 is a CPU.
, 10 are registers.

In Figure 5, 3 from 1A to 1C12A to 2C13A to 3C
Although an example of 2 is shown, other numbers may be used.

The test signal generators 1A to 1C output test signals to each bin of the device at required timings, which pass through the skew circuits 2A to 2C and drivers 3A to 3C, and are applied to each bin of the device.

Each bin of the device must be input according to the set timing, but even if the timing of the output waveform of the test signal generators 1A to 1C is the same, the skew circuits 2A to 2
A skew difference occurs due to errors in the circuits of the drivers 3A to 3C, and variations in the elements used. Therefore, it is necessary to correct the skew deviation in advance.

Next, the skew adjustment circuit will be explained.

The test signal generators 1A to 1C are made to output at the same timing. This waveform is for skew circuits 2A to 2C and driver 3A.
~3C and enters the preset multiplexer circuit 4.

In this multiplexer circuit 4, test signal generators 1A to
The output waveform of 1C is sequentially taken out to line 4A and connected to reference comparator 5.

The signal waveform input to the reference comparator 5 is used to determine whether the device is bus or fail by a determination circuit 6 and a determination strobe 6A.

In FIG. 5, the timing is set to 1 of the skew circuits 2A to 2C.
Only the parts have been corrected.

Next, for each bin of the skew circuits 2A to 2C, the CPU 9
From there, the skew correction data is sequentially transferred to the register 10 like a pinary search, and the skew correction data is sequentially transferred to the register 10 from
At step C, the information is given to each of the skew circuits 2A to 2C, and while operating the waveform, the position where the conversion point of fail comes from the bus is determined at the timing of the reference determination strobe 6A.

Through this operation, the skew correction data obtained for each bin is latched into the register 10, and the data is stored in the CPU 9 as a file. The skew is adjusted in this way.

Next, the skew operation shown in FIG. 5 will be explained with reference to FIG.

FIG. 6 (γ) is the output waveform of the test signal generator IA,
FIG. 6(A) shows the output waveform of the skew circuit 2A.

The skew circuit 2A performs skew correction by changing the waveform of FIG. 6(A) back and forth by the timing Tw.

FIG. 6(a) shows the output voltage waveform of the driver 3A, which is set to an amplitude to be applied to an actual device.

The outputs of FIG. 6 are selected by multiplexer 4 and applied to reference comparator 5.

FIG. 6(1) is an explanatory diagram of the operation of the reference comparator 5, and shows the voltage V. Use □ to judge the level.

Voltage V04. is the high comparator level, and the low comparator level V. In some cases, it is determined by L.

FIG. 6(E) shows the output waveform of the reference comparator 5.

FIG. 6 (force) shows the waveform of the determination strobe 6A that enters the determination circuit 6. The strobe is a value that defines the time position when determining pass/fail.

Inside the determination circuit 6, the output of the reference comparator 5 is latched by the determination rope 6A to determine the timing.

FIG. 6(g) is an output waveform diagram of the determination circuit 6, which is compared with the expected pattern to obtain pass and fail.

Next, the relationship between the test signal generators IA and 7B will be explained.

FIG. 6 (9) shows the waveform when the output waveform of the test signal generator IA arrives at the determination circuit 6, and FIG. This is the waveform of

Although FIG. 6(9) and FIG. 6) are output at the same timing, there is a timing difference of time T at the input point of the determination circuit 6 in FIG.

FIG. 6(C) shows the waveform of the determination strobe 6A, and the waveform 6(9) is ahead of the set value of the determination strobe 6A, and the waveform 6(9) is behind.

In such a case, the skew circuits 2A and 2B shown in FIG.
works. FIG. 6(S) is a waveform obtained by correcting FIG. 6(9), and FIG. 6(C) is a waveform obtained by correcting FIG. 6(E). As shown in FIGS. 6(a) and 6(b), the waveforms move to the same change point, and the skew deviation in the pin direction is corrected.

[Problems to be Solved by the Invention] In the skew adjustment shown in Fig. 5, the skew is corrected by making a judgment at one point of change in the test signal waveform. If there is jitter as shown in Figure 7 that occurs in the waveform output to
It is unclear at what timing the skew was corrected, 21.23.25.27 for the rising waveform and 22.24.26 for the falling waveform, and this also deteriorates the timing accuracy.

Furthermore, when a high-speed waveform is generated, jitter increases, which becomes a big problem. Therefore, it is necessary to clarify the skew adjustment method when such jitter is included.

An object of the present invention is to provide a skew adjustment circuit that uses a fail counter in a conventional circuit to derive the center of jitter from the number of failures and adjust the skew.

[Means for Solving the Problems] In order to achieve this object, the present invention provides skew circuits 2A to 2C connected to each output of the test signal generators 1A to 1C, and a Drivers 3A to 3C and drivers 3A to 3C are connected respectively.
A multiplexer 4 which receives the output of 3C as an input, a reference comparator 5 which uses the output of the multiplexer 4 manually, a judgment circuit 6 which takes the output of the reference comparator 5 and a judgment strobe 6A as inputs, and a judgment circuit 6 which takes the output of the judgment circuit 6 as input. , a selector 7 that outputs outputs to lines 7B and 7A in jitter correction mode 7C, a fail counter 8 connected to line 7B, an output of fail counter 8, and line 7.
A is connected to the CPU 10, and the output of CPU10 is connected to the register 1, which connects the output to the drivers 3A to 3C.
0.

Next, a skew adjustment circuit for a waveform including jitter will be explained with reference to FIG.

In FIG. 1, 7 is a selector, 8 is a fail counter,
Other details are the same as in Figure 5.

That is, FIG. 1 is the same as FIG. 5 with a selector 7 and a fail counter 8 added.

When the selector 7 selects the line 7A, the circuit becomes the same as that shown in FIG.

When the selector 7 selects the line 7A, the skew is corrected for the output waveforms of the test signal generators 1A to 1C as shown in FIG.

In Fig. 1, when the selector 7 switches to line 7B (iTl) in the jitter correction mode 7C, the signal waveform is judged for 11 patterns while operating in a certain range using the skew circuits 2A to 2C. Then, calculate the number of failures at that time using the fail counter 8 with a force of 1 kun l-L, calculate the uncertainty area from the number of failures obtained, and calculate the center value (n / 2) to calculate the jitter. The skew can be corrected with respect to the center of the image.

[Function] In FIG. 1, a selector 7 and a fail counter 8 are placed in the bus/fail result 6B line in FIG. 5.

When the line 7A is selected with the selector 7 in FIG. 1, the point of change can be found by performing a pinary search using the normal one-pattern skew correction.

Next, the 8 jitter correction mode signal 7C is used to switch to line>'7B, and the skew data is changed in the range of -Ins to +lns with the skew data obtained on line 7B as the center.
By stepping the signal waveform, repeating the pattern test 0 times, and performing a search test, the number of failures occurring in each timing state is counted by a fail counter.

Based on this count number, if r□, then it is a bus area.

If n is a fail area, if 1 to (n-1) is a jitter area, and skew data at a position near 1/2 within this jitter area is transferred to skew circuits 2A to 2C.

In this manner, in FIG. 1, the center of jitter is determined without using fail counts, and the skew is corrected.

Next, the operation shown in FIG. 1 will be explained with reference to FIG. 2.

In FIG. 2(A), skew data after skew correction is obtained.

Next, add jitter correction mode signal 7C to selector 7,
Selector 7 selects line 7B.

In this state, the skew data for jitter is corrected in order from the output waveform of the test signal generator IA to the output waveform of the test signal generator 7C.

The method will be explained based on the output waveform of the test signal generator IA.If a pattern that repeats itself n times is generated from the signal waveform, the waveform will contain jitter as shown in FIG. 2(A).

Here, from the standard skew data obtained in Figure 5, the second
As shown in the waveform during jitter correction in Figure (1), -1ns
The data is latched by the register 10, the waveform is passed through the skew circuit 2A, and the driver 3
A. Select the multiplexer 4, enter the judgment circuit 6 via the reference comparator 5, and obtain a pass/fail result 6B with the judgment strobe 6A at the reference setting timing.

This operation is repeated until about +l ns as shown in (1) in Figure 2 (1) of the standard skew data.
In execution, the skew data step is performed with the minimum skew data change necessary to change the delay line by the minimum variable step.

Here, in the process of pass/fail result 6B executed from -1 ns to +Ins, only the fail information that appears at each timing is counted by the newly installed fail counter 8, and the counted number is sent to the CPU 9. .

1 ns to +Ins are sequentially tested in variable steps of the minimum skew data.

At this time, as shown in FIG. 7, the pattern is determined n times in one test using the effective determination rate.

Therefore, if n=100, in the case of a complete pass, the count number of fail occurrences is "0", and in the case of a complete fail, the count number of fail occurrences is r
It becomes 100J.

Here, T in Figure 2 (a). The jittered portions shown by are the portions that pass or fail depending on the rate in patterns 1 to n in FIG. 7, so the number of fails changes with the set timing.

Therefore, in the example (2), fail counts in the digital area from 1 to 99 are obtained.

Further, for the jittered portion shown by T6 in FIG. 2(a), the fail count is obtained from 1 to (n-1). At this time, the CPU 9 performs calculations to obtain skew data in a state where a fail count close to n/2 has been obtained.

If the signal is transferred to the skew circuits 2A to 2C, the skew will be corrected approximately to the center of the jitter region.

In this way, the skew can be corrected for each signal waveform under the same conditions.

In addition, although the signal waveform has been explained in FIG. 2, as shown in the CMP skew block diagram in FIG. 3 and the I10 skew block diagram in FIG. Highly accurate skew correction can be performed using each skew circuit method.

Normally, in a 7C tester, the parts that require skew correction include the driver skew correction shown in FIG. 1, the CMP skew correction shown in FIG. 3, and the I10 skew correction shown in FIG. 4.

Note that CMP is a comparator.

The CMP skew correction shown in Figure 3 corrects the waveform entering the device so that there is no variation from pin to pin.
This is to correct variations in CMP output from bin to bin so that no matter which CMP bin the waveform output from the device is judged to yield the same result.

The effect of Figure 3 is as follows.

The waveform from the reference driver passes from driver 31 through multiplexer circuit 32 and is applied to each bin of CMPs 33A-33C.

Each judgment strobe 34A to 34 calculates the variation of each line.
．． CMP skew times 35A to 35C where C is supplied
By correcting this, variations in the bin direction are eliminated.

The effect of Fig. 4 is as follows.

When measuring a device with an I10 bin, skew correction is performed so that the I10 switching signal does not vary from bin to bin.

The waveforms from each driver that have already been corrected are switched at the timing of I10 switching signals 42A to 42C,
The output waveforms are determined by CMPs 44A to 44C, respectively. Each output of CMP44A to 44C is determined by the judgment straw-1.
45A to 45C eliminate variations in the bin direction.

[Effects of the Invention] According to the present invention, when correcting the skew of a waveform containing jitter, the center of jitter is derived from the number of fails by using a fail counter.
More accurate skew correction can be performed for high-speed devices.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a skew adjustment circuit for a waveform including jitter according to the present invention, FIG. 2 is an explanatory diagram of the operation of FIG. 1, and FIG.
5 and 4 are block diagrams of other embodiments, FIG. 5 is a block diagram of a skew adjustment circuit according to the prior art, FIG. 6 is a diagram explaining the skew operation of FIG. 5, and FIG. 7 is a diagram explaining the effective rate of judgment. It is. ■A~7C...Test signal generator, 2A~2C・
... Skew circuit, 3A to 3C ... Driver, 4 ... Multiplexer, 5 ...
Reference comparator, 6... Judgment circuit, 7...
...Selector, 8...Fail counter, 9
...CPU, 10...Register.

Claims (1)

[Claims] 1. Skew circuits (2A to 2C) connected to each output of the test signal generator (1A to 1C), and drivers (2A to 2C) connected to the outputs of the skew circuits (2A to 2C), respectively. 3A, 3C), a multiplexer (4) that receives the output of the driver (3A to 3C) as input, a reference comparator (5) that receives the output of the multiplexer (4) as input, and determines the output of the reference comparator (5). Strobe (6A
) and a selector (7) which takes the output of the judgment circuit (6) as input and outputs to line (7B) and line (7A) in jitter correction mode (7C).
A fail counter (8) is connected to the line (7B), The output of the fail counter (8) is connected to the CPU (9), and the output of the CPU (9) is connected to the line (7A). Output to driver (3A
~3C) A skew adjustment circuit for waveforms containing jitter, characterized in that the circuit comprises a register (10) connected to a register (10).