JPH03200214A - Circuit for generating liquid crystal-driving voltage - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a liquid crystal drive voltage generation circuit in a time division method for a liquid crystal display device.

[Prior Art] A liquid crystal drive voltage generation circuit in a conventional time division drive method of a liquid crystal display device is configured as shown in FIG.

That is, in Fig. 6, E is a DC power supply whose terminal is grounded, and a variable resistor R1 and a resistor R are connected between the child terminal and the ground.
Two series circuits are connected. Then, the divided voltage between the variable resistor R1 and the resistor R2 is input to the child terminal of the differential amplifier A1. This differential amplifier A1 has one terminal grounded via a resistor Ra, and a feedback resistor Rb connected between the output terminal and the one terminal to constitute a non-inverting amplifier. The amplification factor is determined by Rb.

Then, the output signal of the differential amplifier A1 is taken out as the liquid crystal drive voltage 1, and is inputted to one terminal of the differential amplifier A2 via the resistor Re.

This differential amplifier A2 has a child terminal grounded and a feedback resistor Rd connected between the output terminal and one terminal to form an inverting amplifier, and the amplification factor is determined by the resistors Re and Rd. Ru. And this differential amplifier A2
The output is taken out as the liquid crystal drive voltage v5.

On the other hand, the output terminal of the differential amplifier A1 is connected to the resistors R3 and R
4 in series to ground, and the voltage generated at the connection point between resistors R3 and R4 is input to the + terminal of differential amplifier A3.

20 The differential amplifier A3 has an output signal fed back to one terminal, and constitutes a non-inverting voltage follower. Then, the output of this differential amplifier A3 is taken out as the liquid crystal drive voltage V2.

Further, the output signal of 3 to the differential amplifier is inputted to one terminal of the differential amplifier A4 via a resistor Re. This differential amplifier A4 has a child terminal grounded and a feedback resistor Rf connected between the output terminal and one terminal to form an inverting amplifier, and the amplification factor is determined by the resistors Re and Rf. .

Then, the output of the differential amplifier A4 is the liquid crystal drive voltage ■4
is extracted as.

In order to operate the above circuit, a differential amplifier AI is used.
, A2. A3. At A4, a positive power source E+ and a negative power source E- (not shown) are respectively rE+>vt.

It is supplied under the condition of E-<V5J.

Next, the operation of the above conventional example will be explained. The DC type 11NE is
The voltage is divided by variable resistor R1 and resistor R2, and the divided voltage is supplied to differential amplifier A1 as a reference voltage. In this case, the base Q voltage can be arbitrarily set by varying the variable resistor R1. The differential amplifier A1 amplifies the reference voltage divided by the resistors R1 and R2 with the same polarity and a magnification determined by the values of the resistors Ra and Rb, and outputs it as a liquid crystal drive voltage v1. At the same time, power is applied to the differential amplifier A2 via the resistor Rc. This differential amplifier A2 inverts the polarity with respect to this input, and also has a resistor Rc.

It is amplified by a magnification determined by the value of Rd and output as a liquid crystal drive voltage v5. Therefore, this liquid crystal drive voltage V5 is located at a level (-potential) that is symmetrical with respect to the liquid crystal drive voltage v1 with the ground potential (-V3) as the center.

Further, the output of the differential amplifier A1 is voltage-divided by resistors R3 and R4 and input to the differential amplifier A3.

20 Differential amplifier A3 outputs a voltage of the same polarity as the liquid crystal drive voltage V2 with respect to the divided voltage input, and resistor R
It is input to the differential amplifier A4 via e. This differential amplifier A4 inverts the polarity of the input voltage and amplifies it by a factor determined by the values of the resistors Re and Rf.
Output as liquid crystal drive voltage v4. This liquid crystal driving voltage v
4 is the ground potential (-V3) with respect to the liquid crystal drive voltage V2.
It is located at a level (-level) that is symmetrical about the center.

As described above, the liquid crystal drive voltage Vl, V2°V4. V5
However, in order to obtain a constant bias ratio as shown in FIG. 7, it is necessary to set rVl--V5 J and rV2--V4 J. Therefore, the inverting amplifier A2. A4 is “-
1j times the amplifier, and the resistors Re, Rd, Re, and Rf are set to rRc-RdJ and "Re-RfJ. In other words, the inverting amplifier A2 is a liquid crystal whose polarity is simply inverted with respect to the liquid crystal drive voltage v1. A driving voltage v5 is output, and the differential amplifier A4 outputs a liquid crystal driving voltage V4 whose polarity is simply inverted with respect to the liquid crystal driving voltage v2.

Since the liquid crystal driving voltage Vl is maintained at a constant bias ratio by the values of the resistors R3 and R4 and is input to the differential amplifier A2, the liquid crystal driving voltage V2°V4. V5 is entirely dependent on the liquid crystal drive voltage (1).

Further, the liquid crystal drive voltage V1 changes depending on the reference voltage. Therefore, by varying the reference voltage using variable resistor R1, all liquid crystal drive voltages Vl, V2, V
4. V5 is variable at the same time! , can be adjusted to the ia value. That is, in the above conventional method, each liquid crystal drive voltage VL, V2 . V4 and V5 are initially set at the optimum bias ratio, and are simultaneously variably adjusted by the variable resistor R1 so that the optimum potential is obtained while the bias ratio is fixed.

[Problems to be Solved by the Invention] However, the above conventional liquid crystal drive voltage generation circuit has the following problems.

■) Positive and negative power supplies must be supplied to the amplifier.

(2) Four differential amplifiers are required, making the circuit configuration complicated.

(2) There are five connections between the liquid crystal drive voltage generation circuit section and the liquid crystal drive circuit section, that is, Vl, V2. V3°V4. Since a portion corresponding to V5 is required, it is difficult to miniaturize the entire liquid crystal display device including the power supply circuit section, the liquid crystal drive voltage generation circuit section, the liquid crystal drive circuit section, and the control circuit section.

The present invention has been made in view of the above circumstances, and uses either the power supply or the negative power supply to provide Vl.

V2. V3. V4. It is an object of the present invention to provide a liquid crystal driving voltage generating circuit which can generate a liquid crystal driving voltage of V5 and which can simplify the circuit configuration and achieve miniaturization.

[Means and effects for solving the problem] The present invention has the following features:
A first switched capacitor circuit that inverts the first liquid crystal driving voltage and outputs a second liquid crystal driving voltage is provided for the first voltage source that outputs a liquid crystal driving voltage of A second switched capacitor circuit that inverts the third liquid crystal driving voltage and outputs a fourth liquid crystal driving voltage is provided for the second voltage source that outputs the liquid crystal driving voltage. It is.

With the above configuration, the first liquid crystal drive voltage output from the first voltage source is inverted by the first switched capacitor circuit to create the second liquid crystal drive voltage,
The third liquid crystal drive voltage output from the second voltage source is the second
is inverted by the switched capacitor circuit to create a fourth liquid crystal drive voltage. The first and second switched capacitor circuits are provided as described above. By inverting the second voltage source to generate the liquid crystal driving voltage, it is possible to generate the first to fourth liquid crystal driving voltages using either the positive power source or the negative power source. Furthermore, the number of amplifiers can be reduced and the circuit configuration can be simplified.

Further, the present invention integrates the first switched capacitor circuit with a liquid crystal drive circuit that selects and outputs the first and second liquid crystal drive voltages, and integrates the second switched capacitor circuit with the third and second switched capacitor circuits. The present invention is characterized in that it is integrated with a liquid crystal drive circuit that selects and outputs the fourth liquid crystal drive voltage.

By integrating the first and second switched capacitor circuits together with the liquid crystal drive circuit as described above, the circuit can be miniaturized.

[First Embodiment] The present invention will be described in detail below with reference to the drawings. In Figure 1, E is a DC power supply, one terminal of which is grounded, and
A series circuit of a variable resistor R1 and a resistor R2 is connected between the child terminal and ground. Then, the divided voltage between the variable resistor R1 and the resistor R2 is input to the child terminal of the differential amplifier A1. The differential amplifier A1 has one terminal grounded via a resistor Ra, and a feedback resistor Rb connected between the output terminal and the one terminal to constitute a non-inverting amplifier.
The amplification factor is determined by the values of the resistors Ra and Rb.

Then, the output signal of the differential amplifier AI is output to the output line 1.
1 as the liquid crystal drive voltage Vl, and
Grounded through resistors R3 and R4 in series, and resistors R3 and R
The voltage generated at the connection point with A2 is input to the child terminal of the differential amplifier A2. This differential amplifier A2 has an output terminal connected to one terminal, and constitutes a non-inverting voltage follower.

Then, the output of this differential amplifier A2 is taken out via the output line 12 as a liquid crystal drive voltage v2. The differential amplifiers At and A2 have a ground and a positive power supply E as operating power supplies.
+ is supplied under the condition of "E+>VI J.

Further, the output line 11 from which the liquid crystal drive voltage V1 is taken out is connected to the output line 15 via the first switched capacitor circuit 13. The switched capacitor circuit 13 includes analog switches SWI, SW2,
Consisting of SW3, SW4 and capacitors Ca and Cb,
An analog switch SWI is connected between output line 11 and output line 15.

SW2, SW3, and SW4 are connected in series, and the connection point between analog switches SW3 and SW4 is grounded. And analog switch SW2. A capacitor cb is connected in parallel to SW3, and is also connected between the output line 15 and ground. The above analog switch SWt.

SW3 is on/off controlled by the clock pulse CIA shown in FIG. 2, and is controlled by analog switches SW2. SW4 is controlled on/off by clock pulse CKB.

That is, analog switch SW2. SW3 is a clock pulse CKA.

It turns on when CKB is high level and turns off when it is low level. The clock pulses CIA and CKB have the same period, for example, 2H (IH is one horizontal scanning period) and have a period of 180
They have a phase difference of @, and are set so that they do not become high level at the same time.

On the other hand, the output line 12 from which the liquid crystal driving voltage V2 is taken out is connected to the output line 16 via the second switched capacitor circuit 14. The second switched capacitor circuit 14 includes an analog switch SW5.5WI
Analog switches SW5, SWG, SW7, and SW8 are connected in series between the output line 12 and the output line 16, and the connection point between the analog switches SW5 and SWG is grounded. be done. A capacitor Cc is connected in parallel to the analog switches SW6 and SW7, and a capacitor Cd is connected between the output line 16 and ground. The analog switch SW5.3W7 is on/off controlled by the clock pulse CKC, and the analog switch SW5.3W7 is controlled on/off by the clock pulse CKC.

SW8 is controlled on/off by a clock pulse CKD. That is, the analog switch SW5゜swe is
It is turned on when the clock pulses CKC and CKD are at the high level, and turned off when the clock pulses are at the low level.

The clock pulses CKC and CKD have, for example, a period of 2H and a phase difference of 180', similar to the clock pulses CIA and CKB.

Next, the operation of the above embodiment will be explained. The DC power supply E is voltage-divided by a variable resistor R1 and a resistor R2, and the divided voltage is supplied to the differential amplifier At as its reference voltage. The reference voltage can be arbitrarily set by adjusting the variable resistor R1. Then, the differential amplifier AI amplifies the reference voltage with the same polarity and at a magnification determined by the values of the resistors Ra and Rb, and outputs the liquid crystal drive voltage v from the output line 11.
Output as l. Moreover, this voltage Vl is the resistance R3R
The voltage is divided by 4 and input to the differential amplifier A2. The differential amplifier A2 outputs the same voltage as the divided voltage input via the output line 12 as the liquid crystal drive voltage V2.

On the other hand, the first switched capacitor circuit 13 is controlled by clock pulses CKA and CKB to generate a liquid crystal drive voltage v5. That is, during the period when the clock pulse CIA is at a low level and the clock pulse CKB is at a low level as shown in FIG. 2, the analog switches SWI and SW3 are on, and the analog switches SW2 . SW4 is turned off, and the capacitor Ca is connected between the output line 11 and the ground. Therefore, in the capacitor Ca, the point A side connected to the analog switch SWI is charged to the V level, and the point B side connected to the analog switch SW3 is charged to the ground level.

Next, during the period when the clock pulse CKA is at a low level and the clock pulse CKB is at a high level, the analog switches swt and SW3 are off, and the analog switches SW2 .
SW4 is turned on, and point A of capacitor Ca is grounded, and point B is connected to output line 15. Therefore, the potential of the capacitor Ca at point B becomes -v1, and the capacitor cb connected to the output line 15 is charged to -Vl (point C) as shown in FIG.

Then, during the period when the clock pulse CKB is at low level,
Since analog switch SW4 is turned off, capacitor c
The voltage of 1 Vl charged in the voltage V1b is supplied to the load as the liquid crystal drive voltage V5.

Thereafter, the same operation is repeated, and the liquid crystal drive voltage v5 becomes
It is maintained at a level that is symmetrical with respect to the liquid crystal drive voltage Vl with respect to the ground potential (-V3). In this case, during the period when the analog switch SW4 is off, the capacitor c
Since the charged charge b is discharged through the load, the level of the liquid crystal drive voltage V5 fluctuates, but the level fluctuation is small and the brightness of the liquid crystal display panel does not change.

Further, the second switched capacitor circuit 14 also operates according to the clock pulses CKC and CKD, and the first
By the same operation as the switched capacitor circuit 13,
Generates liquid crystal drive voltage V4. This liquid crystal drive voltage v4 is maintained at a level that is symmetrical to the liquid crystal drive voltage v2 with respect to the ground potential C-V3.

In the above embodiment, the case where the positive power supply E0 was used as the operating power supply of the differential amplifiers Al and A2 was explained.
Even when using a negative power supply, the liquid crystal drive voltage Vl-
V5 can be generated.

As described above, in the first embodiment, the liquid crystal driving voltages vl to 5 can be generated using either the positive power supply or the negative power supply, and the switched capacitor circuits 13 and 14
By generating the liquid crystal drive voltage V5°V4,
The circuit configuration can be simplified by reducing the number of amplifiers. Furthermore, as in the above embodiment, the clock pulse CKA,
C.K.B.

When the cycle of CKC and CKD is set to 2H, the capacitors Cb and C of the switched capacitor circuit 13.14
The switching of charging and discharging for d is performed at the timing of the horizontal retrace period, and as a result, the liquid crystal drive voltage V
5. Even if a ripple occurs in V4, it will not affect the displayed image.

[Second Embodiment] Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 3 shows an example of a circuit in which the first switched capacitor circuit 13 is integrated with a liquid crystal drive circuit.

The first switched capacitor circuit 13 is configured by connecting MOS field effect transistors 21 to 24 in series as analog switches 5WI-SW5. in this case,
Transistor 21 is P-channel type, transistor 22
-24 use an N-channel type. The differential amplifier AI shown in FIG. 1 is connected to the drain electrode of the transistor 21.
A liquid crystal driving voltage V1 sent from the source via an output line 11 is supplied, and the source electrode of the transistor 24 is connected to the output line 15. Also, the transistor 22.2
A capacitor Ca is externally connected to the transistor 23.
．． A capacitor cb is externally connected to 24.

Further, an AC signal CKF for AC driving the liquid crystal display panel is input to the NOR circuit 26 and the NAND circuit 27 via the inverter 25, and the output of the inverter 25 is further input to the NOR circuit 26 via the inverter 28. and is input to the NAND circuit 27. The output signal of the NOR circuit 26 is passed through a level shifter 31 to the clock signal C
The signal is taken out as KA and input to the gate electrode of the transistor 23, and is also input to the gate electrode of the transistor 21 via the inverter 33. Further, the output signal of the NAND circuit 27 is taken out as a clock pulse CKB via an inverter 30 and a level shifter 32, and is input to the gate electrodes of transistors 22 and 24.

Further, the output signal of the inverter 25 is inputted to a selection voltage switching circuit 35 via a level shifter 34. This selection voltage switching circuit 35 includes a P-channel MOS field effect transistor 36 and an N-channel MOS field effect transistor 37, and a signal from the level shifter 34 is input to the gate electrode thereof. Further, the drain electrode of the transistor 36 is supplied with the liquid crystal drive voltage (1), and the drain electrode of the transistor 37 is supplied with the liquid crystal drive voltage v5. Then, the selection voltage VS is taken out from the source electrodes of the transistors 36 and 37. In the selection voltage switching circuit 35, when the output signal of the level shifter 34 is at a low level, the transistor 36 is turned on and the transistor 37 is turned off, and Vl is output as the selection voltage ■S. Further, when the output signal of the level shifter 34 is at a high level, the transistor 36 is turned off and the transistor 37 is turned on, and V5 is output as the selection voltage VS.

That is, depending on the level of the alternating current signal CKF, the selection voltage switching circuit 35 selects the voltage Vl or v5 as the selection voltage v.
Output as S.

Selection voltage VS output from the selection voltage switching circuit 35
are the output buffers 741a, 41b of the liquid crystal drive circuit 40,
...is supplied to... Moreover, this output buffer 41a,
41b, . . . are given the potential of V3.

Further, the liquid crystal drive circuit 40 is supplied with a scanning start signal DI. This scan start signal DI is applied to the inverter 42
．． The signal is input to the shift register 44 via 43. This shift register 44 includes a D-type flip-flop 45a,
45b,... are connected in series, and the clock pulse C
KN is connected to clock terminal CK via inverters 46 and 47.
is input. The shift register 44 reads the scan start signal DI using the clock pulse CKH, sequentially shifts it, and inputs it to the output buffers 41a, 41b, . . . . The output buffers 41a, 41b, . . . output a selection voltage vS when the input signal is at a high level, and output a non-selection voltage V3 when the input signal is at a low level. This output buffer 41a.

41b, . . . are scan electrode drive signals Xi, X2 . ...as a liquid crystal display panel (not shown)
sent to.

The level shifters 29, 30, 31 are configured as shown in FIG. 4, and the output buffers 41a41b, . . .
It is configured as shown in the figure.

The level shifters 29, 30, 31 shown in FIG. 4 are P-channel MOS field effect transistors 51, 5, respectively.
2. N-channel MOS field effect transistor 53.
54 and an inverter 55. That is, transistors 51.53 and 52.54 are connected in series, and voltage vi is supplied to the drain electrode of transistor 51.52, and voltage V5 is supplied to the drain electrode of transistor 53.54. The input signal is input directly to the gate electrode of the transistor 51 and is also input to the gate tti pole of the transistor 52 via the inverter 55. Furthermore, the source electrodes of transistors 51.53 are connected to the gate electrodes of transistors 54, and the source electrodes of transistors 52.54 are connected to the gate electrodes of transistors 53 and to the output line 56.

In the level shifter configured as described above, the transistors 51 and 52 are on/off controlled by an input signal, and the transistors 53 and 53 are controlled in accordance with the on/off operation.
4 is on/off controlled, and the voltage V1 is output from the output line 56.
Or v5 is taken out.

Further, an output buffer 41a shown in FIG.

41b, . . . are a level shifter 61 and an inverter 62.
, P-channel MOS field effect transistor 63, 6
5. Consisting of an N-channel MOS field effect transistor 64. That is, the input signal is inputted to the gate electrodes of transistors 64 and 65 via the level shifter 61, and is also inputted from the level shifter 61 to the gate electrode of the transistor 63 via the inverter 62. Also,
A selection voltage vS is applied to the drain electrodes of transistors 63 and 64.
is supplied, and the V3 potential is supplied to the drain electrode of the transistor 65. And transistor 63.64.6
5 source electrodes are collectively connected to an output line 66,
A selection voltage vS or a non-selection voltage v3 is taken out from this output line 66.

That is, when the level shifter 61 outputs a signal at the normal level, one of the transistors 63 and 64 is turned on depending on the level of the selection voltage S, and the transistor 65 is turned on.
is turned off and the selection voltage vS is taken out from the output line 66. Further, when a low level signal is output from the level shifter 61, the transistors 63 and 64 are turned off, the transistor 65 is turned on, and the non-selection voltage v3 is taken out from the output line 66.

In FIG. 3 above, the first switched capacitor circuit 13
Although the case has been described in which the second switched capacitor circuit 14 is integrated with the liquid crystal drive circuit, the second switched capacitor circuit 14 can also be integrated with the liquid crystal drive circuit in the same manner.

By integrating the first and second switched capacitor circuits together with the liquid crystal drive circuit as described above, the circuit can be miniaturized.

[Effects of the Invention] As detailed above, according to the present invention, the first. A second reference voltage source is provided to generate liquid crystal driving voltages of the same polarity and different levels, and the first reference voltage source is provided with a second reference voltage source to generate liquid crystal driving voltages of the same polarity and different levels. Since the output voltage of the second voltage source is input to the switched capacitor circuit to generate a liquid crystal drive voltage with inverted polarity, the first to fourth can generate a liquid crystal driving voltage of Moreover, by configuring the inversion voltage generation section with a switched capacitor circuit, the number of amplifiers can be reduced and the circuit configuration can be simplified.

Furthermore, since the present invention has a configuration in which the switched capacitor circuit is integrated with the liquid crystal drive circuit, the circuit can be miniaturized, and it is particularly effective when implemented in small liquid crystal display devices such as viewfinders. It is possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the same embodiment, and FIG. 3 is a block diagram showing a second embodiment of the present invention. 4
The figure shows details of the level shifter in Figure 3, and Figure 5 shows details of the level shifter in Figure 3.
The figure shows the details of the output buffer in Figure 3, and Figure 6 shows the details of the output buffer in Figure 3.
7 is a block diagram showing a conventional liquid crystal drive voltage generation circuit, and FIG. 7 is a diagram showing the relationship between bias voltage and liquid crystal drive voltage in the circuit of FIG. 6. At A2...Differential amplifier, 5wt-5w5...
Analog switch, 11, 12, 15.16... Output line, 13.14... Switched capacitor circuit,
35... Selection voltage switching circuit, 40... Liquid crystal drive circuit, 41a, 41b,...,... Output buffer, 44
...Shift register. Figure 12

Claims (2)

[Claims] (1) a first voltage source that outputs a first liquid crystal driving voltage;
a first switched capacitor circuit that inverts the first liquid crystal drive voltage and outputs a second liquid crystal drive voltage; a second voltage source that outputs a third liquid crystal drive voltage; A liquid crystal drive voltage generation circuit comprising: a second switched capacitor circuit that inverts the drive voltage and outputs a fourth liquid crystal drive voltage. (2) In the liquid crystal drive voltage generation circuit according to claim (1), the first switched capacitor circuit is integrated with a liquid crystal drive circuit that selects and outputs the first and second liquid crystal drive voltages, and the second switched capacitor circuit is integrated with a liquid crystal drive circuit that selects and outputs the first and second liquid crystal drive voltages. 1. A liquid crystal drive voltage generation circuit characterized in that a switched capacitor circuit is integrated with a liquid crystal drive circuit that selects and outputs third and fourth liquid crystal drive voltages.