JPH0320023A - Forming method for n-type diffused layer - Google Patents
Forming method for n-type diffused layerInfo
- Publication number
- JPH0320023A JPH0320023A JP15546189A JP15546189A JPH0320023A JP H0320023 A JPH0320023 A JP H0320023A JP 15546189 A JP15546189 A JP 15546189A JP 15546189 A JP15546189 A JP 15546189A JP H0320023 A JPH0320023 A JP H0320023A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- arsenic
- type
- capacitor
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 7
- 238000005468 ion implantation Methods 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 239000012535 impurity Substances 0.000 claims abstract description 4
- 238000009792 diffusion process Methods 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 8
- CXXPNVHRJBAYGS-UHFFFAOYSA-N [F].[As] Chemical compound [F].[As] CXXPNVHRJBAYGS-UHFFFAOYSA-N 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000003990 capacitor Substances 0.000 abstract description 10
- 229910052785 arsenic Inorganic materials 0.000 abstract description 9
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 7
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 230000006866 deterioration Effects 0.000 abstract description 6
- -1 fluorine compound ions Chemical class 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 125000001153 fluoro group Chemical group F* 0.000 abstract description 3
- 238000002955 isolation Methods 0.000 abstract description 3
- 238000006386 neutralization reaction Methods 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 125000004429 atom Chemical group 0.000 abstract description 2
- 239000000126 substance Substances 0.000 abstract 1
- 238000002513 implantation Methods 0.000 description 7
- 238000009826 distribution Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 230000006378 damage Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体の製造方法、特に砒素によるN型拡散
層を形成するのに有効なイオン注入法に関するもの.で
ある。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor manufacturing method, and particularly to an ion implantation method effective for forming an N-type diffusion layer of arsenic. It is.
従来の技術
イオン注入法を用いて砒素によるN型拡散層を形成する
場合には、砒素イオン(As”)が用いられている。1
た、イオン注入にかけるチャージアップを防止するため
に、エレクトロンシャワーと呼ばれる電子の層を注入直
前に導入することによシ、Am+イオンを電気的に中性
化して半導体基板面に砒素を注入する方法が採られてい
る。When forming an N-type diffusion layer of arsenic using conventional ion implantation, arsenic ions (As'') are used.1
In addition, in order to prevent charge-up during ion implantation, a layer of electrons called an electron shower is introduced just before implantation to electrically neutralize the Am+ ions and implant arsenic into the semiconductor substrate surface. method is adopted.
発明が解決しようとする課題
上記従来の技術では、注入条件によっては、電気的な中
性化が困難となる。特に、注入条件が注入量1×101
3cN一似上でビーム電流500μA以上という条件の
場合には、チャージアップが顕著となシ、キャパシター
絶縁膜やゲート絶縁膜などの破壊や劣化をもたらしてし
1う。本発明はこの問題点を解決出来る方法を提供せん
とするものである。Problems to be Solved by the Invention With the above-mentioned conventional techniques, electrical neutralization becomes difficult depending on the implantation conditions. In particular, the injection conditions are injection amount 1×101
If the beam current is 500 .mu.A or more at a current of 3 cN, charge-up will be significant, leading to destruction or deterioration of the capacitor insulating film, gate insulating film, etc. The present invention aims to provide a method that can solve this problem.
課題を解決するための手段
上記課題を解決するために、本発明では、砒素の弗素化
合物イオンをN型不純物源としてもちいた。Means for Solving the Problems In order to solve the above problems, the present invention uses arsenic fluorine compound ions as an N-type impurity source.
作 用
以上の構或において、弗素原子Fは、あらゆる原子のな
かで、最も電気陰颯性度が大きいものである。従って、
AsFn+はAs+よシも電子と結合しやすく、電気的
中性化が容易となる。つ1シ、AsFn+を用いた注入
では、注入雰囲気中の電子と結合するため、静電破壊や
絶縁膜質劣化を防止できる。さらに、高注入量・大ビー
ム電流の注入条件下においても、エレクトロンシャワー
を併用することで従来技術の問題点を解決できる。Function: In the structure described above, the fluorine atom F has the highest degree of electronegativeness among all atoms. Therefore,
AsFn+ is more easily bonded to electrons than As+, and electrical neutralization is facilitated. First, in implantation using AsFn+, since it combines with electrons in the implantation atmosphere, electrostatic breakdown and insulation film quality deterioration can be prevented. Furthermore, even under implantation conditions of high implantation amount and large beam current, the problems of the prior art can be solved by using an electron shower in combination.
実施例 本発明の一実施例を第1図にて説明する。Example An embodiment of the present invention will be explained with reference to FIG.
P型シリコン基板1上に素子分離領域2を形戒した後、
キャパシターかよびゲートを形或し、イオン注入する。After forming an element isolation region 2 on a P-type silicon substrate 1,
Shape and ion implant the capacitor and gate.
(第1図(a))。キャパシターは、N型拡散層3、絶
縁膜4と電極6で形或され、ゲートは、絶縁膜6と電極
7で形或されている。(Figure 1(a)). The capacitor is formed by an N-type diffusion layer 3, an insulating film 4, and an electrode 6, and the gate is formed by an insulating film 6 and an electrode 7.
注入イオンとして砒素の弗素化合物イオン(As+Fn
”Hn=1〜5 )8を用いた場合には、第1図(b)
に示す如く、N型拡散層9を形或しても、キャパシター
やゲートに何ら影響することがない。Arsenic fluorine compound ions (As+Fn
``Hn=1~5)8 is used, Figure 1(b)
As shown in FIG. 2, even if the N-type diffusion layer 9 is formed, it does not affect the capacitor or the gate in any way.
この場合の絶縁膜耐圧分布を第2図に示した。FIG. 2 shows the insulation film breakdown voltage distribution in this case.
砒素イオン(As”)10を用いた場合には、キャパシ
ター電極11やゲート電極14のチャージアップのため
に、破壊したキャパシター絶縁膜12や劣化したゲート
絶縁膜13を生じてしまう。この場合の絶縁膜耐圧分布
を第3図に示した。When arsenic ions (As'') 10 are used, a broken capacitor insulating film 12 and a deteriorated gate insulating film 13 are generated due to charge-up of the capacitor electrode 11 and gate electrode 14. Figure 3 shows the membrane breakdown pressure distribution.
本実験では、注入量が1E11〜1E21cI1−2の
範囲で、ビーム電流が0.1〜7.0mAの範囲で有効
であったが、特に、注入量が1E13〜1E17cII
−2でビーム電流が0.6〜s.OmAの領域で顕著な
差がみられた。In this experiment, it was effective when the implantation amount was in the range of 1E11 to 1E21cI1-2 and the beam current was in the range of 0.1 to 7.0mA.
-2, the beam current is 0.6~s. A significant difference was observed in the OmA region.
1た、弗素原子の数は1〜5個のいずれでも効果があっ
た。Furthermore, any number of fluorine atoms from 1 to 5 was effective.
第2図および第3図は、ともに注入量が3×1o15c
Ir2ビーム電流1 mAの場合であシ、絶縁膜として
は200nmの酸化シリコン膜を用いた場合の結果であ
る。In both Figures 2 and 3, the injection amount is 3 x 1o15c.
The results are for the case where the Ir2 beam current is 1 mA and a 200 nm silicon oxide film is used as the insulating film.
なお、本実施例では、一荷のイオンについてのべたが、
二荷以上のイオンについてもこうかがあることはいうま
でもない。In addition, in this example, a load of ions is described, but
Needless to say, this also applies to ions with two or more charges.
発明の効果
本発明の如く、砒素の弗素化合物イオンを注入すること
で、絶縁膜の静電破壊や膜質劣化のない、砒素によるN
型拡散層の形或が可能となった。Effects of the Invention As in the present invention, by implanting arsenic fluorine compound ions, there is no electrostatic damage to the insulating film or film quality deterioration, and N due to arsenic can be removed.
It is now possible to change the shape of the mold diffusion layer.
第1図(a),Φ)本発明の実施例を示す工程図、第2
図,第3図は木実施例の効果を示す分布図である。
1・・・・・・P型シリコン基板、2・・・・・・素子
分離領域、3,9・・・・・・N型拡散層、4,12・
・・・・・キャパシター絶縁膜、5,11・・・・・・
キャパンター電極、6,13・・・・・・ゲート絶縁膜
、7,14・・・・・・ゲート電極、8・・・・・・砒
素の弗素化合物イオン、10・・−・・・砒素イオン。Fig. 1(a), Φ) Process diagram showing an embodiment of the present invention, Fig. 2
3 are distribution charts showing the effects of the tree embodiment. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... Element isolation region, 3, 9... N-type diffusion layer, 4, 12...
...Capacitor insulating film, 5,11...
Capantor electrode, 6, 13... Gate insulating film, 7, 14... Gate electrode, 8... Arsenic fluoride compound ion, 10... Arsenic ion.
Claims (1)
を形成する工程において、N型不純物源として砒素の弗
素化合物イオンを注入することを特徴とするN型拡散層
の形成方法。A method for forming an N-type diffusion layer, which comprises implanting arsenic fluorine compound ions as an N-type impurity source in the step of forming an N-type diffusion layer in a semiconductor substrate of one conductivity type using an ion implantation method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15546189A JPH0320023A (en) | 1989-06-16 | 1989-06-16 | Forming method for n-type diffused layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15546189A JPH0320023A (en) | 1989-06-16 | 1989-06-16 | Forming method for n-type diffused layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0320023A true JPH0320023A (en) | 1991-01-29 |
Family
ID=15606560
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15546189A Pending JPH0320023A (en) | 1989-06-16 | 1989-06-16 | Forming method for n-type diffused layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0320023A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5366302A (en) * | 1991-07-25 | 1994-11-22 | Kanzaki Seishi Co., Ltd. | Thermal printer |
-
1989
- 1989-06-16 JP JP15546189A patent/JPH0320023A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5366302A (en) * | 1991-07-25 | 1994-11-22 | Kanzaki Seishi Co., Ltd. | Thermal printer |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3847810B2 (en) | Method for manufacturing mesa-isolated SOI transistor | |
| EP0996975B1 (en) | Hethod of fabricating a field effect transistor in silicon carbide | |
| US4925807A (en) | Method of manufacturing a semiconductor device | |
| US3796929A (en) | Junction isolated integrated circuit resistor with crystal damage near isolation junction | |
| US20020048875A1 (en) | Thin film transistors and methods of forming thin film transistors | |
| CN1238564A (en) | Insulated gate transistor, method of manufacturing same, and semiconductor integrated circuit device | |
| US4923824A (en) | Simplified method of fabricating lightly doped drain insulated gate field effect transistors | |
| JPH0786199A (en) | Method for manufacturing silicon carbide semiconductor device | |
| US6908859B2 (en) | Low leakage power transistor and method of forming | |
| JPH01196176A (en) | Mis type semiconductor device | |
| JPH0320022A (en) | Forming method for n-type diffused layer | |
| JPH03229427A (en) | Manufacture of mos-type semiconductor device | |
| JP3480500B2 (en) | Semiconductor element forming method | |
| JP2569809B2 (en) | Method for manufacturing semiconductor device | |
| JPH05175232A (en) | Thin film transistor and its manufacture | |
| JP2713122B2 (en) | Method for manufacturing semiconductor device | |
| JPS6358824A (en) | Manufacturing method of semiconductor device | |
| JP2002526944A (en) | Method for forming amorphous or polycrystalline layer on insulating region | |
| JPH0527273B2 (en) | ||
| JPH02219237A (en) | Mis type semiconductor device | |
| KR100231603B1 (en) | Manufacturing method for transistor of semiconductor device | |
| JP2926817B2 (en) | Method for manufacturing semiconductor device | |
| JPS5929425A (en) | Manufacture of semiconductor device | |
| JPH04179162A (en) | Semiconductor device and manufacture thereof | |
| JPS60195928A (en) | Manufacture of semiconductor device |