JPH0320086A - Manufacture of semiconductor storage device - Google Patents
Manufacture of semiconductor storage deviceInfo
- Publication number
- JPH0320086A JPH0320086A JP15539489A JP15539489A JPH0320086A JP H0320086 A JPH0320086 A JP H0320086A JP 15539489 A JP15539489 A JP 15539489A JP 15539489 A JP15539489 A JP 15539489A JP H0320086 A JPH0320086 A JP H0320086A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polycrystalline silicon
- layer
- oxide film
- tungsten silicide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000002844 melting Methods 0.000 claims abstract description 12
- 230000008018 melting Effects 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000000059 patterning Methods 0.000 claims abstract description 6
- 238000010438 heat treatment Methods 0.000 claims abstract description 4
- 238000009413 insulation Methods 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 18
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 abstract description 12
- 229910021342 tungsten silicide Inorganic materials 0.000 abstract description 12
- 239000005380 borophosphosilicate glass Substances 0.000 abstract description 7
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 abstract description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 2
- 239000001301 oxygen Substances 0.000 abstract description 2
- 229910052760 oxygen Inorganic materials 0.000 abstract description 2
- 238000001039 wet etching Methods 0.000 abstract description 2
- 238000005516 engineering process Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Landscapes
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、信頼性に優れた半導体記憶装置の製造方法に
関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a highly reliable semiconductor memory device.
従来の技術
従来より半導体記憶装置の一つとして、セルゲートにフ
ローティングゲートとコントロールゲートの2つのゲー
トを有し、フローティングゲート中に電子を注入し書き
込み状態を保持する不揮発性半導体記憶装置がよく知ら
れている。上記、記憶装置としてEFROMについての
製造方法について述べる。BACKGROUND OF THE INVENTION Conventionally, a nonvolatile semiconductor memory device has been well known as a type of semiconductor memory device, which has two gates, a floating gate and a control gate, in its cell gate, and maintains a written state by injecting electrons into the floating gate. ing. A manufacturing method for the above-mentioned EFROM as a storage device will be described.
第2図は従来の半導体記憶装置の製造工程断面図である
。以下、第2図を用いて従来の半導体記憶装置の製造方
法について説明する。FIG. 2 is a cross-sectional view of the manufacturing process of a conventional semiconductor memory device. A conventional method for manufacturing a semiconductor memory device will be described below with reference to FIG.
例えば、St基板21を酸化し厚膜の酸化膜22(0.
7μm程度)を形成した後、熱酸化膜23(3001程
度)を形成する。その後、CVD法によりフローティン
グゲートである第1層目の多結晶シリコン膜24(0.
3μm程度)を威長させ、次に不純物の拡散を行う。次
いで通常のりソグラフィ技術およびドライエッチング技
術を用いて所定の形状にパターニングする(第2図(a
))。For example, the St substrate 21 is oxidized and a thick oxide film 22 (0.
After forming a thermal oxide film 23 (about 3001 mm thick). Thereafter, the first layer of polycrystalline silicon film 24 (0.000.
(approximately 3 μm), and then impurity diffusion is performed. Next, it is patterned into a predetermined shape using ordinary lithography technology and dry etching technology (see Fig. 2(a)).
)).
次に高温熱酸化法により多結晶ポリシリコン膜24上に
熱酸化膜2−5を形成する(第2図(b))。Next, a thermal oxide film 2-5 is formed on the polycrystalline silicon film 24 by a high temperature thermal oxidation method (FIG. 2(b)).
次にCVD法によりコントロールゲートである第2層の
多結晶シリコン膜26(0.2μm程度)を成長させ、
次に不純物の拡散を行う。次いでCVD法により高融点
タングステンシリサイド膜27(0.25μm程度)を
成長させ、次いで通常のリングラフィ技術およびドライ
エッチング技術を用いて所定の形状にパターニングする
(第2図(C))。Next, a second layer of polycrystalline silicon film 26 (approximately 0.2 μm), which is a control gate, is grown using the CVD method.
Next, impurities are diffused. Next, a high melting point tungsten silicide film 27 (approximately 0.25 μm) is grown using the CVD method, and then patterned into a predetermined shape using ordinary phosphorography and dry etching techniques (FIG. 2(C)).
上記のように従来の半導体記憶装置では、フローティン
グゲートである第1層目の多結晶シリコン膜24を所定
の形状にパターニングした時に、その端部28が厚膜の
酸化膜22上に乗り上げて段差部を生じる。次にコント
ロールゲートである第2層目の多結晶シリコン膜26お
よび高融点タングステンシリサイド膜27を成長させた
際、第1層目の多結晶シリコン膜24の端部28が厚膜
の酸化膜22上に乗り上げて段差部を生じているため高
融点タングステンシリサイド膜27の密着性が悪化し、
第2層目の多結晶シリコン膜26と段差部において膜の
剥離31および32(第3図)を生じることがありパタ
ーン化が不可能となることがあった。As described above, in the conventional semiconductor memory device, when the first layer polycrystalline silicon film 24, which is a floating gate, is patterned into a predetermined shape, the end portion 28 rides on the thick oxide film 22, resulting in a step. produce part. Next, when the second layer polycrystalline silicon film 26 and the high melting point tungsten silicide film 27, which are control gates, are grown, the end portion 28 of the first layer polycrystalline silicon film 24 forms a thick oxide film 22. Because it rides on top and creates a stepped portion, the adhesion of the high melting point tungsten silicide film 27 deteriorates.
Peeling of the film 31 and 32 (FIG. 3) may occur at the step portion with respect to the second layer polycrystalline silicon film 26, making patterning impossible.
発明が解決しようとする課題
このように、上記従来の構成では、第2層目の多結晶シ
リコン膜と段差部において高融点タングステンシリサイ
ド膜の密着性が悪化し、膜の剥離を生じるという課題が
あった。Problems to be Solved by the Invention As described above, in the above-mentioned conventional configuration, the problem is that the adhesion between the second layer polycrystalline silicon film and the high melting point tungsten silicide film deteriorates at the stepped portion, resulting in peeling of the film. there were.
本発明は、上記従来の課題を解決するもので、第2層目
の多結晶シリコン膜と段差部における高融点タングステ
ンシリサイド膜の膜の剥離を防ぎ、信頼性の優れた半導
体記憶装置の製造方法を提供することを目的とする。The present invention solves the above-mentioned conventional problems, and is a method for manufacturing a semiconductor memory device with excellent reliability by preventing peeling of the second layer polycrystalline silicon film and the high melting point tungsten silicide film at the stepped portion. The purpose is to provide
課題を解決するための手段
この目的を達成するために、本発明は、フローティング
ゲート電極となる導電層を所定形状にバターニングした
後に、その端部が厚膜の酸化膜上に乗り上げた段差部を
平坦化するように熱溶融できる絶縁膜を形威し、次いで
熱処理により先の絶縁膜を溶融しかつフローティングゲ
ート電極となる導電層の上および半導体基板上にゲート
酸化膜を同時に形成し、段差部の平坦化を行なうように
したものである。Means for Solving the Problems In order to achieve this object, the present invention provides a structure in which a conductive layer that becomes a floating gate electrode is patterned into a predetermined shape, and then the end portion of the conductive layer rests on a thick oxide film. An insulating film that can be thermally melted is formed so as to flatten the surface, and then the previous insulating film is melted by heat treatment, and a gate oxide film is simultaneously formed on the conductive layer that will become the floating gate electrode and on the semiconductor substrate. This is to flatten the area.
作用
この構威によって、第2層目の多結晶シリコン膜と段差
部における高融点タングステンシリサイド膜の剥離を防
ぐことができる。Function: This structure can prevent the second layer polycrystalline silicon film from peeling off from the high melting point tungsten silicide film at the stepped portion.
実施例 以下実施例について、図面を参照しながら説明する。Example Examples will be described below with reference to the drawings.
第1図は本発明の一実施例における半導体記憶装置の製
造工程断面図である。まず、第1図(alに示すように
Si基板11の一主面を選択的に酸化し7000人のL
OGOS酸化膜12を形或する。FIG. 1 is a cross-sectional view of the manufacturing process of a semiconductor memory device according to an embodiment of the present invention. First, as shown in FIG. 1 (al), one main surface of the Si substrate 11 was selectively oxidized and
An OGOS oxide film 12 is formed.
その後300人のゲート酸化膜13を高温酸化雰囲気中
で形或し、次いでCVD法により3000Aの第1層目
の多結晶シリコン膜14を成長させ、次に不純物の拡散
を行う。次いでフォトリソグラフィ技術によりパターニ
ングを行い、反応性イオンエッチングにより所定の形状
にバターニンクスる。次に熱溶融できる絶縁膜として6
000人のBPSG膜15を常圧CVD法により成長さ
せ、フォトリングラフイ技術によりバターニングを行い
、ウエットエッチング(バツファードフツ酸液)により
段差部以外の部分を除去する。 次に第1図(b)に示
すように、酸素および水素ガスの高温酸化雰囲気中で熱
処理を行ない、BPSG膜15の熱溶融を行なうと同時
に第1層の多結晶シリコン膜14上およびSt基板上に
ゲート酸化膜16を同時に形成する。Thereafter, a gate oxide film 13 of 300 Å is formed in a high-temperature oxidizing atmosphere, and then a first layer polycrystalline silicon film 14 of 3000 Å is grown using the CVD method, and then impurities are diffused. Next, patterning is performed using photolithography technology, and butterninx is formed into a predetermined shape using reactive ion etching. Next, as an insulating film that can be thermally melted, 6
A BPSG film 15 of 0.0000000000000000000000000000 BPSG film 15 is grown by atmospheric pressure CVD method, patterned by photophosphorography technology, and portions other than the stepped portions are removed by wet etching (buffered hydrofluoric acid solution). Next, as shown in FIG. 1(b), a heat treatment is performed in a high-temperature oxidizing atmosphere of oxygen and hydrogen gas to thermally melt the BPSG film 15, and at the same time to melt the BPSG film 15 and the St substrate. A gate oxide film 16 is simultaneously formed thereon.
次に第1図(Clに示すように、CvD法により200
0Aの第2!ri目の多結晶シリコン膜17を成長させ
次に不純物の拡散を行う。次にCVD法により高融点タ
ングステンシリサイド膜18を2500人成長させ次い
でフォトリングラフィ技術によりバターニングを行ない
、反応性イオンエッチングにより所定の形状にバターニ
ングする。Next, as shown in Figure 1 (Cl), 200
2nd of 0A! An ri-th polycrystalline silicon film 17 is grown, and then impurities are diffused. Next, 2,500 high melting point tungsten silicide films 18 are grown using the CVD method, followed by patterning using photolithography and patterning into a predetermined shape using reactive ion etching.
発明の効果
本発明は、フローティングゲート電極となる導電層を所
定形状にバターニングした後にその端部が厚膜の酸化膜
上に乗り上げた段差部を平坦化することによって、コン
トロールゲート電極である高融点タングステンシリサイ
ド膜の膜の剥離を生じることを防ぎ、信頼性の優れた半
導体記憶装置を実現することができる。Effects of the Invention The present invention has been developed by patterning a conductive layer that will become a floating gate electrode into a predetermined shape and then flattening the stepped portion where the end of the conductive layer rests on a thick oxide film. It is possible to prevent the melting point tungsten silicide film from peeling off, and to realize a highly reliable semiconductor memory device.
第1図(a)〜(Clは本発明の一実施例を示す半導体
記憶装置の製造工程断面図、第2図(al〜(C)は従
来の一例を示す半導体記憶装置の製造工程断面図、第3
図は第2図(C)における拡大図(膜の剥離が生じてい
る図面)である。
11.21・・・・・・Si基板、12.22・・・・
・・LOCOS膜、13.23・・・・・・ゲート酸化
膜、14.24・・・・・・第1層目の多結晶シリコン
膜、15・・・・・・BPSG膜、16.25・・・・
・・ゲート酸化膜、17.26・・・・・・第2層目の
多結晶シリコン膜、18.27・・・・・・高融点タン
グステンシリサイド膜、28・・・・・・第1層目の多
結晶シリコン膜の端部、31.32・・・・・・段差部
における膜の剥離部分。FIGS. 1A to 1C are cross-sectional views of the manufacturing process of a semiconductor memory device showing an embodiment of the present invention, and FIGS. 2A to 2C are cross-sectional views of the manufacturing process of a semiconductor memory device showing an example of the conventional technology , 3rd
The figure is an enlarged view of FIG. 2(C) (a drawing in which peeling of the film has occurred). 11.21...Si substrate, 12.22...
...LOCOS film, 13.23... Gate oxide film, 14.24... First layer polycrystalline silicon film, 15... BPSG film, 16.25・・・・・・
... Gate oxide film, 17.26 ... Second layer polycrystalline silicon film, 18.27 ... High melting point tungsten silicide film, 28 ... First layer Edges of the polycrystalline silicon film, 31.32 . . . peeled portions of the film at step portions.
Claims (1)
ターニングした後にその端部が厚膜の酸化膜上に乗り上
げた段差部を平坦化するように熱溶融できる絶縁膜を形
成し、次いで熱処理により先の絶縁膜を溶融し、かつフ
ローティングゲート電極となる導電層の上および半導体
基板上にゲート酸化膜を同時に形成することを特徴とす
る半導体記憶装置の製造方法。After patterning the conductive layer that will become the floating gate electrode into a predetermined shape, an insulating film that can be thermally melted is formed so as to flatten the stepped portion where the end of the conductive layer rests on the thick oxide film, and then heat treatment is performed to remove the previous insulation film. 1. A method of manufacturing a semiconductor memory device, comprising melting a film and simultaneously forming a gate oxide film on a conductive layer that will become a floating gate electrode and on a semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15539489A JPH0320086A (en) | 1989-06-16 | 1989-06-16 | Manufacture of semiconductor storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15539489A JPH0320086A (en) | 1989-06-16 | 1989-06-16 | Manufacture of semiconductor storage device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0320086A true JPH0320086A (en) | 1991-01-29 |
Family
ID=15604997
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15539489A Pending JPH0320086A (en) | 1989-06-16 | 1989-06-16 | Manufacture of semiconductor storage device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0320086A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5934700A (en) * | 1996-03-08 | 1999-08-10 | Trw Occupant Restraint Systems Gmbh | Gas bag restraint module |
| AT507170A3 (en) * | 2008-08-04 | 2016-01-15 | Insinööritoimisto Oy Ricson Ab | ABSCHLÄMMANLAGE |
-
1989
- 1989-06-16 JP JP15539489A patent/JPH0320086A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5934700A (en) * | 1996-03-08 | 1999-08-10 | Trw Occupant Restraint Systems Gmbh | Gas bag restraint module |
| AT507170A3 (en) * | 2008-08-04 | 2016-01-15 | Insinööritoimisto Oy Ricson Ab | ABSCHLÄMMANLAGE |
| AT507170B1 (en) * | 2008-08-04 | 2016-02-15 | Insinööritoimisto Oy Ricson Ab | ABSCHLÄMMANLAGE |
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