JPH03201438A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an interlayer film having a good flatness without generating a crack by a method wherein prior to a process, in which a coat insulating film is subjected to baking and is vitrified, the insulating film is etched back until the thickness of the insulating film which stays in recessed parts becomes a thickness, in which no crack is generated in the insulating film even if the insulating film is vitrified. CONSTITUTION:An inorganic coat insulating film 15a containing silanol, or the like as its main component is formed on a lower silicon oxide film 15a by a spin coating method, for example, in such a way that recessed parts 20 formed in the surface of the film 15a are filled with the film 15b. After that, a baking is performed for several minutes at temperatures of 100 to 300 deg.C and solvents, such as alcohol and the like, are evaporated from the film 15b. Then, the film 15b is subjected to entire surface etchback by an isotropic dry ethcing method, in which the mixed gas of Freon, for example, and oxygen is used as reaction gas. After that, a baking is performed at a temperature of 400 deg.C or higher, for example, for stabilizing the film 15b by vitrifying. At this time, as the thickness t2 of the film 15b in the recessed parts 20 is 0.5mum or thinner, no crack is generated in the film 15b.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing an F conductor device having a multilayer wiring structure, and in particular, it has excellent crack resistance and
The present invention also relates to a method for manufacturing a semiconductor device with a multilayer wiring structure, which is improved so that an interlayer film with good flatness can be obtained.

[Conventional technology] As semiconductor devices become more highly integrated and multi-functional, multi-layer wiring technology is becoming more and more important in the future. .

FIG. 2 is a cross-sectional view of a memory cell portion of a dynamic random access memory (hereinafter abbreviated as DRAM) that has a conventional multilayer wiring structure. Note that this memory cell consists of one MOS transistor. and one capacitor, and the capacitor has a stacked
A structure called a capacitor is adopted, and by stacking
Efforts are being made to increase the capacity of fLi bonds by increasing their size. A field oxide film 2 is formed on a mound of p-type silicon cut plate 1 to separate the element -671 region from other element regions. A source 3 and a drain 4, which are n-type diffusion layers, are formed on the main surface of the active region of the silicon substrate 1. A gate 7 made of polycrystalline silicon is inserted through a gate oxide film 5 so as to span the source 3 and drain 4.
(N-channel type MOS transistor) 1, 1. will be accomplished. Gate electrode 6 functions as a word line. A silicon oxide film 7 as an interlayer film is formed to cover the gate 7u electrode 6. A contact hole 8 is formed in the silicon oxide film 7 to expose the surface of the drain 4. A storage node 9 made of silicon is connected to the drain 4 through a contact hole 8 . A high dielectric constant film made of silicon nitride film extends over the storage node 9]0
is provided. Further, a cell layer i11 is provided so as to run over the high J8 electric conductor film 10, and a stacked capacitor t111' is formed. A smooth coat film 12 is coated on the gold mine so as to cover the cell bullet 11. The smooth coat film 12 and silicon oxide film 7 include
Contact hole 1 for exposing the surface of source 3
3 is formed. A lower aluminum film 14 serving as a bit line is formed on the smooth source 1-11Z 12, and the aluminum film 14 is connected to the source 3 via a contact hole]3. An upper interlayer rim film 15 is formed on the lower aluminum film 14. An upper aluminum film 16 is formed on the upper living room film 15. A pudgecon film 17 is formed on the gold mine so as to cover the upper aluminum film 16.

Next, the horizontal extension of the interlayer film 15 will be explained in more detail with reference to FIG.

FIG. 3 is a cross-sectional view taken along the l[l-l11 gland in FIG. 2.

Refer to the third garden.
An interlayer 11K 18 of the dots 114 is formed. On the surface of the smooth coat film 12, a wiring pattern of a layer of aluminum film]4 is formed.

An upper interlayer film 15 is provided so as to cover the wiring pattern of the aluminum film 14. The upper interlayer film 15 is
A lower jφ silicon oxide film 15a is provided so as to cover the wiring pattern of the aluminum film 14, and a coated insulating film is provided on the silicon oxide film 15a so as to fill the four parts formed on the surface of the silicon oxide film 15a. 15b, and an upper layer silicon oxide film 15c provided on the coated 1i insulating film 15b. Upper living room membrane 1
5, an upper aluminum film 16 is formed, and a passivation film 17 is formed to cover the aluminum film 16.
is formed. The upper interlayer film 15 has sufficient A11-] properties or poor properties in order to make the patterning properties and wiring reliability of the upper aluminum film 16 formed thereon good (Ij'). For this purpose, the upper interlayer film 15 has the above-mentioned structure.

Next, the formation process of the upper layer interlayer film 15 of the above-mentioned product 1ffl +i"-1 will be explained with reference to FIGS. 4AJ to 4D.
1. I will explain.

Referring to Figure 1i4A, a lower interlayer film 18 (of a predetermined thickness), which is a silicon oxide film, is formed on silicon u and tlN1 (
Gate oxide film 6 + silicon oxide film 7 + smooth coat film 1
2) is formed by CVD method.

Next, a lower aluminum film 14 having a thickness of 5000 to 7000 A is formed on the lower interlayer film 18 by, for example, sputtering. Thereafter, a positive resist, for example, is applied onto the lower aluminum film 4 and patterned by photolithography to form a resist pattern (not shown). Using this resist pattern as a mask, for example, reactive ion etching (RIE) is performed to remove the underlying aluminum film 14.
By selectively etching, one wiring pattern of the aluminum film 14 is formed (three wiring patterns are shown in the drawing).

Next, referring to FIG. 4B, a lower silicon oxide film 15a of a predetermined thickness is formed on the lower interlayer film 18 so as to cover the wiring pattern 19.

The silicon oxide film 15a is formed by thermal CVD7A or plasma CVD.
Silane (Si
It is formed using a mixture gas of B6) and oxygen (02) or an at mixture gas of silane and dish nitrogen oxide (N20) as a reaction gas. At this time, the back ridge of the silicon oxide film 15a of the layer is depressed between the wiring pattern 19 and one wiring pattern. That is, four portions 20 are formed on the surface of the lower silicon oxide film 15a.

Next, referring to FIG. 4C, the lower silicon oxide film 15
Inorganic 9 containing silanol (S i (OH) s ) ''-da as a main component is applied onto the silicon oxide film 1'5a by, for example, a four-roll coating method so as to fill the four parts 20 that have come to the surface of the silicon oxide film 1'5a. (+j 81 Form the edge film 15b.

Thereafter, baking is performed at a temperature of 100 to 300°C for several minutes to evaporate the solvents such as alcohol and q- from the applied insulating film 15b. Next, baking is performed at a temperature of 400°C or higher, for example, to remove the coating. Baking the insulating film 15b,
Make it a foothold. Thus, the superficial flattening is destroyed.

Next, referring to No. 4D-, the silicon oxide film 15b is coated with a predetermined thickness of 1 on the entire upper surface of the applied insulating film 15b by the same method as in the formation of the silicon oxide film 15a of the second layer. Membrane 1
Form 5c. Note that the film 1 of the upper interlayer film 15 is 8,000 to 10,000Af on the aluminum wiring 14.
It is Ju degree.

[24 Problems to be Solved by the Invention] The conventional manufacturing method for the lower If interlayer film 15 was as described above (14). But the cow came.

That is, as the wiring becomes finer and the wiring spacing becomes narrower to the submicron range, the thickness t of the coated rim film 15b accumulates in the four parts 20 between the wiring patterns 19, as shown in FIG. becomes larger, and crack 21 occurs in subsequent betas. This is due to the fact that the applied insulating film 15b undergoes a large external shrinkage when it is kept at a bake temperature of 400°C or higher.For example, silanol (Si(O
H) In the case of a coated insulating film 15b whose main component is 4), cracks 21 occur if the thickness exceeds 0.05 μm.
is complete! 1 step easier.

In this way, if a crack 21 occurs in the coated insulating film 15b, when the upper silicon oxide film 15C is deposited thereon, the shape of the base is reflected and the 4;-++1 property of the upper silicon oxide film 15c is changed. becomes worse.

As a result, as shown in FIG. 6, the upper layer aluminum film 16 may be disconnected, causing
It has a big impact on sexuality.

This invention was made to solve the above-mentioned problems, and includes an improved multilayer wiring structure that provides an interlayer film with excellent crack resistance and good flatness.゛1 We agree to share the manufacturing method for the conductor A.

[Means for resolving the problem] According to the method of manufacturing a semiconductor device for multi-layer wiring HLT according to the present invention, first, half of 9 pieces! A wiring pattern is formed on the L temporary. An insulating film is formed on the clay semiconductor substrate to cover the wiring pattern.

A coating insulating film containing a solvent is applied onto the insulating film so as to fill the four parts formed on the surface of the insulating film.

After that, the solvent is evaporated from the applied insulating film. Next, apply O
The thickness of the applied insulating film accumulated in the four parts of the i insulating film is
Until it reaches a thickness that will not cause cracks even after baking.
Have sex back. Thereafter, the applied insulating film is baked to harden it.

[Function] According to the present invention, 9 (+i
Since the B edge film is etched back until the thickness of the insulating film accumulated in the four parts becomes a thickness that does not cause cracks even when baked, an interlayer film having good flatness can be obtained without causing cracks.

[Length example] Hereinafter, an embodiment of the present invention will be explained with reference to the drawings.

FIGS. 1A to 1F are construction diagrams of an embodiment of the present invention, and are represented by section i1J.

Referring to the first Ald, the lower interlayer film 18 is formed on the silicon overboard 1. The method for forming the lower interlayer film 18 is as described in the explanation of FIG. 4A. Therefore, a detailed explanation will be omitted.

Next, on the lower interlayer film 18, a lower aluminum film 14 with a film thickness of about 5000 to 7 (10,4) is formed by, for example, sputtering. Next, by the method described above, 7' One wiring pattern of the aluminum film 14 is formed.

Next, referring to FIG. 1B, a silicon oxide film 15a of a predetermined layer +y is formed on the lower layer Ii'i interlayer 18 so as to cover the wiring pattern 19.

silicon oxide film], 5 a is 1. +A CVD method or plasma CVD method at 300-450'C is a reading gas of silane (S lH4) and oxygen (02) or silane! ■1llJ 'N of nitrogen oxide CN20)
It is formed using a gas as a reactant gas. At this time, lower j□
The surface of the Schifcon oxide film 15a of □□ is the wiring pattern 1
and wiring pattern] 9. That is,
Silicon oxide 1i% on the bottom j □□□ The surface of 15a is r
A U1 portion 20 is formed.

Next, referring to FIG. 1C, the lower silicon oxide film 1'
An inorganic coating (1i An insulating film 15b is formed.

Thereafter, baking is performed at a temperature of 100 to 300° C. for several minutes to evaporate the alcohol-based agent from the applied insulating film 15b. At this time, the applied insulating film 15b accumulates on the four parts 20.
The film thickness t may exceed 0.5 μm.

Next, referring to the first DII, the coated insulating film 15b is coated with, for example, 'lJA' of freon (CI?4) and oxygen (02).
The entire surface is etched back by an isotropic dry etching method using '6 gas as a reaction gas. This etch hack is for recess 20/l? The thickness t2 of the coated insulating film 15b is
This is done until the thickness is such that no cracks will occur even if it is baked (in this case, p, 1' thickness not exceeding 0.5 .mu.n1). In this case, when the etching rate of the coated VHi insulating film 15b is 50 to 1000 A/min, it is possible to etch back with good controllability. Then, baking is performed at a temperature of, for example, 400° C. or higher.At this time, since t2 is 0°5 μI11 or lower, no cracks occur in the coated insulating film 15b as in the conventional case.

Next, referring to FIG. 1E, an upper silicon oxide film 15c having a given thickness is formed on the entire upper surface of the silicon plate 1 including the applied insulating film 15b.

The silicon oxide film 15c is formed by thermal CVD method or plasma CVD method.
/A from 300 to 450℃ by method! Silane (Si)
It is formed using a flood gas of H<) and oxygen (02) or a flood gas of silane and dish nitrogen oxide (N20) as the reaction gas. The thickness of the upper f4 interlayer film 15 consisting of the lower silicon oxide film 15a, the coated insulating film 15b, and the upper silicon oxide film 1'5c is the same as that of the lower aluminum film 14.
Above that, about 8000 to 100 OOA is dangerous. In this way, the official use of cattle is carried out.

Next, referring to FIG. 1F (14), an upper aluminum film 16 is placed on top of the upper interlayer film 15.

Thereafter, a full-surface nipassivation film 7 is formed so as to cover the upper aluminum film 6.

In the above embodiment, the lower silicon oxide film 15a and the upper silicon oxide film 15c are formed by thermal CVD or plasma CVD, but they may be formed by other methods.

Furthermore, in the above embodiment, silanol (
Inorganic coating 1' whose main component is S i (OH) 4)
Although the Ii insulating film is shown as an example, the same effect can be obtained with other coated '6'i insulating films such as the Iki-coated 11i insulating film or the silicon ladder polymer.

Further, in the above embodiments, aluminum is used as the lower interconnection film and the upper interconnection film, but the present invention is not limited to this. and other high melting point metals and their silicides (WSi2.MoSi2.Ti5i
2) Alternatively, a similar effect can be achieved using polycrystalline silicon wiring.

In addition, although the above-mentioned embodiment describes a wiring film that has two layers, the present invention is not limited to this, and can be applied to a case where the wiring film is further multilayered.

[Effects of the Invention] As explained above, according to the present invention, prior to the step of baking the applied insulating film,
Coating (etching back the color border film until the thickness of the coating N1 insulation film that accumulates on the four parts becomes a thickness that will not cause cracks even when baked, followed by baking to expose and stabilize the coated insulation film) Since I tried to do this, I could maintain a good palm pattern (j-I<4) without causing any cracks.
The interlayer is rubbed, and as a result, it becomes possible to create submicron-level wiring patterns. Therefore, the stability of patterning is improved, and it is possible to form highly reliable wiring that does not cause disconnections or the like. As a result, it is possible to obtain an F''9-body device capable of drawing multilayer wiring with high reliability.

4. Explanation of the drawings Figures 1A to 1F are construction drawings of a method for manufacturing a 19-body device with a multilayer wiring diagram for one-dog care according to the present invention. , Itli dm diagram.

FIG. 2 shows a conventional DRA in which the multilayer wiring tVIa is -G.
FIG. 3 is a cross-sectional view of a memory cell portion of M.

FIG. 3 is a sectional view taken along line III-m in FIG. 2.

FIGS. 4A to 4D show the process of forming the 11% intercostal space in the upper layer of the conventional semiconductor device shown in FIG. 3, and are shown in cross-sectional views.

FIGS. 5 and 6 are diagrams showing problems in the conventional interlayer IL+ forming method.

In the figure, 1 is a silicon-like plate, 15a is a lower layer silicon oxide film, 15b is a '1=I'Iiii color border film, 15c is an upper layer silicon oxide film, 1 is a wiring pattern, 20 is a recess, and t2 is a recess. The thickness of the applied insulating film remains at .

In each figure, the same initial number indicates the same or corresponding part.

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Claims (1)

[Claims] A step of forming a wiring pattern on a semiconductor substrate, a step of forming an insulating film on the semiconductor substrate so as to cover the wiring pattern, and filling a recess formed on the surface of the insulating film. The steps include: applying a coated insulating film containing a solvent on the insulating film; evaporating the solvent from the coated insulating film; , a step of etching back the applied insulating film to a thickness that does not cause cracks even when baked, and a step of baking the applied insulating film by baking the applied insulating film. Production method.