JPH03201537A - Manufacturing method of thin film transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a thin film transistor, and more particularly, to a method for manufacturing a transistor having a blocking layer for preventing damage and contamination of the active layer (channel region) during manufacturing. , for example, relates to a technique effective for use in the manufacturing process of inverted stagger type thin film transistors.

[Prior Art] There is a simple matrix type liquid crystal display device used in liquid crystal televisions and the like. However, the simple matrix type has limitations in achieving high contrast and high time-division driving. Therefore, an active matrix type is developed, which adds and integrates a switch element and, if necessary, a capacitor element for each pixel at the matrix intersection of the scanning electrode and the signal electrode, in order to improve display performance such as contrast and response speed. It is starting to be used. In particular, among three-terminal switch elements, those using thin film transistors can operate at low voltages, are highly compatible with C-MO3ICs, and have the potential to incorporate peripheral circuits on the same substrate. From Kotona etc., I want to become a barista or MIM in the future.
It is thought that it will become mainstream, surpassing the two-terminal nonlinear elements such as.

Structures such as a staggered type, an inverted staggered type, a coplanar type, and an inverted staggered type have been proposed for thin film transistors.

Among these, in the inverted stagger type thin film transistor, a gate electrode is formed on a glass substrate, a semiconductor layer that becomes an active layer is placed on top of the gate electrode via an insulating film, and a contact layer and source and drain electrodes are placed on top of this semiconductor layer! This is a structure with poles formed.

In manufacturing this inverted stagger type thin film transistor,
This method has the disadvantage that the surface of the active layer, which directly affects the characteristics of the device, may be damaged or contaminated by etching during patterning of the contact layer and source and drain electrodes, resulting in deterioration of the characteristics of the device.

Therefore, a technique has been developed in which a blocking layer made of an insulating film is provided above the region that will become the channel part of the active layer to prevent damage and contamination of the channel part during patterning of the contact layer and source and drain electrodes. Proposed.

Hereinafter, the structure and manufacturing method of a conventionally proposed inverted staggered thin film transistor having a blocking layer will be briefly described with reference to FIG.

First, an aluminum layer 2 is formed on a glass substrate 1 by sputtering and patterned to form a gate electrode 2a.
(Fig. 2(A)). Then, a SiNx film 3 that will become a gate insulating film, a semiconductor layer 4 such as non-doped amorphous silicon that will become an active layer, and a second SiNx film 5 that will become a blocking layer are successively deposited (see Fig. 2 (B).
)).

Next, the second SiNxjJj5 is etched using a resist as a mask using a photolithography technique.
A blocking layer 5a is patterned above the gate electrode 2a (FIG. 2(C)).

After that, the n-type amorphous silicon layer 6 that will become the contact layer and the aluminum layer 7 that will become the source and drain electrodes are shaped (Fig. 2 (D)), and the aluminum layer 7 and the n-type amorphous silicon layer 6 are formed to separate the source and drain. Etch layer 6 to form source and drain electrodes [77
contact layers 6a, 6b were formed with a, 7 and b (
Figure 2 (E)). In the above process, the semiconductor layer 4
Since the blocking layer 5a is provided on top of the source,
It is possible to protect the channel portion of the semiconductor layer 4 from the etching liquid or etching gas for separating the drain, thereby preventing deterioration of device characteristics due to damage or contamination.

[Problem to be Solved by the Invention] However, in the conventional process shown in FIGS. 2(A) to 2(E), the channel length is determined by the length of the blocking layer 5a, considering the accuracy of mask alignment. It must be designed to be larger than the minimum processing dimension a by the process by 2b (b+b), which is the margin for mask alignment. The channel length in this case is 6-7 μm. As a result, there are problems in that the element size becomes large, the on-current of the manufactured thin film transistor is small, and the switching speed is also slow.

An object of the present invention is to reduce the element size of a thin film transistor having a blocking layer and to improve the characteristics of the transistor.

[Means for Solving the Problems] In order to achieve the above object, the present invention includes a step of forming a gate electrode on a glass substrate, and subsequently forming an insulating film, a semiconductor layer, a second insulating film, and a metal layer thereon. a step of etching the metal layer and the second insulating film and subsequently depositing an n-type amorphous silicon and aluminum layer; and a lift-off method to remove the metal layer and the silicon and aluminum layers thereon. This process consists of simultaneously removing the contact layer and forming the source and drain electrodes.

[Operation] According to the above-described means, the source and drain electrodes and the contact layer are formed in a self-aligned manner with respect to the blocking layer, so there is no need for mask alignment margin between the blocking layer and the source and drain electrodes, The length of the blocking layer, ie the channel length, can be shortened.

Additionally, if the blocking layer is over-etched in the lateral direction during etching, when the n-type amorphous silicon that will become the contact layer and the aluminum layer that will become the source and drain electrodes are deposited, the sidewalls of the blocking layer will be covered with silicon. This creates constrictions and gaps in the metal layer and the aluminum layer, making it easier to peel off the metal layer using the lift-off method.

[Example 1] FIG. 1 shows an example in which the present invention is applied to the process of an inverted stagger type thin film transistor in the order of steps.

In this embodiment, first, a conductive layer 2 made of aluminum is deposited on an insulating substrate l such as a glass substrate by sputtering, and the conductive layer 2 is etched using a resist as a mask using photolithography to form a desired pattern. A shaped gate electrode 2a is formed.

Next, an insulating film 3 such as a SiNx film, a semiconductor layer 4 of non-doped amorphous silicon, and a second insulating film 5 such as an SiNx film serving as a blocking layer are sequentially formed on the gate electrode [j2a by plasma CVD method or the like. Further, a metal layer 8 of Cr or the like is deposited thereon by, for example, sputtering (FIG. 1(B)).

Then, using the resist as a mask, the metal layer 8 is patterned into a desired shape by wet etching or dry etching, and the second insulating film 5 underneath is etched using the patterned metal layer 8a as a mask to form the blocking layer 5a. (Fig. 1(C)). In this embodiment, the second insulating film 5 is etched by, for example, wet etching or plasma etching, so that the second alveolar film 5 is laterally overetched to form an eaves at the end of the metal layer 8a. I have to.

Next, a contact layer 6 of n-type amorphous silicon is deposited by plasma CVD, and a conductive layer 7 of aluminum or the like is deposited thereon by sputtering. Then, a constriction or a gap is generated between the contact layer 6 and the conductive layer 7 at the side wall portion of the blocking layer 5a (FIG. 1(D)).

Next, wet etching is performed on the second insulating film 5 using an etchant (if the insulating film 5 is made of Cr, a mixed solution of ceric ammonium nitrate, perchloric acid, and water). Then, the etchant percolates from the constriction of the contact layer 6 and etches the metal layer 8a, and the n-type amorphous silicon and aluminum thereon are simultaneously removed by the lift-off effect, and the contact layer 6 and the conductive layer 7 are separated. , source and drain regions 6a
, 6b and source and drain electrodes 117a.

7b is formed (FIG. 1(E)).

In the above embodiment, after a gate electrode is formed on a glass substrate, an insulating film, a semiconductor layer, a second insulating film, and a metal layer such as Cr are successively deposited thereon.
After etching the insulating film, the n-type amorphous silicon and aluminum layers are successively deposited, and the metal layer and the silicon and aluminum layers above it are simultaneously removed using a lift-off method, and then the contact layer and source and drain electrodes are formed. Since the source and drain electrodes and the contact layer are formed in a self-aligned manner with respect to the blocking layer, there is no need for a margin for mask alignment between the blocking layer and the source and drain electrodes. As a result, in the conventional inverted staggered transistor, the channel length must be made larger by the mask alignment margin than the minimum processing dimension of the process, so the channel length was 6 to 7 μm. By applying this, the channel length can be made the same as the minimum processing dimension of the process (for example, 3 μm). As a result, the element size of the transistor can be reduced, the on-state current can be increased, and the switching speed can be improved.

Furthermore, in the above embodiment, when etching the blocking layer, the width of the blocking layer is made smaller than the width of the metal layer above it by over-etching it in the lateral direction, so that an eaves of the metal layer remains. Therefore, when n-type amorphous silicon, which will become a contact layer, and aluminum layers, which will become source and drain electrodes, are deposited, constrictions and gaps will occur in the silicon layer and aluminum layer at the sidewalls of the blocking layer, and metal removal using the lift-off method will occur. This has the effect of making it easier to peel off the layers.

In the above embodiment, the blocking layer 5a is over-etched in the lateral direction so that an eaves can be formed in the metal layer 8a, but it is not necessarily necessary to over-etch the metal layer 8a. In that case, before lifting off the metal layer 8a with an etchant, wet etching may be performed lightly with an etchant for aluminum or silicon, and then wet etching with the etchant may be performed on the metal layer 8a.

Further, in the above embodiment, C is used as the metal layer 8 to be lifted off.
Although r is used, the present invention is not limited thereto, and any material may be used as long as it has a high selectivity with respect to the material of the blocking layer 5a. For example, when C and r are used instead of aluminum for the conductive layer 7 forming the # film transistors 7a and 7b, aluminum can be used instead of Cr for the metal layer 8. In that case,
Lift-off can be easily achieved by using an alkaline solution as an etchant.

Further, the materials used for the insulating film 3.5, the semiconductor layer 4, the gate electrode 2a, etc. used in the above embodiments are just examples, and it goes without saying that other materials having the same or similar properties can be used. do not have.

[Effects of the Invention J As explained above, the present invention makes it possible to shorten the channel length of a thin film transistor having a blocking layer, thereby reducing the device size, enabling high integration, and reducing the on-state current of the transistor. This has the effect of increasing the switching speed and increasing the switching speed.

[Brief explanation of drawings]

FIGS. 1(A) to (E) are cross-sectional views showing an embodiment of the present invention applied to the process of an inverted stagger type thin film transistor in the order of steps, and FIGS. 2(A) to (E) are cross-sectional views showing a conventional blocking layer. FIG. 3 is a cross-sectional view illustrating an example of a method for manufacturing an inverted staggered thin film transistor. l...substrate, 2a...gate electrode, 3...
Gate insulating film, 4... semiconductor layer, 5a... blocking layer, 6... contact layer, 7a, 7b...
...Source and drain electrodes. Figure l

Claims (2)

[Claims] (1) A step of forming a gate electrode on an insulating substrate, a step of successively depositing an insulating film, a semiconductor layer, a second insulating film, and a metal layer thereon, and a step of depositing the above metal layer and the second insulating film. After etching to form a desired shape, a contact layer and a conductive layer are sequentially deposited, and a lift-off method is used to simultaneously remove a portion of the metal layer, contact layer, and conductive layer to form a source, drain region, and the like. A method for manufacturing a thin film transistor, comprising the steps of forming source and drain electrodes. (2) The method for manufacturing a thin film transistor according to claim 1, wherein the second insulating film is etched by wet etching or plasma etching.