JPH03201542A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce series resistance and improve high frequency characteristics of an FET by providing an electrode coating metal layer which is partially laminated on an electrode base and fills a slit between counter faces of the electrode base and an insulation film. CONSTITUTION:Adjacent to an insulation film is made of SiO2 on the upper face of a semi-insulating substrate 20, a source electrode 21S and a drain electrode 21d of specific patterns are laminated with an electrode base layer is on a part of the electrode base layer 15, and an electrode coating metal layer 18 for filling a slit between counter faces of the side walls of the layer 15 and the insulation film 16 is formed. On an n-layer 14, an opening is made on a part of an oxide film 16 coating the layer 14 wherein a gate electrode 19 comprising titanium and aluminum as examples is provided in the opening. Since the metal layer 18 is provided in the periphery of the electrode, an electrode contact area is increased, series resistance Rs between the source and the gate is reduced and high frequency characteristics are improved. Since the metal layer is applied on a surface of electrode metal, adhesion is improved with respect to bonding using metal wires and by selecting plate metal an effect as a GaAs surface protection film even against the atmosphere can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device with an improved electrode structure.

(Prior Art) In recent years, as the range of applications of gallium arsenide Schottky junction field effect transistors (hereinafter abbreviated as GaAs FETs) has expanded, improving their performance has become even more important.

As shown in FIG. 4(a), in the manufacturing process of GaAs FETs used in particular in the microwave band, a pattern is usually formed on a semi-insulating substrate 101 by photolithography (hereinafter referred to as PEP). via an insulating film 102 made of 5in2.

Si ions are implanted using an ion implanter and an annealing process is performed to form an N+ layer 103 and an N layer 104.

Next, after PEP, the N1 layer 103 is made of gold-germanium alloy/
A source and train electrode metal layer 105 made of platinum is deposited, and unnecessary portions are removed by lift-off, followed by heat treatment for alloying in a hydrogen furnace to form source and drain electrodes. Then, an insulating film 102 between the source and the train
A pattern for forming a gate electrode is opened using PEP,
Titanium/aluminum is evaporated and a finely structured gate electrode 106 is formed by lift-off to complete the GaAs FET.

The electrode dimensions of small signal GaAs FEETs for microwave bands (e.g. about 4 to 18 GHz) are 3 to 4 p between the source and drain electrodes, approximately 1 gn between the gate and source electrodes, and approximately 1 gn between the gate and source electrodes in order to achieve high frequency characteristics. length is 0.3~0
．． It has an extremely small size of 5/a.

However, when looking microscopically at the source and train electrode parts of the GaAs FET manufactured in this way, Fig. 4(b) shows an enlarged view of the part bent by the broken circle in Fig. 4(a). As shown, the source/drain electrode metal layer 105 is melted during the heat treatment for alloying, and during the subsequent cooling process, due to the contraction effect due to the surface tension peculiar to the metal film, the shape of the electrode after cooling shows that the electrode is fully bent. Gap 10 between oxidized IE1i window
7, and the state in which the electrode fills the window of the oxide film cannot be reproduced. Up to now, various gold electrodes have been selected and experiments have been attempted, but at present, an appropriate constituent gold ρC has not been determined.

(Problem to be solved by the invention) In a GaAs FET, its high frequency characteristics are determined by the source,
The static capacitance (Cx-) between the gates and the series resistance (R
, ) is a numerical value fr expressed as the reciprocal of the product (the following formula (1)
)% formula % (1), and in order to obtain the desired characteristics, C1a
It is essential to keep R8 small. Capacitance C
In order to reduce ff1s, it is common to shorten the gate length as much as possible. Also, the series resistance R.

For this purpose, attempts have been made to shorten the source-gate interval and introduce an N+ layer on the N layer, but these measures also have certain limitations because the gate-source withstand voltage cannot be ensured. On the other hand, there was a fundamental defect in that the series resistance was not reduced because the contact resistance of the electrodes was not reduced, making it difficult to improve the characteristics.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device manufacturing method for manufacturing an electrode structure for reducing this series resistance and improving the high frequency characteristics of an FET by eliminating the gap between the source and drain electrodes. do.

[Structure of the Invention &] (Means for Solving the Problems) A semiconductor device according to the present invention includes an electrode and an insulating film in a predetermined pattern formed adjacent to a surface of a semiconductor substrate, wherein the electrode is , an electrode base layer having an alloy layer with the semiconductor substrate on the side facing the semiconductor substrate; and an electrode coating partially laminated on the electrode base and filling the space between the electrode base and the insulating film facing each other. It is characterized by comprising a metal layer.

Since the contact resistance is reduced by increasing the electrode area, the series resistance is reduced, and as a result, the high frequency characteristics of the semiconductor device are improved.

(Function) The present invention embeds metal in the non-alloyed part (GaAs surface) generated in the circumference of the gold electrode bending part by the above-mentioned heat treatment.
% By increasing the contact area, GaAs FI
The source-gate series resistance of the ET is reduced, and high frequency characteristics are improved. In the above description, GaAs is consistently mentioned among compound semiconductors that have a great advantage in operating speed as a semiconductor material. however,
This does not limit the materials used in the present invention, and the present invention can be applied to a wide range of general semiconductor materials, such as elemental semiconductors such as Si and Ge, and other compound semiconductors.

(Example) Hereinafter, GaAs? of one example of the present invention will be described. An example of an Ii field effect transistor (GaAs FET) will be described with reference to FIG. 1, which shows its structure in cross-sectional view, and FIG. 2, which shows its manufacturing method in order of steps.

In the GaAs FET shown in FIG.
4. Electrodes 18, 19, etc. are formed on this main surface, and a lower surface electrode 22 is formed on the other main surface (lower surface).

Further, on the upper surface of the semi-insulating substrate 20, a source electrode 21S and a drain electrode 21d in a predetermined pattern are formed on the n+ layer 13 adjacent to the insulating film 16 made of SiO□.
An electrode base Its made of an alloy of germanium/platinum) is partially laminated on this electrode base layer 15, and its side surface and an insulating film 1 are laminated on the electrode base layer 15.
It is formed of an electrode covering metal layer 18 that fills the space between the opposing surfaces of the electrode 6 and the electrode 6. Furthermore, an opening is formed in a part of the oxide film 16 covering the 0 layer 14, and a gate electrode 19 made of titanium and aluminum, for example, is provided in the opening. Note that, as an example, a lower surface electrode 22 made of gold is formed on the lower surface of the semi-insulating substrate 20.

Next, the method for manufacturing the above GaAs FET is shown in Fig. 2(a).
This will be explained by (f).

Mirror-finished semi-insulating substrate I with crystal axis <100)
After etching O with a tartaric acid etchant, an insulating film 30 of 5 in 2 is deposited on the upper surface by thermal decomposition of silane to a thickness of 4000 Å.

(Figure 2(a)).

Next, a photo etching process (hereinafter abbreviated as PEP)
Openings are then made in the insulating film 30 in areas where the source and drain electrodes are to be formed, and ions are implanted into the semi-insulating substrate exposed here. This ion implantation.

Implant with an ion implanter at an acceleration voltage of 120 keV and a dose of 2 x 1013 cm (Figure 2 (b))
.

The insulating film 40 is deposited again, an opening is made in this insulating film by PEP in the area where the N layer is to be formed on the semi-insulating substrate, and the Si
Ions were accelerated at a voltage of 50 keV and a dose of &5×101
Type in the conditions of 2CI11-2. Thereafter, in order to activate the implanted Si ions, the semi-insulating substrate was subjected to an activation treatment at 850°C for 15 minutes in arsenic gas, and the N+
Layer 13 and N layer 14 are formed (second layer (C)).

Next, holes were opened in the oxide film on the surface of the N+ layer 13 to form sources and drains, and gold/germanium (12% by weight) was deposited at 2000λ, followed by platinum at 200A.
After removing unnecessary parts by lift-off, heat at 400℃ in a hydrogen furnace for 5 minutes.
Heat treatment is performed for a minute (FIG. 2(d)). At this time, a gap 17 is generated around the electrode base layer 15.

In order to fill the exposed portion of GaAs on the surface of the N4 layer 14 in the gap 17 caused by the shrinkage of the electrode base layer (gold/germanium/platinum alloy) 15 due to the heat treatment, electroless gold plating was applied at a temperature of 60°C. The electrode coating metal layer 18 was formed by applying the coating for 15 minutes. This plating has a layer thickness of approximately 15
00λ was applied (FIG. 2(e)).

Next, after photoetching an opening in the oxide film in the area where the gate electrode is to be formed using ammonium fluoride, a titanium layer is formed with a thickness of 200A, and an aluminum layer is formed with a thickness of 5000A.
After this vapor deposition, unnecessary portions are removed by lift-off, and the electrode formation on the active layer side is completed.

Finally, in order to thin the semi-insulating substrate to an appropriate thickness (approximately 100p), the back surface was wrapped with No. 3000 emery powder, and then sulfuric acid: hydrogen peroxide: water (8:1:1
) using an etchant at a temperature of 50.degree. C. for about 3 minutes, and then a gold layer with a thickness of 3000 nm is deposited as the lower electrode 22. Next, in order to improve the adhesion with the semi-insulating substrate around the entire circumference, heat treatment is performed at 300° C. for 10 minutes, completing the 12-step fabrication process of the GaAs electrode effect transistor (FIG. 2(f)).

In this embodiment, gold is used as the plating metal. The plated metal around the electrode forms a Schottky junction with the N+ layer, but because the N+ phantom carrier concentration is sufficiently high, the barrier that occurs is low, and it essentially forms an ohmic contact. There is no problem in thinking that. Also, N
Even if diffusion into one layer occurs, it acts as a donor, so it also has the advantage of further reducing the series resistance.

Next, in order to compare the high frequency characteristics, the completed GaAs
After scribing the FET, mount it in a small signal envelope,
GaAs FE with similar shape made by conventional method
Noise figure NF in T and 12GIIz band and 18GIIz band
Measurements were made. The results are shown in FIG. As is clear from the figure, compared to the conventional product, it is approximately 0.1 to 0.15 dB.
It was demonstrated that the degree of improvement was achieved. This example shows an example in which a gold plating layer is formed in the vicinity of an ohmic electrode metal that shrinks during alloying; however, due to the characteristics of the electroless plating solution, it is not affected by the semiconductor material.

Of course, the present invention can also be applied to other similar semiconductor materials.

〔Effect of the invention〕

As described above, the present invention has the following advantages.

(i) Since a metal layer is provided around the electrode to cover it, the electrode contact area is expanded, thereby reducing the series resistance R3 between the source and the gate, and improving high frequency characteristics.

0) Since the surface of the electrode metal is also coated with a metal layer, it has the effect of improving adhesion for bonding using gold wire performed in a subsequent process.

(i) The effect as a GaAs surface protective film can be obtained by selecting a plating metal even when exposed to the outside air.

0) By appropriately using PEP masks, it is possible to color each electrode according to the plating metal, which simplifies the assembly operation.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a GaAs FET according to an embodiment of the present invention, FIGS. 2(a) to (f) are cross-sectional views showing the method for manufacturing the FET shown in FIG. 1 in order of steps, and FIG. is FE
A diagram for explaining one embodiment of the high frequency characteristics of T, FIG. 4(a) is a cross-sectional view showing a conventional example of GaAs FET, and FIG. 4(b) is a cross-sectional view showing a part of (a) enlarged. It is a diagram. 13.n layer, 14...°n layer, 15...electrode base layer, 16...insulating film, I8...electrode coating metal layer, 1
9... Gate electrode, 21S... Source electrode, 21d
...Drain electrode.

Claims (1)

[Claims] In a semiconductor device comprising a predetermined pattern of electrodes and an insulating film formed adjacent to a surface of a semiconductor substrate, the electrodes include:
an electrode base layer having an alloy layer with the semiconductor substrate on the side facing the semiconductor substrate; and an electrode coating metal partially laminated on the electrode base and filling the space between the electrode base and the insulating film facing each other. A semiconductor device characterized by comprising a layer.