JPH0320165B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an integral type phase-locked oscillator having an integrating circuit in its loop for the purpose of suppressing steady-state phase errors.

Conventionally, for the purpose of suppressing steady-state phase errors, etc., an integral type phase-locked oscillator having an integrating circuit in its loop uses a reference input signal 100 and an output signal of a voltage-controlled oscillation circuit 4 as shown in FIG. The phase comparison circuit 1 includes a phase comparison circuit 1 that generates a signal proportional to a phase difference of 200 degrees, and an integration circuit 3 that integrates the output signal of the phase comparison circuit 1 and provides a control voltage to the voltage controlled oscillator 4. Note that the center frequency of the voltage controlled oscillator circuit 4 is generally equal to the output frequency of the integral phase synchronized oscillator during normal operation.

Problems to be Solved by the Invention In the conventional integral type phase-locked oscillator as described above, when a disconnection failure occurs in the reference input signal 100, the occupancy rate of the output signal of the phase comparator circuit 1 becomes a constant value. Since the integrating circuit 3 integrates the output signal of the phase comparator circuit 1 and generates the control voltage for the voltage controlled oscillation circuit 4, unless the occupancy rate of the output signal of the phase comparator circuit 1 is strictly 50%, the integration circuit 3 The output voltage ultimately reaches a maximum or minimum value determined by its capabilities. As a result, the output frequency of the voltage controlled oscillation circuit 4 also becomes the highest frequency or the lowest frequency that is far away from the center frequency.

As described above, the conventional integral type phase-locked oscillator has the drawback that the output frequency when the reference input signal is impaired is a value that is significantly different from the output frequency during normal operation.

The present invention has been made in view of the above-mentioned conventional circumstances, and therefore, an object of the present invention is to eliminate the drawbacks of the conventional integral type phase synchronized oscillator as described above with a simple circuit configuration, and to provide a system in which the reference input signal is An object of the present invention is to provide a novel phase-locked oscillator that can maintain its output frequency at a predetermined frequency even in the event of a disturbance.

Means for Solving the Problems In order to achieve the above object, a phase synchronized oscillator according to the present invention includes a voltage controlled oscillator circuit and converts the occupancy rate of the output signal waveform of the voltage controlled oscillator circuit in accordance with a control signal. a phase comparator circuit that generates a signal proportional to the phase difference between the output signal of the voltage controlled oscillation circuit and the reference input signal, one input of which is the output signal of the occupancy conversion circuit; a selection circuit that takes an input as an output signal of the phase comparison circuit and selects one of the output signals according to a selection signal; an integration circuit that integrates the output signal of the selection circuit and provides a control voltage to the voltage-controlled oscillation circuit; and the control circuit. A voltage comparison circuit that compares a voltage with a predetermined potential and provides the control signal to the occupancy conversion circuit; and a fault detection circuit that detects a fault in the reference input signal and provides a selection signal to the selection circuit. configured.

Embodiments of the Invention Next, one preferred embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a phase-locked oscillator according to the present invention. In the figure, reference numeral 100 is an input terminal of the phase-locked oscillator according to the present invention, and 200 is also an output terminal. Also, 1
is a phase comparison circuit, 2 is a selection circuit, 3 is an integration circuit,
4 is a voltage controlled oscillation circuit, 5 is a voltage comparison circuit, 6 is an occupancy conversion circuit, and 7 is a reference input signal failure detection circuit. The occupancy rate conversion circuit 6 is easily configured by, for example, a frequency dividing circuit or various waveform conversion circuits. In addition, the fault detection circuit 7
Various detection circuits are used depending on the type of fault, and in the case of the present invention, for example, a disconnection detection circuit is used.

As for the occupancy rates of the output signals 500 of the occupancy rate conversion circuit 6, at least one of them has an occupancy rate of 50% or more, and at least one of the other has an occupancy rate of Less than 50%. In addition, the output frequency f _D of the occupancy rate conversion circuit 6
When the integration time constant of the integrator circuit 3 is T, it is sufficient that the following formula (1) is satisfied, and the phase comparator circuit 1 is not necessarily
It does not have to be equal to the output frequency of , and the frequency may change as the occupancy rate is converted.

T≫1/f _D ...(1) In the integral type phase-locked oscillator shown in this embodiment, when a normal reference input signal is applied from the input terminal 100, the selection issued from the input failure detection circuit 7 Based on the signal, the selection circuit 2 selects the output signal of the phase comparison circuit 1 from among the two input signals. Therefore, in this state, the reference input signal 1
00 and the output signal of the voltage controlled oscillation circuit 4 are applied to the phase comparator circuit 1, and this output signal is integrated by the integrating circuit 3 and becomes the control voltage of the voltage controlled oscillation circuit 4. It has the same configuration as a conventional integral type phase-locked oscillator, and operates in the same way.

Next, a case will be described in which the reference input signal is in a failure state.

When a failure occurs in the reference input signal applied to the input terminal 100, the failure detection circuit 7 detects this and inverts the selection signal. As a result, the selection circuit 2 selects and outputs the output signal of the occupancy conversion circuit 6 from among the two input signals. As a result, the pulse train is applied to the integrating circuit 3 in the same way as while the reference input signal was normal. here,
If the above equation (1) is established, the control voltage applied to the voltage controlled oscillator 4 via the integrating circuit 3 is the same as before the failure occurred in the reference input signal, and no harmful voltage fluctuation occurs. Now, the occupancy conversion circuit 6
As shown in FIG. 2 500a, the output signal of
If it is 50% or more, the output voltage of the integrating circuit 3 obtained by integrating this signal will increase.

This control voltage is constantly compared with a predetermined reference potential by a voltage comparison circuit 5 so that the voltage controlled oscillation circuit 4 oscillates at a predetermined frequency.
When the control voltage exceeds the reference potential, the voltage comparator circuit 5
The output signal of the occupancy rate conversion circuit 6, that is, the control signal of the occupancy rate conversion circuit 6 is
The signal changes to the one shown in b when the occupancy rate reaches 50%.

As a result, the output voltage of the integrating circuit 3 decreases, and as described above, if this potential falls below the predetermined reference potential, the voltage comparator circuit 3
The control signal generated by the occupancy rate conversion circuit 6 changes again so that the occupancy rate of the output signal of the occupancy rate conversion circuit 6 becomes 50% or more.

In this way, in this phase-locked oscillator, the above operation is repeated when the input signal fails, so that the output voltage of the integrating circuit 3 finally becomes sufficiently equal to the predetermined reference potential. Therefore, if this reference potential is determined in advance so that the output frequency of the voltage controlled oscillation circuit 4 will be a predetermined value, the predetermined frequency will be maintained even when the reference input signal fails.

In this embodiment, a case has been described in which the output 500 of the occupancy conversion circuit 6 changes into two types of occupancy as shown in FIG. In that case, the potential comparator 5 can also be set to 3 accordingly.
Of course, the configuration can output more than one type of control signal.

Effects of the Invention As is clear from the above description, according to the present invention, even when a failure occurs in the reference input signal, the integral type phase synchronization that maintains the output frequency as a predetermined value can be achieved by using a simple circuit configuration. An oscillator can be provided. Furthermore, as can be seen from the above explanation,
The phase comparison circuit, selection circuit, occupancy rate conversion circuit, etc. that constitute the phase synchronized oscillator of the present invention can all be constructed from digital logic circuits, which are not only easy to manufacture but also suitable for integration into an integrated circuit. There is.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram showing an example of the output signal waveform of the occupancy conversion circuit shown in FIG. 1, and FIG. 3 is a conventional integral type phase diagram. FIG. 2 is a block diagram showing a synchronous oscillator. 1... Phase comparison circuit, 2... Selection circuit, 3...
Integrating circuit, 4... Voltage controlled oscillation circuit, 5... Voltage comparison circuit, 6... Occupancy rate conversion circuit, 100... Input terminal, 200... Output terminal, 500... Output signal of occupation rate conversion circuit, 500a ...Output waveform of occupancy rate conversion circuit (occupancy rate 50% or more), 500b...
Output waveform of occupancy rate conversion circuit (occupancy rate less than 50%).

Claims (1)

[Claims] 1. A voltage controlled oscillation circuit, an occupancy conversion circuit that converts the occupancy of the output signal waveform of the voltage controlled oscillation circuit in accordance with a control signal, and an occupancy conversion circuit that converts the occupancy of the output signal waveform of the voltage controlled oscillation circuit in accordance with a control signal, and a phase comparator circuit that generates a signal from the occupancy rate conversion circuit; a selection circuit that has one input as the output signal of the occupancy conversion circuit and the other input as the output signal of the phase comparator circuit; an integrating circuit that integrates the output signal of the selection circuit and provides a control voltage to the voltage controlled oscillation circuit; a voltage comparison circuit that compares the control voltage with a predetermined potential and provides a control signal to the occupancy conversion circuit; and the reference. A phase synchronized oscillator comprising: a failure detection circuit that detects a failure in an input signal and provides a selection signal to the selection circuit.