JPH03201733A - Time built-in processing method of data word and device for executing its method - Google Patents

Abstract

PURPOSE: To increase the processing speed of a method and device for processing assemblage of with data words by automatically restarting the processing of a first data word by processing a second data word during the succeeding time when such a data word that has not been processed and is temporarily stored does not exist after processing data words. CONSTITUTION: When the processing of a data word (n) ends immediately before the arrival of the succeeding data word n+1, the data word n+1 stays in an intermediate memory, but, since the data word nil stays in the intermediate memory until the next data word n+2 arrives, the data word n+1 must be read out from the intermediate memory and processed immediately before the arrival of the data word n+2. Therefore, the data word n+1 is read out and, immediately after the word n+1 is read out, the succeeding data word n+2 is written. The duration of a processing block (m) varies depending upon the number and types of the commands realized here. Therefore, the processing speed of a method and device for processing assemblage of time with data word can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The invention relates to a method for time-integrated processing of a sequence of first data words arriving at a predetermined constant frequency and a sequence of second data words arriving at a lower frequency. The method relates to a method in which the processing of each first data word requires a period less than the inverse of a predetermined frequency, and also relates to an apparatus for implementing the method.

PRIOR ART In particular, a method of this type is implemented by a signal processor processing sampled values of an analog signal source digitized as data words or sampled values of a signal already provided digitally, the signal being It is time-dependent and individual sampling values of the same signal or of the same signal source are processed in each case according to the same program. In the case of special applications for this, for example, the currently widespread compact disc CD
Processing of digitized audio signals from storage media. Since each of these signal values is subjected to the same algorithm in the form of an application program within this signal processor, the number of instructions that can be executed within a sampling period and the extent of the instructions themselves are a measure of the work of the digital signal processor used. express.

In this application, for example, in the case of a CD, 44.1k
In addition to primary functions such as volume and balance, the setting of the highest and lowest notes performed in the signal processor in a foreground program that repeats at a sampling frequency of Hz requires only a small amount of time, e.g. There are other functions within the audio system that may be referred to as secondary functions. The rate of change of the signal for these secondary functions is therefore considerably less than for the primary functions, so
- It is possible to execute the secondary function within the time difference remaining during or at the end of the sampling period between the execution of the foreground program for the next function.

An example of such a secondary function is stereo/mono switching within an audio system or a means for decoding station identifiers.

In order to be able to execute the background program, it is therefore necessary that the sampling period is not completely occupied by instructions of the foreground program.

Since the space for the background program is usually limited within the sampling period, the background program must be divided into a corresponding number of suitable sub-programs, and one such sub-program can Processed in successive sampling periods after the foreground program. Since the branch programmed into the corresponding sub-program of the background program is then executed at the end of each foreground program, and the return branch to the beginning of the subsequent foreground program is frequently controlled by the corresponding synchronization signal. , a wait loop is provided at the end of the background sub-program to wait for this synchronization signal.

This already constitutes an inconvenient use of time for this signal processor. Moreover, for each program branch, many commands must be given, especially for the handling of branch addresses, which increases the program execution time proportionally as background sub-programs become smaller. Requires.

OBJECT OF THE INVENTION It is an object of the invention to disclose a method of the kind mentioned at the outset, in which the time remaining after the processing of a first data word within a constant sampling period is , can possibly be used for processing at least one further data word.

(Means for Solving the Problems) According to the present invention, this objective is to
of the data words are in each case temporarily stored, and for many directly consecutive data words, as long as the processing of the data word is followed by a previously unprocessed temporarily stored data word. Immediately after the processing of each previous data word is completed, the temporarily stored data word is processed, and otherwise at least one second data word is processed during a subsequent time and then the first This is achieved by automatically restarting the processing of data words.

In this method, the time remaining in a cycle for execution of a program for a first data word is accumulated over a plurality of cycles until there are no more temporarily stored data words that have not been processed. Therefore, subsequent time is now available which can be used to process at least one second data word.

The period of time that follows is determined by the number of data words that are temporarily stored and does not need to be fully utilized, but only after the second of all second data words has been processed. In the event of a failure, no waiting cycle has to be inserted, rather the next temporarily stored first data word can be processed again directly in succession. However, since generally only a few second data words, often only one second data word in each case, are to be processed, and this processing program usually does not require much time, , according to one further refinement of the invention, said first number is 1, the previous data word is overwritten when a new data word is stored, and the subsequent time period is It is advisable that it is at most equal to the reciprocal of the predetermined frequency. Particularly in the case of audio signal processing, this period is practically always sufficient and requires little memory expenditure.

for carrying out the method according to the invention, comprising a program-controlled signal processor having a data terminal for receiving a data word to be processed and for outputting a processed data word, and having a control terminal; The apparatus is configured such that a first memory is provided for said first number of data words, one input terminal of said first memory being for said first data words and for storing said first data words as data. The data of the signal processor is connected to an input terminal for writing into a first memory with word timing, and one output terminal of this first memory is controlled by a first output signal from the signal processor. the input terminal for the second data word can be connected to the data terminal of the signal processor via a second switch controlled by a second subsequent signal from the signal processor; It is characterized by Therefore, in this type of device,
only one memory is required, while the control and in particular the switching from the processing of the first data word to the processing of the second data word is carried out directly by the signal processor;
The writing of one first data word to the first memory in each case is signaled to the first memory. Since the processing of the first data words is now carried out asynchronously with their arrival time, this The processed data word is normally output at the data terminal of the signal processor, also asynchronously with respect to the arriving data word. However, since this requires additional programming and time expenditure, one further improvement of the device according to the invention is that a second memory is provided and one input terminal of this second memory is connected to its It is possible to connect to the data terminal of the signal processor via a third switch controlled by the write signal of the signal processor, and to one output terminal of the second memory thereof, an equal interval depending on the data word timing is provided. It is characterized in that it is possible to retrieve the processed data words. This second memory
The capacity of the second memory largely matches that of the first memory.
The layout is completely symmetrical to the memory capacity.

The capacity of these memories can be selected according to the desired duration. An advantageous further refinement of the device according to the invention for carrying out a further refinement of the method according to the invention is that the at least first memory (26, 28) stores only one data word in each case, and It is characterized in that when storing a new data word, an old data word is overwritten. This usually creates a sufficient period for the processing of at least one second data word and requires only a small memory with very simple control.

For other applications, particularly for processing digital audio data from compact disc CDs, data words are transferred bit serially with data bit timing. An additional improvement of the present invention is to receive the data bits sequentially with data bit timing;
and a serial-to-parallel converter configured to output the data word in parallel form to the first memory after receiving the data bits of one data word in each case, and to generate data word timing from the data bit timing. It is characterized by being provided before the memory. The output terminal of this serial-to-parallel converter then represents a source of parallel data words. In a corresponding manner, if a second memory is provided, it is taken over by a parallel-to-serial converter, so that the data word is finally output again bit-serially.

If the device according to the invention is used for digital audio signal processing, a stereo audio signal is usually assumed, the data words being sampled values of the stereo audio signal, in each case two data partial words. , two successive data part words representing in each case mutually corresponding sampling values of two stereo channels.

In order also to be able to process these accompanying data part words almost simultaneously in each case, an additional further refinement of the device according to the invention provides that the at least first memory can process one data part word in each case. The first and second data part word timings occur alternately for each second data part word. and the first intermediate memory writes the data portion word at the first data portion word timing;
and both first data portions with word tying of the second data portion.
It is characterized in that the partial memories are adapted to write the data partial words at the same time. In this method, both data part words are available in parallel and can be transferred by this signal processor in direct succession.

If a second memory is used, it is expedient to configure it similarly to the output side.

(Embodiment) In the following, referring to the drawings, FIG. 1 shows a plurality of sequential first data words n-3 to n+2 and a second data word m.
and the order in which they are processed. Column a> indicates by arrows the instants of arrival of the first data word and their number for the data word, optionally appended with n.

Column b) represents the contents of the intermediate memory which receives and temporarily stores the supplied data words. In this case, it is assumed that only one data word is temporarily stored, and this data word is overwritten by the next supplied data word.

The period between the instant at which a data word is written into the intermediate memory and the instant at which this data word is read and provided is shown in column C〉, and this subsequent instant is indicated by an arrow in column d). . Column C) further shows the contents of a flag memory within the processing device which is set with each temporary storage of a new first data word and reset when this data word is transferred for processing. As can be seen from FIG. 1, the period between two successive instants is shorter than the period between the arrival of two successive data words.

Therefore, the period between reading and writing the intermediate memory becomes shorter and shorter for successive data words up to data word n.

Adjacent blocks in column e) are each intended to symbolize the processing of one word, the code in the block indicating the data word being processed during this time. It is clear from this column e) that at the end of the processing of data word n, the following data word n
+1 has not yet arrived and a switch occurs to process the second data word m. For this, a processing period of at most the period of the first data word is obtained. The reason is that if the processing of data word n ends just before the arrival of the next following data word n+1, the latter data word n+1 remains in the intermediate memory until the arrival of the next data word n+2. , and therefore data word n+1 is at least data word n+
This is because it is necessary to read out and use the processing immediately before the arrival of 2. This is shown in columns C) and d), where data word n+1 is read and immediately followed by the next succeeding data word n+2. The duration of a processing block m is determined by the number and type of commands executed here. As is clear from FIG. 1, processing block m
It is also possible to easily shorten the duration of . In this case, the next block to process the second data word is
Repeated after fewer first data words.

In this way, the difference between the period of the first data word and the processing period is accumulated for successive data words, ultimately resulting in successive processing blocks for the second data word. However, the arrival of the first data words and the processing of these first data words are performed asynchronously with respect to each other.

However, this asynchronous execution is made possible by using intermediate memory. The successive durations of processing the second data words therefore make it possible to carry out this processing very efficiently and with low administrative costs. The reason is that such processing of the second data word is usually short and can be completed within the period of the first data word. Otherwise,
Processing of the second data word must be terminated and subsequently resumed during the next consecutive period of processing the second data word. However, the administrative costs required in this case are only a fraction of the duration of the total processing block obtained for the second data word.

The processed data word is in each case the end of the processing of the first data word, as can be seen from column f> in FIG.

It will be output at 7 o'clock. This also shows that, firstly, the time interval between processed data words is not constant and, secondly, this time interval is shorter than the time interval between the incoming first data words.

Furthermore, it is possible to ensure that the processed data words occur synchronously with the supplied data words, i.e. only certain shifts of one or more complete data words are allowed. Often desirable.

This can be done by using a temporary storage (intermediate memory) for the processed first data words on the output side so that these processed first data words occur in accordance with the instants in column f) in FIG. This is achieved by making

Column h) shows the contents of this intermediate memory. The processed data word is written in each case at the specified instant in column f), and the processed first data word temporarily stored at the output is processed as shown in column i〉. is output synchronously with the arrival of the first data word.

The signal waveform in column g) indicates the interval between the reading of the intermediate memory on the output side and the next writing of the subsequent processed data word, and at the same time the processed data word is read, i.e. the intermediate memory It shows the state of the flag memory for processing on the output side, which is set each time the next processed data word is written. Therefore, the new data word is in this column g
) can be written only when the signal is at high level. However, at the end of the processing of data word n in column e〉, the signal in column g) is still at a low level, so that the processed data word n cannot be output immediately;
This output occurs only at the end of processing block m. This can be easily achieved during processing by having the processing block for a first data word in each case not start with the reading of a new data word, but with the output of the last processed data word. be able to. By doing this, the processed data word n
is output only at the end of processing block m, as is clear from column f).

FIG. 2 is a circuit diagram showing in block form an apparatus for processing serially applied and output digital stereo audio signals as well as other data words. The device essentially comprises an input 2 for serial-to-parallel conversion and time storage of data words, and a signal processor 3 symbolically shown.
an output section 4 with an intermediate memory and a parallel-to-serial converter. These three parts are controlled by a controllable switch 36
and 38 or 56 and 58 via the data bus 5 , furthermore the input line 17 for the second data word can be connected to the data bus 5 via the switch 34 . The data word to be processed is supplied in bit series via an input line 15 with a bit timing signal via line 13, with which it is serially written into the input shift register 22. In each case,
a predetermined number of sequential bits (generally 16 bits corresponds to 2 bytes) constitute a data portion word and represent one sampled value of one of the two audio channels;
Two sequential data portion words represent related simultaneous sampling values of the two audio channels. The channel control signal on line 11 indicates to which channel the simultaneously arriving data bits or data partial words formed therefrom belong.

The input line 13 for the bit timing signal, in addition to the input shift register 22, is led to an input timing controller 20 which also receives the channel control signal via the input line 1 and inputs each data part word forming the data part word. A signal is generated on line 21 or 23 at the end of the data bit stream. At the end of the first of the two associated data part words, a signal is generated on line 21, which signal is fed to intermediate register 24 and which is contained in input shift register 22 at this instant. The data bits of the first data portion word are connected to the line 25.
a second register which writes in parallel form to this intermediate register via
At the end of the data part word, its bits are present in parallel form at one input of the human register 28 via the connection line 25, and at the same time the first data part word from the intermediate register 24 is present in the other input register 26. Present in parallel form at one input terminal, both of these data part words are transferred to these two input registers 26 and 28 with a signal on line 23 at the end of the second data part word. Next, the contents of these manual registers are output line 2
7 and 29 in parallel form.

The signal on line 23 is further fed to the signal processor 3 via its control input and sets the flag memory 7 of this signal processor to provide the signal processor 3 with a complete data word consisting of two data partial words. can be obtained in parallel form. As soon as the signal processor 3 has finished processing the associated pair of data part words, it supplies subsequent signals in sequence via lines 37 and 39 to switches 36 and 38, so that these switches
7 and 29 are connected in sequence to the data bus 25 so that this signal processor can write two data part words directly in sequence and supply these data part words to the processing program.

At the same time, the flag memory 7 of the signal processor 3 is reset (cleared). The principle of this sequence is the first
It is also clear from columns a) to e) of the figure that the instants shown in column a) represent the times when the signal is formed on line 23 of FIG.

Flag memory 7 at the end of processing of a pair of data part words
is not set, which is the case at the end of processing data word n in FIG. A line 17 is connected to the data bus 5 so that the second data word can be transferred in parallel via this input line 17 to the signal processor 3 for processing.

However, it is also possible to supply the second data word serially to the signal processor 3 via a corresponding further input terminal, so that the processed second data word is output in parallel form via the data bus 5; It can be output in series via another output terminal (not shown for simplicity).

After each processing of a pair of data part words, the signal processor 3 outputs these two data part words sequentially via the data bus 5 and in each case sends a write signal to line 57 or 5.
9 and these write signals operate switches 56 and 58 in sequence, so that two data part words are written into one output register 46 or 4 via input terminals 53 or 55, respectively. These instants are the first
This is the instant shown in column f) of the figure. At the same time, the flag memory 8 of the signal processor 3 is reset.

The data portion words stored in output registers 46 and 48 are transferred to data output line 19 with a tie that is not synchronized with the signal processor's write signals on lines 57 and 59.
Further, an output intermediate register 44, a parallel-to-serial converter 42, and an output timing controller 40 are provided in order to sequentially output bits in series.

Output timing controller 40 receives data bit timing signals on line 13 and channel control signals on line 11 and generates internal control signals on lines 41, 43 and 45. As a result, the data bits of the processed data word are produced on the output line 19 synchronously with the data bits of the data word to be processed arriving on the input line 15, and from input to output the total number of Only pairs of data words or data subwords are shifted.

At the beginning of a pair of data portion words, ie at the beginning of the first data portion word, signals are asserted on lines 43 and 45. The signal on line 43 transfers one data portion word from output register 48 to output intermediate register 44 and the signal on line 45 transfers the other data portion word from output register 46 to connection line 47 and line 41. The switch 50 has just been switched into a conductive state by a corresponding signal.
and connection line 49 to the parallel input terminals of the output shift register 42, which acts as a parallel-to-serial converter. Thereafter, as a result of the data bit timing signal on input line 13, this parallel data portion word is output via output line 19 in bit parallel fashion.

The signal on line 43 causes the output flag memory 8 of the signal processor 3 to be set again and the output register 46
and 48 can each again receive one data portion word. The reason is that the previous contents have been transferred to the output intermediate register 44 or output shift register 42. The signal on line 43 therefore occurs at the instant shown in column i) of FIG.

At the end of the first data portion word, the signal is on line 45.
Since the signal on line 41 is again switched, the switch 52 is switched into conduction via the inverter 54, and the second data portion word is transferred from the output intermediate register 44 to the parallel input terminal of the output shift register 42. This second data portion word is supplied to line 4.
This output intermediate register 44 is written by the signal at 5. This second data portion word is input line 1
The data bit tying signal at 3 outputs the bits serially via output line 19.

Therefore, by using input registers 26 and 28, during the processing of regularly arriving data words, the time difference between the period of arrival of these data words and the processing period for successive data words is accumulated and and the processing of these data words are performed asynchronously with respect to each other,
It may be provided that successive periods of processing the second data word are available after a number of data words that depend on the time difference. Since this example concerns processing stereo digital audio signals, intermediate registers 22 and 24 were used. Particularly when using multiple input registers similar to registers 26 and 28 that need to be serially connected in the data path and thus buffer multiple data words, one or more second data It will be readily appreciated that longer processing blocks for words are possible.

[Brief explanation of drawings]

1 is a timing diagram illustrating the method according to the invention, and FIG. 2 is a block diagram illustrating a device according to the invention with memories on the input and output sides. 2... Input section, 3... Signal processor, 4... Output section, 7... Flag memory, 8... Output flag memory, 20... Input timing controller, 22... Human power Shift register, 24...Intermediate register, 26, 28...Input register, 34, 36.38.50.52.56.58...Switch, 40...Output timing system? ! [, 42... Output cash register (parallel-serial converter) 4
4... Output intermediate register, 46, 48... Output register, 54... Inverter, 口D Q#～--NA (KO1KO CL) gin-mo 27-L

Claims (1)

Claims: 1. A method for time-integrated processing of a sequence of first data words arriving at a predetermined constant frequency and a second sequence of data words arriving at a lower frequency, wherein each first data word In a time-integrated processing method of data words, in which the processing of data words requires a period shorter than the reciprocal of a predetermined frequency, a predetermined first number of first data words are in each case temporarily stored and a number of direct During successive data words, immediately after the processing of each previous data word is completed, as long as there is a previously unprocessed temporarily stored data word after the processing of the data word, Data characterized in that a stored data word is processed and otherwise at least one second data word is processed during a subsequent time after which processing of the first data word is automatically resumed. Word time embedding processing method. 2. said first number is 1, the previous data word is overwritten when a new data word is stored, and the subsequent period of time is at most equal to the reciprocal of the predetermined frequency; 2. A method according to claim 1, characterized in that: 3. The method according to claim 1 or 2, comprising a program-controlled signal processor having a data terminal for receiving the data words to be processed and for outputting the processed data words, and having a control terminal. A first memory (26, 28) is provided for said first number of data words, one input of said first memory being for said first data word. are connected to an input terminal (25) for writing these first data words into a first memory (26, 28) with data word timing (23), and one output terminal (27) of this first memory. , 29) to the data terminal (5) of the signal processor (3) via a first switch (36, 38) controlled by a first read signal (37, 39) from the signal processor (3). and that the input terminal (17) for the second data word is connected to the signal processor (3) via a second switch (34) controlled by a second read signal (35) from the signal processor (3). 3)
A device for time-integrated processing of data words, characterized in that it can be connected to a data terminal (5) of a data word. 4. A second memory (46, 48) is provided, the second memory (46, 48)
One input terminal (53, 55) of the memory to the data terminal (5) of the signal processor via a third switch (56, 58) controlled by the write signal (57, 59) of the signal processor (3) one output terminal (49) of the second memory (46, 48) for retrieving processed data words at equal intervals depending on the data word timing (23); 4. A time-integrated processing device for data words as claimed in claim 3, characterized in that it is possible. 5. At least the first memory (26, 28) is in each case one
5. A time-integrated processing device for data words as claimed in claim 3 or 4, characterized in that it stores only five data words and, when storing a new data word, overwrites an old data word. 6. A time-integrated processing device for data words according to claim 3, 4 or 5, wherein the data words arrive bit serially with data bit timing, and in each case one After receiving the data bits of a data word, the data word is first
Serial output to memory (26, 28) and generating data word timing (23) from data bit timing.
A parallel converter (20, 22) is connected to the first memory (26,
28). 7. The data words are sampling values of a stereo audio signal and consist in each case of two data part words, two sequential data part words in each case representing mutually corresponding sampling values of two stereo channels; A device for time-integrated processing of data words according to any one of claims 3 to 6, characterized in that the at least first memory comprises two partial memories (26, 28) each for one data partial word. configured,
an intermediate memory is provided before one of the partial memories (26); the first and second data partial word timings occur alternately for each data partial word;
and the first intermediate memory (24) writes the data portion word with the first data portion word timing, and the first intermediate memory (24) writes the data portion word with the first data portion word timing;
A device for time-integrated processing of data words, characterized in that both first partial memories (26, 28) write data part words simultaneously with data part word timing.