JPH0320175B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applied to a time division multiplex communication system. In particular, the present invention relates to a frame synchronization circuit for establishing frame synchronization by detecting frame synchronization bits from a received data string when transmission data includes frame synchronization bits to constitute frame synchronization.

[Conventional technology]

FIG. 3 shows a frame structure used in a conventional time division multiplex communication system. One frame synchronization word period (one multiframe MF) consists of several to several hundred frames F, and one frame F is a multiplexed frame consisting of one frame synchronization bit (F' or MF') and multiple bits. It is composed of data D. Here, the frame synchronization bits F' and MF' are repeated for each frame. In particular, the frame synchronization bit F' alternates between "1" and "0" patterns every other time.

FIG. 2 shows a circuit diagram of a main part of a conventional frame synchronization circuit. The received data string input to the input terminal 1 is input to the synchronization signal separation circuit 2. If one frame F is made up of A bits, the synchronizing signal separation circuit 2 outputs a signal a every 2A bits.
The synchronization control circuit 3 inputs the signal a to determine and control the frame synchronization bit, and outputs a shift pulse b when frame synchronization is not established.

When the synchronizing signal separation circuit 2 receives the shift pulse b, it delays the timing at which the signal a is taken out by one clock. By outputting the shift pulse b, the synchronization control circuit 3 stops outputting the shift pulse b when it determines that the frame synchronization bit F' has been continuously detected m times. When reception of the period of frame synchronization bit F′ is established, the signal included in the input signal IN is
The time position of the MF' bit becomes clear (Figure 3).

Synchronous signal separation circuit 2 selects the input signal IN from the input signal IN.
The MF' bit is extracted and input to one side of the exclusive OR circuit 4. The output signal d of the pattern generation circuit 5 is input to the other exclusive OR circuit 4, and the two signals are compared. Pattern generation circuit 5
generates the same pattern as the MF' bit. The synchronization control circuit 6 inputs the output signal e of the exclusive OR circuit 4 to determine and control MF' bit synchronization, and if it is determined that MF' bit synchronization has not been established, it outputs a shift pulse f. It is output to the pattern generation circuit 5 and the signal d is delayed by one clock. signal
When the patterns of MF′ and d match, the synchronization control circuit 6
determines that MF' bit synchronization has been established and stops the shift pulse f. However, when the synchronization control circuit 6 does not receive the frame synchronization bit reception cycle establishment state signal g from the synchronization control circuit 3, it does not accept the signal e and the MF' bit is out of synchronization.

[Problem that the invention seeks to solve]

However, in such conventional circuits, the circuit configuration requires that the frame synchronization bits have a regular repeating pattern, and the number of frames included in one synchronization word period (one multiframe) increases. The disadvantage is that the longer the time, the more time it takes to establish multiframe synchronization.

In a communication system such as a time division multiplex communication system where a frame structure exists in the received data stream, the time required to establish frame synchronization and multi-frame synchronization from the received data is wasted time, so this wasted time should be minimized. There is a need to.

The present invention solves this problem, and when received data forms a frame structure or a multi-frame structure as in time division multiplex communication, when an arbitrary bit structure is formed as a frame synchronization word in the received data. An object of the present invention is to provide a frame synchronization circuit that minimizes wasted time required to establish frame synchronization and multi-frame synchronization (frame synchronization word synchronization) even when repeated synchronization of frame synchronization words is prolonged. do.

[Means for solving problems]

In the present invention, a frame synchronization word consisting of M bits in total is provided for each frame with N bits (M>
In the data transmission system where N) are allocated,
means for storing received data corresponding to this timing in an L-bit shift register using the reception timing of locally generated frame synchronization bits, and a frame in which the code constituted by the L bits is composed of M bits A means for determining whether or not the word is a component of a synchronization word; and a means for determining whether the word is a component of a synchronization word; means for performing the above determination again after bit shifting; and control for shifting the locally generated frame synchronization bit reception timing by one bit when the determining means determines that the L-bit code is a constituent element of a frame synchronization word. When the stopping means and the determining means determine which part of the frame synchronization word composed of M bits the L bit code is a component of, frame synchronization is performed from the received data string by knowing this position information. and means for establishing multi-frame synchronization (word synchronization for frame synchronization).

[Effect]

The phase correction of the signal is repeated until it is determined that the L-bit code is a component of the frame synchronization word, and once it is determined that the L-bit code is a component of the frame synchronization word, the next L-bit code is , the generation cycle of the frame synchronization bit reception timing is held until it is determined that the bit is not a constituent element of the frame synchronization word.

〔Example〕

An embodiment of the present invention will be described based on the drawings.

FIG. 1 is a block diagram of essential parts of an embodiment of the present invention. Input terminal 1 is L bit shift register 1
Connect to the 0 input. The output of this L-bit shift register 10 is transferred to a 2 ^L × P-bit ROM (Read Only
Memory) 11, and its output is led to a state control circuit 12 and a frame counter 13, respectively. The output of this state control circuit 12 is guided to a frame counter 13. The output of this frame counter 13 is led to the L-bit shift register 10.

With this circuit configuration, a frame synchronization word made up of M bits input to input terminal 1 is transmitted to each frame as frame synchronization bits N(M
The received data string of the input signal IN containing >N) bits is applied to the L-bit shift register 10. The L-bit shift register 10 selectively extracts data specified by the frame synchronization bit reception timing signal h generated by the frame counter 13 from the input signal IN, and stores the bits specified by the signal h in L bits. And this L bit is 2 ^L
It is output to the ROM 11 consisting of ×P bits. The ROM 11 uses the output signal i of the L-bit shift register 10 as an address input, and the L-bit code stored in the L-bit shift register 10 is
It is determined whether it is a subset consisting of L bits in the frame synchronization word consisting of bits. If it is determined that it is a subset of the frame synchronization word, it is determined at which position in the frame synchronization word consisting of M bits the subset is located, and the former determination result is sent to the determination information signal. output to the state control circuit 12 as j,
The L-bit code generation position information k, which is the result of the latter determination, is output to the frame counter 13.

The state control circuit 12 inputs the judgment information signal j as the output of the ROM 11, and the judgment information signal j is a subset of the frame synchronization word composed of M bits, and the L-bit code stored in the L-bit shift register 10 is input to the state control circuit 12. If it is determined that this is not the case, it outputs a control signal l for shifting the frame synchronization bit reception timing signal h by 1 bit to the frame counter 13, and also determines that the L bit code is a subset of the frame synchronization word. In this case, the output of the control signal l is stopped.

The state control circuit 12 operates in cases other than the above, namely, a set in which the L bit code i is determined to belong to a subset of frame synchronization words, and a set in which it is determined that the L bit code i does not belong to a subset of frame synchronization words. If the result of the determination that the control bell l belongs to any of the above is input as the determination information j, no new state determination is performed, and the control bell l retains its previous state.

The frame counter 13 receives the control signal l and position information k and generates a frame synchronization bit reception timing signal h. Frame counter 13
In the section where the control signal l instructs correction of the output timing of the frame synchronization bit reception timing signal h, the output phase is shifted by 1 bit every time the frame synchronization bit reception timing signal h is generated L times, and this is repeatedly controlled. When the signal l stops the correction instruction, the phase correction of the signal h is stopped.

That is, the phase correction of the signal h is repeated until it is determined that the L-bit code i is a component of the frame synchronization word, and once it is determined that the L-bit code is a component of the frame synchronization word, the The generation cycle of the frame synchronization bit reception timing signal h is held until it is determined that the L bit code is not a component of the frame synchronization word.

On the other hand, if it is determined that the L-bit code is a component of the frame synchronization word, it is determined which L-bit subset of the frame synchronization word composed of M bits the L-bit code is. The position information k thus obtained is input to establish frame synchronization and multi-frame synchronization (word cycle for frame synchronization).

Furthermore, using the output timing of the frame counter 13 in the above embodiment, the results of comparing the frame synchronization bits locally generated externally with the pits selectively extracted by the signal h in the above embodiment are shown. A circuit that establishes frame synchronization and multiframe synchronization by adding a circuit input to the L-bit shift register 10 is also considered as an application example of the present invention.

〔Effect of the invention〕

As explained above, according to the present invention, even when the number of frames required to send a frame synchronization word increases, and even when one frame includes a plurality of frame synchronization bits, it is possible to extract frames from a received data string. It is possible to establish frame synchronization and multiframe synchronization by minimizing wasted time required for establishing synchronization and multiframe synchronization (word reception period for frame synchronization).

According to the present invention, there is no need to limit the configuration pattern of the frame synchronization word to a simple repeating pattern.

[Brief explanation of drawings]

FIG. 1 is a block diagram of essential parts of an embodiment of the present invention. FIG. 2 is a block diagram of a conventional device. Third
The figure shows a frame structure of a general time division multiplex communication system. 1...Input terminal, 2...Synchronization signal separation circuit,
3, 6...Synchronization control circuit, 5...Pattern generation circuit, 10...L-bit shift register, 12...
State control circuit, 13...frame counter.

Claims (1)

[Claims] 1. Detecting a frame synchronization word from a received data string, which is assigned N bits (N is an integer greater than or equal to 1) to each frame and has M bits (M is an integer greater than N) for each multiframe. In the frame synchronization circuit, there is a circuit that synchronizes with the received data string and generates a timing signal equal to the repetition timing at which the frame synchronization word exists, and a circuit that synchronizes with the timing of the output signal of this circuit. A circuit that temporarily stores bit signals in a received data string; and a circuit that uses the bit signal stored by this temporary storage circuit as an address input, and determines whether or not this bit signal is a set of at least a portion of the frame synchronization word. and a circuit that determines which part the bit signal is a component of and outputs its position information when determining that it is a partial set, and a circuit that determines that this circuit is not the above set. means for changing the phase of the output signal of the circuit that generates the timing signal when the timing signal has been determined, and stopping the change in the phase of the output signal when determining that the timing signal is the set; A frame synchronization circuit comprising means for establishing frame synchronization and multi-frame synchronization based on position information output by the circuit for determining when determining that the frames are a set.