JPH03201775A - Synchronizing signal separation circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for a variable resistor by detecting it that a low level time or a high level time of a composite synchronizing signal is consecutive for a set time or over and generating and outputting a vertical synchronizing signal. CONSTITUTION:Suppose that an output of a vertical synchronizing signal generating section 11 goes to L by an input of an H pulse from decision means 10 and, e.g. five H pulses are outputted from the decision means 10 are outputted while the period of the vertical synchronizing signal Vs is consecutive, an output of the vertical synchronizing signal generating section 11 goes to L while the five H pulses are inputted from the decision means 10 and the output of the vertical synchronizing signal generating means 11 is inverted to H when the 5th H pulse is finished for input and a signal C is outputted to an output terminal 7 as the vertical synchronizing signal. Thus, when the consecutive time of the L level of the composite synchronizing signal counted by a counter 9 is a set time TL or over, the vertical synchronizing signal is generated and outputted to eliminate the need for a variable resistor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronization signal separation circuit that separates a vertical synchronization signal from a composite synchronization signal.

[Conventional technology]

FIG. 3 is a block diagram of a conventional synchronization signal separation circuit. As shown in the figure, the composite synchronization signal inputted to the input terminal 1 is amplified by the manual buffer circuit 2, and the variable resistor 3
The output signal of the input buffer circuit 2 is inputted to the output buffer circuit 6 via an integrating circuit 5 consisting of a capacitor 4 and a capacitor 4, and the output signal of the output buffer circuit 6 is outputted as a vertical synchronizing signal to a vertical synchronizing signal output terminal 7.

Next, the operation will be explained in detail using the signal waveform diagram shown in FIG.

When a composite synchronization signal as shown in FIG. 4(a) is input to the manual buffer circuit 2 via the input terminal 1, this is amplified by the input buffer circuit 2, and the composite synchronization signal as shown in FIG. 4(b) is amplified. The signal is input to the integrating circuit 5 and integrated by the integrating circuit 5, and a signal having a waveform as shown in FIG. The human input signal to circuit 6 is shown in the same figure.
8) A signal is output from the output buffer circuit 6, which is a high level when the threshold level is higher than the threshold level of the output buffer circuit 6, and a low level when the threshold level is lower than the threshold level of the output buffer circuit 6, as shown by the broken line in the middle.

At this time, the v8 part shown in FIG. 4(a) corresponds to the vertical synchronizing signal part included in the composite synchronizing signal, and the above operation causes the period corresponding to the Vs part to be low as shown in FIG. 4(d). The signal that becomes the level is output from the output buffer circuit 6 to the output terminal 7 as a vertical synchronization signal.

By the way, if the adjustment of the time constant of the integrating circuit 5 by the variable resistor 3 is not appropriate, as shown in FIG. As a result, the output signal of the output buffer circuit 6 becomes a pulse signal as shown in (f') in the same figure, and a normal vertical synchronizing signal as shown in (d) in the same figure is obtained. Therefore, it is necessary to optimally adjust the variable resistor 3.

[Problem to be solved by the invention]

In the conventional case, once the variable resistor 3 is adjusted, there is no need to adjust it later, but in devices such as television receivers equipped with a synchronizing signal separation circuit as shown in FIG. ．． Output buffer circuit 6. Since there are variations in the characteristics of the capacitor 4, the variable resistor 3 is always required to compensate for this variation and always obtain a normal vertical synchronization signal as shown in Figure 4(d). In the case of external attachment, the number of parts increases, and furthermore, the variable resistor 3 must be adjusted for each device when assembling the device, resulting in an increase in manufacturing costs.

Further, since the process is analog processing using the integrating circuit 5, there is a problem in that the circuit is likely to malfunction due to noise.

This invention was made in order to solve the above-mentioned problems, and it is possible to prevent malfunctions caused by noise without requiring a variable resistor for adjusting the integration time constant as in the conventional case. purpose.

[Means to solve the problem]

The synchronization signal separation circuit according to the present invention includes a detection means for detecting whether the low level or high level time of the composite synchronization signal continues for a predetermined set time, and outputting a detection signal if it continues; The present invention is characterized in that it includes a vertical synchronization signal generation section that generates a vertical synchronization signal based on the detection signal.

[Effect]

In this invention, the low level of the composite synchronization signal or
It detects that the high level time continues for longer than the set time and generates and outputs a vertical synchronization signal, so there is no need for conventional variable resistors or adjustments, and there is no risk of malfunction due to noise. Nor.

〔Example〕

FIG. 1 is a block diagram of an embodiment of the synchronizing signal separation circuit of the present invention.

In the figure, 8 is a system clock input terminal, 9 is a counter that counts the duration of the low level (hereinafter referred to as) of the composite synchronization signal to the reset terminal R, and 10 is a determination means, which together with the counter 9 is a detection means. It has a built-in decoder that decodes the count output of the counter 9, and detects that the counted duration has reached a predetermined set time based on the decoded content, and detects that the vertical synchronization signal part is input. A high level signal (
A pulse (hereinafter referred to as H) is output.

Furthermore, in FIG. 1, 11 is a vertical synchronizing signal generating section, and for example, when the input time of five H pulses from the determining means 10 corresponds to the width of the vertical synchronizing signal determined by regulations, five H pulses are generated. While the H pulse of
The output becomes L, and such a signal is outputted to the vertical synchronization signal output terminal 7 as a vertical synchronization signal.

At this time, since the composite synchronization signal is input to the reset terminal R of the counter 9, the counter 9 receives the composite synchronization signal at the low level.
The counting operation is performed using the clock to the system clock input terminal 8 only when the composite synchronization signal is H.
The counter 9 is in a reset state.

Next, the operation of the circuit shown in FIG. 1 will be explained in detail with reference to the signal waveform diagram shown in FIG.

Now, when a composite synchronization signal as shown in FIG. 2(a) is inputted to the counter 9 via the input terminal 1, the counter 9 performs a counting operation when the composite synchronization signal is L, as described above. However, when the vertical synchronization signal component V8 included in the composite synchronization signal is L, the duration of this L is as shown in Fig. 2 (
Since the predetermined set time Tt shown in a) is shorter, the determination means 10 does not output an H pulse due to the output of the counter 9.

Then, when the V8 portion of the composite synchronization signal shown in FIG. Assuming that the vertical synchronization signal 1g part v8 of the composite synchronization signal is input, the determination means 10 outputs an H pulse, as shown in FIG.
Similar operations are repeated while the vertical synchronization signal portion v8 is manually input.

On the other hand, the second
As shown in FIG. (c), when the output of the vertical synchronizing signal generator 11 becomes L and the determining means 10 outputs, for example, five H pulses while the period of the vertical synchronizing signal portion V8 continues. Then, while 5 H pulses are input from the determining means 10, the output of the vertical synchronizing signal generating section 11 becomes L, and 5 H pulses are input.
When the input of the H pulse is completed, the output of the vertical synchronizing signal generating section 11 is inverted to H, and a signal as shown in FIG. 2(C) is outputted to the output terminal 7 as a vertical synchronizing signal.

In this way, when the duration of L of the composite synchronization signal counted by the counter 9 is longer than the set time T5,
By generating and outputting a vertical synchronization signal, there is no need for a conventional variable resistor, and there is no need to perform adjustment work using this variable resistor, and when integrated circuits are implemented, the number of external components can be significantly reduced. Miniaturization can be achieved.

Furthermore, since the vertical synchronization signal can be generated by digital processing, even if the composite synchronization signal contains noise, malfunctions due to this noise can be prevented.

In the above embodiment, a case has been described in which the vertical synchronization signal portion is detected by counting the duration of L of the composite synchronization signal. However, if the polarity of the composite synchronization signal is opposite to the waveform shown in FIG. 2(a), In the case of polarity, the composite synchronization signal ′
The vertical synchronizing signal portion may be detected by counting the duration of the H signal. In this case, for example, in the configuration shown in FIG. 1, an inverting circuit may be provided immediately after the input terminal 1.

〔Effect of the invention〕

As described above, according to the present invention, in order to detect that the low level or high level time of the composite synchronization signal continues for a set time or longer, and generate and output the vertical synchronization signal,
It eliminates the need for a conventional variable resistor, eliminates the need for adjustment work using this variable resistor, prevents malfunctions due to noise, allows easy integration into integrated circuits, and provides a compact and highly reliable synchronization system. A signal separation circuit can be provided.

[Brief explanation of drawings]

FIG. 1 is a block wiring diagram of the synchronization signal separation circuit of the present invention, FIG. 2 is a waveform diagram of each signal for explaining the operation of FIG. 1, and FIG.
The figure is a block diagram of a conventional synchronizing signal separation circuit, and FIG. 4 is a waveform diagram of each signal for explaining the operation of FIG. 3. In the figure, 9 is a counter, 10 is a determining means, and 11 is a vertical synchronizing signal generating section. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) Detection means for detecting whether the low level or high level time of the composite synchronization signal continues for a predetermined set time, and outputting a detection signal if it continues, and vertical synchronization based on the detection signal. 1. A synchronization signal separation circuit comprising: a vertical synchronization signal generation section that generates a signal.