JPH03203378A - Thin film transistor - Google Patents

Abstract

PURPOSE:To restrain hot carrier effect of bias stress, realize high reliability, and reduce irregularity of characteristics, by making the thickness of a polycrystalline silicon film constituting a channel region 10-40nm. CONSTITUTION:On an Si substrate 1, a field oxide film 2 is formed, and thereon a polycrystalline Si film 3 of 10-40nm in thickness is formed. By thermal oxidation, an Si oxide film 4 is formed on the film 3, and the thickness of the film 3 is reduced. The whole part of the film 4 is etched and eliminated, and an element forming region is defined by patterning the film 3. By thermally oxidizing the film 3 surface, a gate oxide film 5 is formed. A gate electrode 6 is selectively formed on the film 5; the electrode 6 is used as a mask, and P-type impurity ions are introduced, thereby forming a source.drain region 7. An interlayer insulating film 8 is deposited on the surface; an extraction electrode 9 connected with the region 7 is formed by selectively forming an aperture; thus a thin film transistor is constituted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film transistor, and more particularly to a thin film transistor using a polycrystalline silicon film.

[Conventional technology]

2. Description of the Related Art A polycrystalline silicon thin film transistor whose active layer is made of a polycrystalline silicon film is known.

FIG. 5 is a cross-sectional view showing an example of a conventional thin film transistor.

A patterned thin polycrystalline silicon film 3 is provided on a field oxide film 2 provided on a silicon substrate l,
A gate electrode 6 is provided on the polycrystalline silicon film 3 via a gate oxide film 5, a source/drain region 7 is provided in the polycrystalline silicon film 3 in alignment with the gate electrode 6, and the polycrystalline silicon film 3 and the gate electrode are provided. An interlayer insulating film 8 is provided so as to cover the entire surface of the polycrystalline silicon film 3, and an extraction electrode 9 is provided in each of the contact openings provided in the interlayer insulating film 8 so as to be connected to the source/drain regions 7 of the polycrystalline silicon film 3. It consists of

Here, it is said that the effective mobility is maximized when the thickness of the polycrystalline silicon film 3 in the channel region under the gate electrode 6 is, for example, 2 to 10 nm (Japanese Unexamined Patent Publication No. 61-85868).
(see issue).

[Problem to be solved by the invention]

The above-mentioned conventional thin film transistor has a drawback that when the thickness of the polycrystalline silicon film forming the channel region is reduced to 10 nm or less, the characteristics vary widely as shown below. That is, the variation in on-current tends to increase as the thickness of the polycrystalline silicon film becomes thinner.
Below nm, the variation rapidly increases. When the thickness of the polycrystalline silicon film is 10 nm or less, the crystal grains of the polycrystalline silicon film are
Adjacent grain boundaries are separated from each other, and they are not closely approached.
The resistance component at grain boundaries becomes extremely large. Therefore, the presence and area of grain boundaries in the polycrystalline silicon film in the channel region causes on-current to vary greatly depending on the number of grain boundaries.

[Means to solve the problem]

In the thin film transistor of the present invention, the thickness of the polycrystalline silicon film forming the channel region is 10 to 40 nm.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1A to 1E are cross-sectional views of a semiconductor chip shown in order of steps for explaining an embodiment of the present invention.

First, as shown in FIG. 1(a), a field oxide film 2 is provided on a silicon substrate 1, and the field oxide film 2 is grown at 575° C. using SiH4 as a source gas, for example, by low pressure chemical vapor deposition. An amorphous silicon thin film containing P-type impurities is deposited to a thickness of about 15 nm at temperature. After that,
Heat treatment is performed at 600° C. for 12 hours in a nitrogen atmosphere to polycrystallize the amorphous silicon thin film, forming a polycrystalline silicon film 3.
form. The reason why we first deposited an amorphous silicon thin film and subjected it to heat treatment at 600° C. for 12 hours to polycrystallize it was to obtain a polycrystalline silicon film 3 with large crystal grains. Increasing the grain size of the polycrystalline silicon film 3 has the effect of increasing the effective mobility of the transistor.

Next, as shown in FIG. 1(b), a polycrystalline silicon film 3
The upper surface of the polycrystalline silicon film 3 is thermally oxidized to form a silicon oxide film 4, and the thickness of the polycrystalline silicon film 3 is reduced.

Next, as shown in FIG. 1C, the silicon oxide film 4 is etched and removed over the entire surface, and the thinned polycrystalline silicon film 3 is selectively etched and patterned to form the device. Define the formation area.

Next, the surface of polycrystalline silicon film 3 is thermally oxidized to form gate oxide film 5.

Next, as shown in FIG. 1(d), a gate electrode 6 is selectively formed on the gate oxide film 5 in the element formation region, and the polycrystalline silicon film 3 is formed by ion implantation using the gate electrode 6 as a mask. P-type impurity ions are introduced to form source/drain regions 7.

Next, as shown in FIG. 1(e), a polycrystalline silicon film 3
and depositing a glabellar insulating film 8 on the surface including the gate electrode 6,
Contact openings are provided by selectively opening holes in the glabella insulating film 8 above the source/drain regions 7. Next, lead electrodes 9 connected to the source/drain regions 7 of the contact openings are selectively provided to form a thin film transistor.

Figures 2 (a) and (b) show the P-channel type polycrystalline silicon thin film of the example! FIG. 3 is a subthreshold/1/mode characteristic diagram of a +- transistor. Here, the gate length is 0.6 μm.

The solid line is the initial characteristic, and the dashed line is the gate and
Source voltage -2V, drain-source voltage -1
This is the characteristic after applying stress by applying 0V and holding it for 1000 seconds. The thickness of the polycrystalline silicon film in the channel region is 120 nm in FIG. 2(a) and 40 nm in FIG. 2(b).
It is nm. As shown in Figure 2(a), when the polycrystalline silicon film has a thickness of 120 nm, it exhibits bunch-through characteristics after stress and exhibits large deterioration, whereas as shown in Figure 2(b), The thickness of the polycrystalline silicon thin film is 40 mm.
In the case of nm, there is almost no deterioration in characteristics after stress.

The punch-through characteristic appears after stress because hot electrons generated near the drain during stress are captured in the gate oxide film, forming a channel at the end of the drain, resulting in a shortening of the effective gate length. In a P-channel transistor, this occurs during operation in the saturation region. The amount of hot carriers can be evaluated by the amount of gate current in the operating state.

FIG. 3 is a characteristic diagram of gate current versus gate voltage. The solid line indicates the case where the thickness of the polycrystalline silicon film forming the channel region is 120 nm, and the broken line indicates the case where the film thickness is 40 nm. The gate current with a film thickness of 40 nm is one order of magnitude lower than that with a film thickness of 120 nm, as shown in Figure 2 (
This agrees with the results shown in a) and (b) that the film thickness of 40 nm is more resistant to deterioration.

In FIG. 4, the solid line shows the relationship between the maximum gate current and the thickness of the polycrystalline silicon thin film in the channel region, and the broken line shows the relationship between the variation in on-current and the film thickness of the polycrystalline silicon thin film in the channel region. The maximum gate current is obtained by setting the drain-source voltage to -10 V and applying the G-I source voltage in a sweeping manner from 0 to -15 V, and is the maximum value of the gate current in this range. The variation in on-current is expressed as the drain current when the drain-source voltage is 15V and the gate-source voltage is 15V, and the ratio of the maximum value and minimum value of this on-current is expressed as a logarithm. did.

The maximum gate current tends to become smaller as the thickness of the polycrystalline silicon thin film becomes thinner, but it tends to be saturated when the film thickness is about 40 nm or less.

Therefore, in order to obtain a thin film transistor that is resistant to bias stress, it is necessary to increase the thickness of the polycrystalline silicon film in the channel region by 40 mm.
It can be said that it is desirable to make it less than nm.

Furthermore, the variation tends to increase as the thickness of the polycrystalline silicon film in the channel region becomes thinner. In particular, when the film thickness is 10 nm or less, the variation increases rapidly. Therefore, a thin film transistor that is resistant to bias stress, has high reliability with high hot carrier resistance, and has small variations in characteristics is made when the thickness of the polycrystalline silicon film in the channel region is 10 to 4.
This can be obtained by setting the thickness to 0 nm.

The above describes an example of a P-channel type polycrystalline silicon thin film transistor, but the same applies to an N-channel type as well, and by making the polycrystalline silicon thin film that forms the channel region 10 to 40 nm thick, high reliability with high hot carrier resistance can be achieved. With this, it is possible to obtain a thin film transistor with small variations in characteristics.

〔Effect of the invention〕

As explained above, the present invention makes it possible to greatly suppress the hot carrier effect caused by bias stress by setting the thickness of the polycrystalline silicon film forming the channel region in the polycrystalline silicon thin film transistor within the range of 10 to 40 nm. This has the effect of achieving reliability and reducing variation in characteristics.

[Brief explanation of drawings]

1(a) to 1(e) are cross-sectional views of semiconductor chips shown in the order of steps for explaining one embodiment of the present invention, and FIG. 2(a)
), (b) is a subthreshold characteristic diagram of the example, FIG. 3 is a gate current vs. gate voltage characteristic diagram, and FIG. 4 is a relationship between maximum gate current vs. film thickness of the polycrystalline silicon film in the channel region, and on-current. FIG. 5 is a cross-sectional view showing an example of a conventional thin film transistor. l...Silicon substrate, 2...Field oxide film, 3...Polycrystalline silicon film, 4...
...Silicon oxide film, 5...Gate oxide film,
6...Gate electrode, 7...Source/drain region, 8...Interlayer insulating film, 9...
・Extraction electrode.

Claims (1)

[Claims] 1. A thin film transistor in which an active layer in which a channel is formed is made of a polycrystalline silicon film, wherein the polycrystalline silicon film has a thickness of 10 to 40 nm.