JPH03204968A - Semiconductor device and manufacture thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly relates to a method for manufacturing a semiconductor device and a method for manufacturing the same.
In5ulator Sen+1 conductor
) A semiconductor device in which a transistor is formed and a method for manufacturing the same.

[Prior art]

Conventionally, semiconductor devices in which bipolar elements and MIS transistors are formed on the main surface of a semiconductor substrate include bipolar transistors, M, OS (Metal Oxid
e Sem1 conductor) transistors, bipolar transistors and CMOS
(Complementary Metal Oxid
e Sem1 conductor) transistors are known (Jiko 54-46489).
No. 55-91857.

Jikai 55-99763 Publication, Jikai 55-157257
Publication No.

(Refer to Jikai No. 57-75453).

These will be explained using FIG. 1. Figures (1) to (1)
4) shows the main manufacturing steps of a semiconductor device in which an NPN bipolar transistor and a CMOS transistor are formed, and FIGS. 1(a) to 1(e) show schematic cross-sectional views of the main steps.

(FIG. 1(a)) An N-type high impurity concentration buried layer 2 is formed in a P-type semiconductor substrate 1, and an N-type epitaxial layer 3 is grown to form a semiconductor substrate. Next, P ten layers 4 for isolation between elements, NMO
A P-type well region 5 for forming an S transistor is formed. Furthermore, an oxide film layer 6 is formed by a selective oxidation method. N.M.
After forming the gate oxide film 7 of the OS transistor (PuO3)-transistor, boron ions 9 are implanted using the photoresist film 8 as a mask to form the base region 10 of the bipolar transistor.

(FIG. 1(b)) After removing the photoresist film 8, the photoresist film (
(not shown) and by known photoetching.
After opening the emitter window 12 in the gate oxide film 7, the polycrystalline silicon layer 11 used for the gate electrode and the emitter electrode is laminated, and the entire surface of the polycrystalline silicon layer 11 is doped with an N-type impurity (for example, arsenic) that will become the emitter region of the bipolar transistor. is implanted using the ion implantation method.

(FIG. 1(C)) The polycrystalline silicon layer 11 is photo-etched and PuO
2) - transistor, NMO 3) - Gate electrodes 11', 11' of transistor and emitter electrode 11'' of NPN bipolar transistor are formed, and then oxide film 13 is formed.
After growing, SiO is grown as a mask for forming the source and drain of NMo5 transistor and PMOS transistor.
2 membrane 14 by a known CVD (Chemical Va.
It is formed by the Pour Dcposition method.

(FIG. 1(d)) A window is opened in the NMOS transistor section, and N-type source and drain regions 16 are formed by introducing N-type impurities.

(FIG. 1(e)) Again, the SiOx film 17 serving as a mask is formed by the CVD method, windows are opened in the PMOS transistor part and the external base part of the bipolar transistor, and P-type impurities are introduced. source area.

Drain region 18. An external base region 18' is formed.

The above describes the conventional method and structure for producing polycrystalline silicon for the gate electrode of NMOS transistors and PMOS transistors and polycrystalline silicon for the emitter electrode of bipolar transistors in the same process. In this case, there is a problem as shown in (1) below, and the conventional manufacturing method of a semiconductor device has further problems as shown in (1) and (2) below.

(2) First, the gate electrode of the NMOS transistor and PMOS transistor should preferably have a low resistance layer (thick electrode).

Furthermore, since the emitter region of the bipolar transistor requires ion implantation of N-type impurities into the emitter electrode of the polycrystalline silicon layer 11, the emitter electrode is preferably thin.

The conventional semiconductor device shown in FIG. 1 cannot always satisfy these requirements.

For example, when the emitter electrode is formed of polycrystalline silicon, arsenic is used as an impurity in the emitter region to improve the high frequency characteristics of the bipolar transistor, and ion implantation is used to easily control the current amplification factor. Preferably, the method is used. However, when forming emitter regions of the same depth by ion implantation into polycrystalline silicon, it becomes necessary to increase the amount of ion implantation in proportion to the thickness of the polycrystalline silicon. This means that the diffusion coefficient of arsenic in polycrystalline silicon is 2
Because it is more than an order of magnitude larger, in the early stage of heat treatment after ion implantation.

The arsenic concentration in polycrystalline silicon is determined by dividing the ion implantation amount by the thickness of the polycrystalline silicon layer.

When polycrystalline silicon is used as the gate electrode of a MOS transistor, the thickness is increased by about 3,000 Ω, and phosphorus is usually diffused to lower the resistance sufficiently (usually 20Ω/
sq). However, when attempting to form an emitter region by implanting arsenic ions into an emitter electrode made of polycrystalline silicon with a thickness of about 3000, the required implantation amount is 2 x 101 B/aJ.

High-concentration ion implantation requires a long time (e.g. 2X
It takes 20 minutes to implant 1018/a7 ions), so the thickness of the polycrystalline silicon layer is reduced by about half (approximately 1500
If it is done by a person, the time will be shortened, but there will be a problem that the resistance value of the gate electrode of the CMOS transistor will increase.

■ Problems with contamination of gate oxide film 7 and change in film thickness. That is, after the gate oxide film 7 is formed, a two-stage photoetching process (
Steps (2) and (4) in FIG. 1 are present, and the gate film 7 is contaminated or the film thickness changes, which causes a fluctuation in the threshold voltage of the MOS transistor. High speed of MOS transistor.

This problem becomes more severe as the gate oxide film 7 becomes thinner due to higher integration.

■ Incompatible with metal gate materials for MOS transistors. The gate electrode materials of MOS transistors tend to be metal silicides (e.g., molybdenum silicide, etc.) and high-melting point metals (e.g., tungsten, etc.) in order to increase the speed of circuits. Incompatible with crystalline silicon emitter electrodes.

Furthermore, when forming NPN bipolar transistors and NMOS transistors in addition to the above-mentioned transistors (1) to (2), it becomes difficult to control the current amplification factor (hrE) of the bipolar transistors.

After forming the emitter region of the bipolar transistor (step (6) in FIG. 1), it is necessary to perform the step of forming the source and drain regions of the NMOS transistor (step (11) in FIG. 1). If arsenic is used as an impurity, the same degree of heat treatment as that for the emitter region is required, and the current amplification factor of the bipolar transistor tends to fluctuate.

Such problems are not limited to CMOS transistors, but also PMO transistors.
General MIS transistors such as only S transistors and only NMo5 transistors, not only NPN bipolar transistors but also PNP bipolar transistors,
A similar problem occurs in a semiconductor device in which a general bipolar element such as a PNPN thyristor is formed in the same semiconductor device.

[Purpose of the invention]

In order to realize a high-performance bipolar with a high cutoff frequency, it is necessary to have a structure with a narrow base width. However, since an emitter layer is formed in the base layer, the base width depends on the process of forming the emitter layer. In a typical high-speed bipolar device, polycrystalline silicon (poly-Si) is placed on the surface of the base layer, and an n-type impurity element is soaked into the base layer from the polycrystalline silicon to form an emitter layer. At this time, phosphorus and arsenic can be considered as n-type impurity elements, but if phosphorus is used, boron, which is a P-type impurity in the base layer, will undergo accelerated diffusion in response to the diffusion of phosphorus, and will be directly below the emitter layer. The problem is that the base layer becomes deep, making it impossible to form a narrow base width, resulting in a bipolar structure with a low cutoff frequency. For this reason, in conventional bipolar devices, arsenic has been used to form the emitter layer. On the other hand, a MOS device has a structure in which at least polycrystalline silicon is used as a gate electrode. In this case, various impurities are mixed into the gate oxide film during each manufacturing process, resulting in fluctuations in the threshold voltage of MO8 or failure in gate breakdown voltage. When the polycrystalline silicon that is the gate electrode is doped with phosphorus, the phosphorus getster the impurities that enter during the above manufacturing process and has the effect of making the gate oxide film of good quality. However, this effect is small with arsenic, and the polycrystalline silicon used as the gate electrode had to be doped with phosphorus.

As described above, arsenic must be used to achieve high performance in Viparra, and phosphorus must be used to achieve high reliability in Mo3. An object of the present invention is to solve the above-mentioned problems and simultaneously realize a high-performance bipolar transistor and a highly reliable MOS transistor.

[Summary of the invention]

A feature of the semiconductor device of the present invention that achieves the above object is that in a semiconductor device in which at least a MOS transistor and a bipolar transistor are formed on the main surface of a semiconductor substrate, a gate electrode of a MOS transistor and a bipolar transistor are formed. The emitter layer is formed from a layer containing polycrystalline silicon, and both polycrystalline silicon layers are separate layers so that phosphorus and arsenic can be doped as N-type impurity elements, respectively.

[Embodiments of the invention]

The present invention will be described in detail below based on examples.

FIG. 2 (1) to (14) are NPs that are an embodiment of the present invention.
It shows the main manufacturing process of semiconductor devices in which N bipolar transistors and CMOS transistors are formed.
FIGS. 2(a) to 2(f) show schematic cross-sectional views at the main steps.

(Fig. 2 (a)) After selectively thermally diffusing impurities such as antimony into a P-type silicon substrate 1 with a specific resistance of 10Ω to form a buried layer 2 with a high impurity concentration, an N-type epitaxial layer 3 is formed. (specific resistance: 1 Ω·], thickness: 6 μm) to form a semiconductor substrate. Subsequently, a P-type element isolation layer 4 (depth 8 μm),
P-type well region 5 for forming NMO5 transistor (
Surface impurity concentration 1 x 1016/aj, depth 4μm)
Further, a thick oxide film 6 (thickness: 1 μm) and a t-gate oxide film 7 (thickness: 300 μm) are formed by a normal selective oxidation method using a silicon nitride film. So far, the first
This is similar to the prior art shown in the figure.

Next, a polycrystalline silicon layer 11 having a thickness of about 3,500 layers, which will become the gate electrodes of the PMOS transistor and the NMOS transistor, is laminated by a known technique.

Next, an N-type impurity such as phosphorus is diffused into the polycrystalline silicon layer 11 to reduce the resistance value (approximately 20 Ω/sq).

In this embodiment, since the polycrystalline silicon layer 11 is formed and the gate oxide film 7 is covered with the polycrystalline silicon layer 11, the contamination and thickness change of the gate oxide film 7 as described in the prior art can be avoided. It will never occur. Note that, instead of the polycrystalline silicon 11, metal silicide (for example, molybdenum silicide) or a high-melting point metal (for example, tungsten) can be used as the gate electrode of the MOS transistor. These metal-based electrodes cannot be used in a method in which they are also used as an emitter electrode, as in the prior art.

(FIG. 2(b)) The polycrystalline silicon layer 11 is etched by a known photoetching method to form the gate electrode 11' of the PMOS transistor and the gate electrode 11'' of the NMo5 transistor.
form. Next, a known oxidation step is applied to Mo3)-
A double layer 13 (thickness: 500 mm) is formed on the polycrystalline silicon surface of the transistor gate electrodes 11', 11', and an oxide film 13' (thickness: 500 mm thick) is formed on the NPN bipolar transistor formation area.
form people). Note that when the gate electrodes 11', 11' are metal electrodes, an oxide film may be deposited by CVD instead of the oxidation process.

(FIG. 2(C)) Using the photoresist film 8 as a mask, ion implantation of boron 9 is performed to form the base region 10 of the NPN bipolar transistor (energy 80 keV, implantation amount 2
X 1014/an2).

(FIG. 2(d)) After removing the photoresist film 8, the photoresist film (
(not shown) and open the window 12 for forming the emitter region of the NPN bipolar transistor in the gate oxide film 13' by known photoetching.
Approximately 1 mm thick, which serves as the emitter electrode of a bipolar transistor
500 polycrystalline silicon layers 19 are laminated by a known method. The resistance of this polycrystalline silicon layer 19 is 80 Ω·sq, and since it is thinner than the polycrystalline silicon layer 11, the resistance is greater than that of the polycrystalline silicon layer 1.

(FIG. 2(e)) The polycrystalline silicon layer 19 and oxide film 13 in the NMOS transistor formation region are removed by known etching. Next, arsenic ion implantation (energy 10 keV,
Depth: I x 10”/an2), and
Arsenic ions are implanted into the source and drain regions of the OS transistor and the polycrystalline silicon N19# on the emitter window. After this, heat treatment (], OOOoC, 30 minutes)
The emitter region 12' is formed simultaneously with the formation of the source and train regions 16 of the NMOS transistor.

(FIG. 2(f)) (f) is an oxide film 17 (thickness 20 mm) formed by a known CVD method.
00 people), photoetching process, and NMO
While masking the S transistor part and removing the oxide film and polycrystalline silicon 19 of the PMOS transistor part, the NP
A polycrystalline electrode 11'' on the emitter region 12' of the N bipolar transistor section is formed using an oxide film 17'' formed by the CVD method as a mask. Note that instead of the oxide film 17 formed by the CVD method, a photoresist film (
It is also possible to process polycrystalline silicon only by using a method (not shown). Subsequently, ion implantation of boron was performed (energy 100 k e V, implantation amount 1×1015/mark 2).
, heat treated (950°C, 720 minutes), PMO8)
- Source and train regions 18 of transistors. NP
An external base region 18# of an N bipolar transistor is formed. This external base region 18# is the emitter electrode 1
1" in a self-aligned manner, and has a large effect of reducing external base resistance.

An embodiment of the present invention has been described above, and the effects of the embodiment of the present invention can be summarized as follows.

■ The thickness of the emitter electrode of the NPN bipolar transistor is thinner than the thickness of the gate electrode of the transistor. ″ resistance.

Furthermore, since the thickness of the emitter electrode 11'' made of polycrystalline silicon (about 1500 mm) is thinner than the thickness of the gate electrodes 11' and 11' made of polycrystalline silicon (about 3500 mm), as mentioned above, the arsenic The amount of ion implantation can be reduced compared to the conventional method, and the ion implantation time can be shortened.

By separately forming the emitter electrode 11'' after forming the gate electrodes 11', 11', the following advantages arise.

(2) Since the gate oxide film 7 is covered with the polycrystalline silicon layer 11, no contamination or change in absorption thickness of the gate oxide film 7 occurs (FIG. 2(a)).

Q M OS transistor gate electrode 11'11
The metals mentioned above can also be used as ``.

Other effects obtained from this embodiment are listed below.

■ Current amplification factor of NPN bipolar transistor (hr
s) becomes easier to control. This is the emitter region 12'
This is because the main heat treatment after the formation heat treatment (1000° C., 30 minutes) is only the heat treatment for forming the source region 18 and drain region 18 of the PMOS transistor. The diffusion coefficient of boron is approximately twice as large at 1000° C. as the diffusion coefficient of arsenic used to form the emitter region 12', for example to obtain a junction depth of 0.4 μm.

950°C for about 20 minutes is sufficient, and 1000'C first.
, has almost no effect on the impurity distribution of arsenic formed in 30 minutes.

■ Emitter region 12 of NPN bipolar transistor
It is possible to share the impurity implantation when forming the source region 16 and the drain region 16 of the NMOS transistor with the impurity implantation when forming the source region 16 and the drain region 16 of the NMOS transistor.
Figure (11)).

(2) Photoetching for forming the source region 18 and drain region 18 of the PuO8 transistor and photoetching for forming the emitter electrode 11'' of the NPN bipolar transistor can be performed in the same process, simplifying the process (FIGS. 2(] and 3)).

[F] PuO2) - The formation of the source region 18 and drain region 18 of the transistor and the formation of the external base region 18' of the NPN bipolar transistor can be performed in the same impurity introduction step, simplifying the process (see FIG. 2 (1, 4)). )).

- In the embodiments of the present invention, a semiconductor device in which a CMOS transistor and an NPN bipolar transistor are formed on the same semiconductor substrate has been described as an example, but the present invention is not limited to this, and It is easy to understand that it can be applied to semiconductor devices in which general MiS transistors such as transistors and NMOS transistors, and general bipolar elements such as PNP bipolar transistors and PNPN thyristors are formed on the same semiconductor substrate. Will.

The present invention is not limited to these embodiments and can be modified in various ways within the scope of the spirit of the invention.

〔Effect of the invention〕

As described above, according to the present invention, a high-performance bipolar transistor and a highly reliable MOS transistor can be realized at the same time.

[Brief explanation of drawings]

FIG. 1 is a diagram and a schematic cross-sectional view showing the main steps of a semiconductor device in which a conventional NPN bipolar transistor and a CMo5 transistor are formed, and FIG. 2 is a diagram showing an NPN bipolar transistor and a CMOS according to an embodiment of the present invention.
FIG. 2 is a diagram and a schematic cross-sectional view showing the main steps of a semiconductor device in which a transistor is formed. DESCRIPTION OF SYMBOLS 1... Semiconductor base, 7... Gate oxide film, 11,1
9°19', 19'...polycrystalline silicon, 11'
・・Gate electrode of PMO5i-transistor, 11′・・
・Gate electrode of NMOS transistor, 11'''...
NPN/<Ibo-62:

Claims (1)

[Claims] 1. A semiconductor device in which at least an MIS transistor and a bipolar transistor are formed on the main surface of a semiconductor substrate, wherein the gate electrode of the MIS transistor is a layer containing polycrystalline silicon containing phosphorus, and A semiconductor device characterized in that an emitter electrode of a bipolar transistor is a layer containing polycrystalline silicon containing arsenic. 2. A method for manufacturing a semiconductor device in which at least an MIS transistor and a bipolar transistor having at least one electrode made of polycrystalline silicon are formed on the main surface of a semiconductor substrate, at least (1) on the main surface of the semiconductor substrate. (2) forming a gate electrode layer having polycrystalline silicon containing phosphorus on at least the gate oxide film; (3) selectively removing the gate electrode layer; M.I.
(4) forming an oxide film on at least the surface of the gate electrode; (5) forming a polycrystalline silicon layer containing arsenic on the main surface of the semiconductor substrate; 6) A method for manufacturing a semiconductor device, comprising: selectively removing the polycrystalline silicon layer to form an emitter electrode of the bipolar transistor.