JPH03206620A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03206620A JPH03206620A JP280690A JP280690A JPH03206620A JP H03206620 A JPH03206620 A JP H03206620A JP 280690 A JP280690 A JP 280690A JP 280690 A JP280690 A JP 280690A JP H03206620 A JPH03206620 A JP H03206620A
- Authority
- JP
- Japan
- Prior art keywords
- coat
- wiring
- semiconductor device
- aluminum wiring
- passivation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は半導体装置の製造方法に関し、特に温度サイ
クルによる配線のスライド防止方法を提供するものであ
る。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and in particular provides a method for preventing wiring from sliding due to temperature cycles.
第３図は従来の半導体装置の配線部分の断面図で、図に
おいて、１は半導体基板、２はフィールド酸化膜、３は
層間絶縁膜、４はアルミ配線、５はパッシベーション膜
である。FIG. 3 is a cross-sectional view of a wiring portion of a conventional semiconductor device. In the figure, 1 is a semiconductor substrate, 2 is a field oxide film, 3 is an interlayer insulating film, 4 is an aluminum wiring, and 5 is a passivation film.
従来の半導体装置は図に示す様な断面構造であるが故に
、例えば、アルミ配！Ｉ４の巾が１００μｍ程度と広く
なりチップの外周等に配線されていると、チップが温度
サイクルでモールドからの応力を受け、その為にアルミ
配線４がスライドすることが発生していた。Conventional semiconductor devices have a cross-sectional structure as shown in the figure, so for example, aluminum wiring! When the width of I4 is increased to about 100 μm and wired around the outer periphery of the chip, the chip receives stress from the mold during temperature cycles, which causes the aluminum wiring 4 to slide.
その対策としてアルミ配線４にスリットを設け、スライ
ドを防止することが行なわれた。As a countermeasure, slits were provided in the aluminum wiring 4 to prevent sliding.
しかし、それでもチップサイズが大きくなってきた場合
には、アルミ配線のスライドを防止することが困難であ
った。However, as the chip size increases, it is difficult to prevent the aluminum wiring from sliding.
（発明が解決しようとする課題）
従来の半導体装置は以上のように構威されていたので、
アルミ配線のスライドの防止が困難で特にチップサイズ
が大きくなるにしたがって増大するという問題点を有し
ていた。(Problem to be solved by the invention) Since conventional semiconductor devices were structured as described above,
It is difficult to prevent the aluminum wiring from sliding, and this problem particularly increases as the chip size increases.
この発明は上記のような問題点を解決するためになされ
たもので、チップサイズの大きな基板で安価にかつ簡単
にアルミ配線のスライドを防止した半導体装置の製造方
法を得ることを目的とするものである。This invention was made in order to solve the above-mentioned problems, and the object is to provide a method for manufacturing a semiconductor device that easily and inexpensively prevents aluminum wiring from sliding on a large chip-sized substrate. It is.
この発明に係る半導体装置の製造方法は、アルミ配線に
スリットを設け、さらにパツシベーション膜の上にバッ
ファコートを塗るようにしたものである。A method of manufacturing a semiconductor device according to the present invention includes providing a slit in an aluminum wiring and further applying a buffer coat on a passivation film.
この発明における半導体装置の製造方法は、アルミ配線
にスリットを設け、バツファコートを塗ることにより、
外部からの応力を防ぎアルミスライトを防止する。The method for manufacturing a semiconductor device according to the present invention is to provide a slit in an aluminum wiring and apply a buffer coat.
Prevents stress from the outside and prevents aluminum slite.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図はこの発明の一実施例である半導体装置の完成断
面図、第２図（ａ）〜（ｈ）は第１図の製造工程を示す
各断面図である。なお、図中符号（１）〜（５）は前記
従来のものと同一につき説明は省略する。６はバツファ
コートである。第２図（ａ）に於いて、半導体基板１に
フィールド酸化膜２を形成する。次に（ｂ）図に於いて
、フィールド酸化膜２の上に層間膜３をデボし、（Ｃ）
図に於いて、層問膜３の上にアルミ配線４をスバッタし
、（ｄ）図に於いて、アルミ配線の写真製版を行い、（
ｅ）図でレジスト４１をカバーにしてアルミ配線４をエ
ッチングし、（ｆ）図で、レジスト４１を除去し、（ｇ
）図でアルミ配Ｈ４の上にパッシベーション膜５をデポ
し、（ｈ）図でバッファコート６を塗る。FIG. 1 is a completed sectional view of a semiconductor device according to an embodiment of the present invention, and FIGS. 2(a) to 2(h) are sectional views showing the manufacturing steps of FIG. 1. Note that the symbols (1) to (5) in the drawings are the same as those of the conventional device, and the explanation thereof will be omitted. 6 is a buffer coat. In FIG. 2(a), a field oxide film 2 is formed on a semiconductor substrate 1. As shown in FIG. Next, as shown in (b), the interlayer film 3 is deposited on the field oxide film 2, and (c)
In the figure, the aluminum wiring 4 is spattered on the interlayer film 3, and in the figure (d), the aluminum wiring is photoengraved.
e) In the figure, the aluminum wiring 4 is etched using the resist 41 as a cover. In the figure (f), the resist 41 is removed, and in the figure (g)
) In the figure, a passivation film 5 is deposited on the aluminum wiring H4, and in the figure (h), a buffer coat 6 is applied.
（発明の効果）
以上のようにこの発明によれば、最近の大チップサイズ
化に於いても、アルミ配線をスライドさせることなく使
用でき、又、巾広い温度範囲での使用も可能となる。(Effects of the Invention) As described above, according to the present invention, even with the recent increase in chip size, aluminum wiring can be used without sliding, and it can also be used in a wide temperature range.
第１図はこの発明の一実施例である半導体装置の完成後
の断面図、第２図（ａ）〜（ｈ）は第１図の半導体装置
の製造工程を示す各断面図、第３図は従来の半導体装置
の断面図である。
図に於いて、１は半導体基板、２はフィールド酸化膜、
３は層間脱、４はアルミ配線、５はパッシベーション膜
、６はバッファコート、４１はレジストをボす。
なお、
図中、
同一符号は同一
または相当部分を
示す。FIG. 1 is a cross-sectional view of a completed semiconductor device according to an embodiment of the present invention, FIGS. 2(a) to (h) are cross-sectional views showing manufacturing steps of the semiconductor device of FIG. 1, and FIG. is a cross-sectional view of a conventional semiconductor device. In the figure, 1 is a semiconductor substrate, 2 is a field oxide film,
3 is an interlayer removal, 4 is an aluminum wiring, 5 is a passivation film, 6 is a buffer coat, and 41 is a resist. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
線の上に形成したパッシベーション膜上にバッファコー
トを塗布したことを特徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device, characterized in that a slit is provided in an aluminum wiring, and a buffer coat is applied on a passivation film formed on the aluminum wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP280690A JPH03206620A (en) | 1990-01-09 | 1990-01-09 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP280690A JPH03206620A (en) | 1990-01-09 | 1990-01-09 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03206620A true JPH03206620A (en) | 1991-09-10 |
Family
ID=11539629
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP280690A Pending JPH03206620A (en) | 1990-01-09 | 1990-01-09 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03206620A (en) |
-
1990
- 1990-01-09 JP JP280690A patent/JPH03206620A/en active Pending
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