JPH0320898B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a wiring structure made of a heat-resistant metal in a semiconductor device and a method for forming the same.

As one of the package structures of IC Zener,
Conventionally, there is a double heat sink diode (DHD) structure as shown in FIG. This is an IC
It has a structure in which a semiconductor element 1 constituting a Zener is sandwiched between the large-diameter end faces of a pair of leads 2, a glass tube 3 is inserted, and the glass tube 3 is further sealed by welding. . Further, a bump electrode 4 made of silver is formed on the main surface of the semiconductor element 1, and a silver electrode (not shown) is previously formed on the other surface. These two electrodes face each other and are connected to the lead end face.

By the way, glass sealing is performed at a high temperature of 650°C. For this reason, the wiring layer provided below the bump electrode 4 must be made of a heat-resistant material that can sufficiently withstand the sealing temperature, and conventionally, a titanium (Ti) layer,
It is sequentially stacked and patterned with palladium (Pd) layers. In addition, Pd in the bump electrode formation area
A layer of Ag is provided on the layer by vapor deposition, and then this Ag layer is
After forming a thick Ag plating layer on the layer, the Ag is heated to form a hemispherical shape to form a pump electrode.

However, in such a wiring structure, the thicker the Pd, the greater the strain on the film, which increases the stress on the silicon substrate, causing the silicon substrate (in wafer form) to warp or the wiring layer to peel off. do. Furthermore, as the thickness of the wiring layer increases, the reaction with silicon progresses in the portions that are in direct contact with the silicon substrate, destroying the PN junction provided on the surface layer of the silicon substrate.

For this reason, the thickness of the wiring layer is, for example, 4000 to 5000.
It must be made as thin as 〓. However, when the film thickness is this thin, there are drawbacks such as wire breakage at stepped portions or a small tolerance value for surges due to the small current capacity.

Therefore, in order to increase the thickness of the wiring layer, Ti,
One possible method is to form an Ag layer on a wiring layer made of Pd.

However, in this method, the Ag layer tends to be side-etched by the etching solution used when patterning the Ag layer. For this reason, a so-called "just etch" is used for etching time, in which etching ends when the Ag layer is patterned.
There is a risk that Ag may remain in undesired areas due to nonuniform layer thickness, etc., and etching processing of Ag is difficult and the yield is low. Also, the wiring layer is CVD
(Chemical vapor deposition) Often covered with an insulating film,
In this case, since the difference in thermal expansion coefficient between the insulating film and Ag is large, cracks occur in the insulating film due to thermal history, and the original passivation effect of providing the insulating film is weakened.

Therefore, an object of the present invention is to increase the current capacity and prevent disconnection at the stepped portion by increasing the thickness of the heat-resistant wiring layer.

Another object of the present invention is to provide a method for forming a thick film heat-resistant wiring layer that is simple and has a high yield.

Furthermore, another object of the present invention is to provide a heat-resistant wiring structure in which cracks are difficult to form in an insulating film provided on a heat-resistant wiring layer.

In order to achieve such an object, the present invention sequentially forms a Ti layer and a Pd layer or a Pt layer in a predetermined pattern directly or indirectly through an insulating film on the main surface of a semiconductor substrate, and then covers the entire main surface. form an Ag layer on
Thereafter, Ag, Ti, Pd, or Pt are alloyed by heat treatment, and the unalloyed Ag is removed by etching to form a thick heat-resistant wiring layer. Explain.

Figure 2 shows a DHD type IC according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view of the device at each step showing an example of forming a wiring structure in a Zener device.

As shown in FIG. It is formed based on the N-type silicon substrate 6 provided on the side. That is, predetermined impurities are diffused into predetermined regions of the epitaxial layer 5 to form a P ⁺ type region, a P type region, and an N type region, and the emitter region 8, base region 9, and collector region 10 of the transistor 7. And an anode region 12 and a cathode region 13 of a Zener diode 11 are formed, respectively. Further, the main surface of the silicon substrate 6 is covered with an insulating film 14 except for the contact regions facing the emitter/base regions 8, 9 and the anode/cathode regions 12, 13. The contact region is formed by partially etching away the insulating film 14 to provide a contact hole 15.

When forming a heat-resistant wiring structure in such an element 16, as shown in FIG.
A layer 17 and a Pd layer 18 are formed by vapor deposition, and a wiring layer having a desired shape is formed by a commonly used photoetching technique. Thereafter, vapor deposition is performed again to cover the entire main surface of the silicon substrate 6 with the Ag layer 19.
This Ag layer 19 is thick, for example, 5000 Å, and the Ti layer 1
7. The thickness including the Pd layer 18 is, for example, 10,000 Å
(For example, Ti layer 1
7 is 2200 Å, Pd layer 18 is 3500 Å).

Next, this element 16 is heat-treated at 450° C. for 10 minutes to form a ternary alloy of Ti, Pd, and Ag, thereby forming an alloy layer 20. The alloy layer 20 is shown in FIG.
As shown in , it is formed to a depth of about 4500 Å from below the Ag layer. Note that if the treatment time is increased, alloying will reach the surface of the Ag layer. Also,
Similarly, there may be some unalloyed portions below the bottom Ti layer, but for convenience of explanation, the entire layer is illustrated as an alloy layer. In addition, the alloying treatment temperature of 450°C is higher than the upper limit temperature of 550°C, at which the silicide formed on the surface layer of the silicon substrate becomes deep, or silicon penetrates into the upper Pd layer 18 and an alloy layer containing silicon is not formed. Decided. As a result, this alloying treatment does not destroy the junction, even if it is a shallow PN junction, and can prevent an increase in leakage current due to the presence of the silicon-containing alloy layer.

Next, as shown in Figure d, the Ag layer 19 is removed by etching, and a final patching film 21 is formed in a desired shape on the main surface of the silicon substrate 6, and bumps made of silver are formed on the main surface. A DHD type IC Zener element 16 is manufactured by forming an electrode 22 made of silver on the other side of the electrode 4.

An element having a wiring layer made of such a Ti-Pd-Ag alloy layer 20 has the following effects.

(1) Since the thickness of the wiring layer is approximately 10,000 Å,
The step coverage at the stepped portion is improved, preventing wire breakage, and since the current capacity is increased, the tolerance against surges is large, and the yield can be improved.

(2) Conventionally, when forming a three-layer wiring structure of Ti, Pd, and Ag, patterning the Ag layer requires a photolithographic process with high man-hours and low yield. In this example, patterning can be achieved by etching without heat treatment or masking, which reduces the number of man-hours and improves yield.

(3) Since the alloy layer is acid resistant (proven in experiments), it can prevent etching of the Ti layer with low etching resistance that may remain in the inner underlying layer.

(4) The wiring layer made of an alloy layer has a thermal expansion coefficient similar to that of an insulating film such as CVD-PSG (phosphorus glass). Therefore, undesirable phenomena such as cracks in the insulating film on the wiring layer due to thermal stress between the wiring layer and the wiring layer do not occur as in the conventional case.

(5) In this example, since the growth of silicide in the contact region is not large, it can not only be applied to devices with shallow PN junctions, but also
Since the growth of silicide in the parallel direction is small, it is possible to achieve high integration, and conversely, it is also possible to reduce the element size.

Note that the present invention is not limited to the above embodiments. For example, similar effects can be obtained by using Pt (platinum) instead of Pd.

The present invention also relates to semiconductor devices other than DHD structures,
It can also be applied to elements in ICs, etc.

As described above, according to the present invention, since the thickness of the heat-resistant wiring layer is thick, it is possible to prevent disconnection at the stepped portion and increase the current capacity. Furthermore, since the wiring layer has a thermal expansion coefficient similar to that of the insulating film, cracks do not occur in the insulating film on the wiring layer due to thermal stress. As a result, deterioration of device characteristics can be prevented.

Furthermore, according to the method of the present invention, a thick film heat-resistant wiring layer can be formed easily and with high yield.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a DHD type IC Zener, and FIGS. 2 a to 2 d are cross-sectional views showing the state of the device at each step showing a method for forming a heat-resistant wiring layer of an IC Zener device according to an embodiment of the present invention. It is. 4...Bump electrode, 6...Silicon substrate, 7...
...Transistor, 8...Zener diode, 1
4... Insulating film, 16... Element, 17... Ti layer,
18... Pd layer, 19... Ag layer, 20... alloy layer, 21... final packaging film.

Claims (1)

[Claims] 1. The wiring structure formed on the main surface of the semiconductor substrate for configuring the semiconductor element is made of Ti, Pd, Ag or
A semiconductor element characterized by being made of an alloy layer consisting of Ti, Pt, and Ag. 2. The wiring structure formed on the main surface of the semiconductor substrate for configuring the semiconductor element is made of Ti, Pd, Ag or
1. A semiconductor device comprising an alloy layer made of Ti, Pt, and Ag, and an insulating film formed on wiring of the alloy layer. 3 Laminating a Ti lower layer and a Pd or Pt upper layer directly or via an insulating film on the main surface of the semiconductor substrate, and forming them into a predetermined pattern, and an Ag layer covering the entire main surface of the semiconductor substrate. a step of forming Ag in the Ag layer and Pd in the lower layer of the Ag layer or
A heat treatment process in which Pt and Ti react with each other to form a ternary alloy, and
A method for forming a semiconductor device, comprising the step of etching and removing an Ag layer.