JPH0320902B2 - - Google Patents
Info
- Publication number
- JPH0320902B2 JPH0320902B2 JP58018799A JP1879983A JPH0320902B2 JP H0320902 B2 JPH0320902 B2 JP H0320902B2 JP 58018799 A JP58018799 A JP 58018799A JP 1879983 A JP1879983 A JP 1879983A JP H0320902 B2 JPH0320902 B2 JP H0320902B2
- Authority
- JP
- Japan
- Prior art keywords
- press
- spring
- spring guide
- hole
- laminate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Rectifiers (AREA)
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体整流装置に用いる平型半導体素
子の積層スタツクの構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to the structure of a laminated stack of flat semiconductor elements used in a semiconductor rectifier.
〔従来技術〕
第1図および第2図は、従来から半導体整流装
置に用いられている平型半導体素子の積層スタツ
クの構造を示す正面図および側面図である。[Prior Art] FIGS. 1 and 2 are front and side views showing the structure of a laminated stack of flat semiconductor elements conventionally used in semiconductor rectifiers.
これらの図において、複数の平型半導体素子1
はその両端に配置された冷却フイン2を介して積
層されると共に、積層端部の一方の冷却フイン2
は絶縁スペーサ3Aおよびバネガイド4を介して
下押え板9との間に配置されたバネ5により押圧
され、他方の冷却フイン2は絶縁スペーサ3Bお
よびスチールボール6を介して上押え板8の中心
部分に配置された加圧ボルト7によつて押圧さ
れ、上押え板8および下押え板9は絶縁ボルト1
0によつて適正な間隔を保ち連結固定されてい
る。また、下押え板9にはL字形の金具12が固
定されると共に、バネガイド4には下押え板9の
中心部分を貫通するロツド11が固定されてお
り、加圧ボルト7を回転させてスチールボール6
を介して絶縁スペーサ3Bを押圧すると平型半導
体素子1および冷却フイン2はバネ5の反力によ
つて圧接され、この時の圧接力はロツド11の先
端と金具12との間隙13を測ることによつて検
知できるように構成されている。 In these figures, a plurality of flat semiconductor elements 1
are stacked with cooling fins 2 disposed at both ends thereof, and one cooling fin 2 at the stacked end.
is pressed by a spring 5 disposed between it and the lower press plate 9 via an insulating spacer 3A and a spring guide 4, and the other cooling fin 2 is pressed against the center part of the upper press plate 8 via an insulating spacer 3B and a steel ball 6. The upper presser plate 8 and the lower presser plate 9 are pressed by the insulating bolt 1.
0, they are connected and fixed at appropriate intervals. Further, an L-shaped metal fitting 12 is fixed to the lower presser plate 9, and a rod 11 passing through the center of the lower presser plate 9 is fixed to the spring guide 4. ball 6
When the insulating spacer 3B is pressed through the insulating spacer 3B, the flat semiconductor element 1 and the cooling fin 2 are pressed together by the reaction force of the spring 5, and the pressing force at this time is measured by the gap 13 between the tip of the rod 11 and the metal fitting 12. It is configured so that it can be detected by
従つて、このような構成の積層スタツクにおい
ては、ロツド11の先端と金具12との間隙13
を管理することにより、平型半導体素子1の適正
な圧接力を管理することができる。例えば、素子
1の劣化等によりこれを交換する場合は、バネ5
の反力がなくなるまで加圧ボルトを弛めることに
より素子1の交換ができる状態となり、交換後は
間隙13が規定値に達するまで加圧ボルト7を締
付けることにより、特別な圧力計等を用いずに素
子交換前の圧接状態と同じにすることができる。 Therefore, in a laminated stack having such a structure, the gap 13 between the tip of the rod 11 and the metal fitting 12 is
By managing this, it is possible to manage the appropriate pressure contact force of the flat semiconductor element 1. For example, when replacing element 1 due to deterioration, spring 5
By loosening the pressure bolt until the reaction force disappears, the element 1 can be replaced, and after replacement, by tightening the pressure bolt 7 until the gap 13 reaches the specified value, the element 1 can be replaced without using a special pressure gauge, etc. The pressure welding state can be the same as before replacing the element.
しかしながら、このような構造においては加圧
ボルト7および金具12、ロツド11が押え板
8,9より外側に突出しているため、このような
積層スタツクを多数使用する大容量半導体整流装
置では装置全体の寸法が大きくなり不経済になつ
てしまうという欠点があつた。 However, in such a structure, the pressure bolt 7, metal fitting 12, and rod 11 protrude outward from the holding plates 8 and 9, so in a large-capacity semiconductor rectifier that uses a large number of such laminated stacks, the entire device is The drawback was that it became large and uneconomical.
本発明の目的は、半導体整流装置全体の形状を
小形化し得る積層スタツクを提供することにあ
る。
SUMMARY OF THE INVENTION An object of the present invention is to provide a laminated stack that can reduce the size of the entire semiconductor rectifier device.
本発明は加圧ボルトおよび隙間測定部を押え板
の内側に配置するようにしたものである。
In the present invention, the pressure bolt and the gap measuring section are arranged inside the holding plate.
第3図〜第5図は本発明の一実施例を示す図で
あつて、第3図は積層スタツクの正面図、第4図
はその側面図、第5図はバネガイドの平面図をそ
れぞれ示している。
3 to 5 are views showing an embodiment of the present invention, in which FIG. 3 shows a front view of a laminated stack, FIG. 4 shows a side view thereof, and FIG. 5 shows a plan view of a spring guide. ing.
第3図および第4図において、平型半導体素子
1、冷却フイン2、絶縁スペーサ3A,3Bは、
従来と同様に上押え板8と下押え板9との間に絶
縁ボルト10によつて一直線上に積層され、絶縁
スペーサ3A,3Bはバネガイド4およびスチー
ルボール6を介して加圧ボルト7とバネ5とによ
つて押圧されている。 In FIGS. 3 and 4, the flat semiconductor element 1, the cooling fins 2, and the insulating spacers 3A, 3B are
As in the past, the upper holding plate 8 and the lower holding plate 9 are stacked in a straight line with insulating bolts 10, and the insulating spacers 3A and 3B are connected to the pressure bolt 7 and the spring through the spring guide 4 and the steel ball 6. 5 and is pressed by.
しかし、ここでの加圧ボルト7はその頭部が上
押え板8の内側になるように該押え板8に螺合さ
れ、かつその頭部には円錘状の切込みが設けられ
てスチールボール6を絶縁スペーサ3Bとの間で
確実に挾持するように構成されている。 However, the pressure bolt 7 here is screwed into the upper presser plate 8 so that its head is inside the upper presser plate 8, and the head is provided with a conical notch so that the steel ball 6 and the insulating spacer 3B.
一方、バネガイド4には第3図および第5図で
示すようにその中心部分を軸方向に貫通する貫通
孔14が設けられ、下押え板9に固定されかつ該
板9の内側に突出したロツド11をこの貫通孔1
4に貫通させ、バネガイド4の中心部分に形成さ
れた凹部15においてロツド11の先端と絶縁ス
ペーサ3Aとの間隙13を測定できるように構成
されている。 On the other hand, as shown in FIGS. 3 and 5, the spring guide 4 is provided with a through hole 14 passing through its center in the axial direction, and a rod fixed to the lower holding plate 9 and protruding inside the plate 9. 11 into this through hole 1
4, and is configured such that the gap 13 between the tip of the rod 11 and the insulating spacer 3A can be measured in a recess 15 formed in the center of the spring guide 4.
従つて、このような構造においては加圧ボルト
7を回転させることによつて素子1および冷却フ
イン2をバネ5の反力によつて適切な圧接力で圧
接させることができる。そして、その圧接力は下
押え板9の内側に突出したロツド11の先端と絶
縁スペーサ3Aとの間隙13を測定することによ
つて検知でき、また圧接力は上押え板8の内側に
ある加圧ボルト7の頭部を回転させることによつ
て調整できる。すなわち、従来と同様の機能を得
ることができる。しかし、ここでは加圧ボルト7
およびバネ5のたわみ量測定部に相当する間隙測
定部を上押え板8と下押え板9の内側に配置した
ため、長軸方向の最大寸法を小さくすることがで
きる。 Therefore, in such a structure, by rotating the pressure bolt 7, the element 1 and the cooling fin 2 can be brought into pressure contact with each other with an appropriate contact force by the reaction force of the spring 5. The pressure contact force can be detected by measuring the gap 13 between the tip of the rod 11 protruding inside the lower holding plate 9 and the insulating spacer 3A, and the pressure contact force can be detected by applying pressure inside the upper holding plate 8. Adjustment can be made by rotating the head of the pressure bolt 7. In other words, the same functions as conventional ones can be obtained. However, here the pressure bolt 7
Since the gap measuring section corresponding to the deflection measuring section of the spring 5 is arranged inside the upper holding plate 8 and the lower holding plate 9, the maximum dimension in the long axis direction can be reduced.
以上の説明から明らかなように本発明によれ
ば、積層スタツクの長軸方向の最大寸法を小さく
することができ、半導体整流装置における取付け
占有空間は小さくて済み、装置全体の形状を小形
化することができる。また、長軸方向の最大寸法
はバネの圧接力にばらつきがあつても上押え板と
下押え板との距離によつて定まるため、取付け位
置の設計に際してバネの圧接力のばらつきを考慮
しなくて済み、設計時の取扱いが便利になるなど
の効果がある。
As is clear from the above description, according to the present invention, the maximum dimension of the laminated stack in the long axis direction can be reduced, the space occupied by the semiconductor rectifier can be reduced, and the overall shape of the device can be made smaller. be able to. In addition, even if the spring pressure force varies, the maximum dimension in the long axis direction is determined by the distance between the upper and lower press plates, so variations in spring pressure force should not be taken into account when designing the mounting position. This has the effect of making handling easier during design.
第1図および第2図は従来における積層スタツ
クの構造を示す正面図および側面図、第3図およ
び第4図は本発明による積層スタツクの一実施例
を示す正面図および側面図、第5図はバネガイド
の構造を示す平面図である。
1……平型半導体素子、2……冷却フイン、3
A,3B……絶縁スペーサ、4……バネガイド、
5……バネ、6……スチールボール、7……加圧
ボルト、8……上押え板、9……下押え板、10
……絶縁ボルト、11……ロツド。
1 and 2 are a front view and a side view showing the structure of a conventional laminated stack, FIGS. 3 and 4 are a front view and a side view showing an embodiment of a laminated stack according to the present invention, and FIG. FIG. 2 is a plan view showing the structure of a spring guide. 1... Flat semiconductor element, 2... Cooling fin, 3
A, 3B...Insulating spacer, 4...Spring guide,
5... Spring, 6... Steel ball, 7... Pressure bolt, 8... Upper holding plate, 9... Lower holding plate, 10
...Insulation bolt, 11...rod.
Claims (1)
積層し、この積層体を所定間隔で対向配置させた
一対の押え板の間に一方の前記押え板に形成され
た加圧ボルトおよび他方の前記押え板に形成され
た圧接バネによつて圧接し、その圧接力を前記圧
接バネのたわみ量によつて測定する測定部を備え
た半導体整流装置用積層スタツクにおいて、前記
加圧ボルトはその頭部を前記積層体と当接する側
に配置させて前記押え板に螺合させているととも
に、前記測定部は前記圧接バネと前記積層体との
間に配置されかつ中心軸上に形成された孔および
側面に前記孔の一部内を比較的広い視野で目視し
得る窓とが形成されたバネガイドと、前記他方の
押え板の前記積層体側に植設されかつ前記バネガ
イドの孔を挿通してその先端が前記孔の一部内に
位置づけられているロツドとからなつていること
を特徴とした半導体整流装置用積層スタツク。1 A plurality of flat semiconductor elements are stacked together via a cooling fan, and the stacked bodies are arranged facing each other at a predetermined interval between a pair of presser plates, and a pressure bolt formed on one of the presser plates and the other presser plate. In the laminated stack for a semiconductor rectifier device, the stack includes a measurement unit for press-contacting with a press-contact spring formed in the press-contact spring and measuring the press-contact force based on the amount of deflection of the press-contact spring. The measuring section is disposed on the side that contacts the laminate and is screwed into the presser plate, and the measuring section is disposed between the pressure contact spring and the laminate and is formed in a hole formed on the central axis and on the side surface. A spring guide is provided with a window that allows the inside of a portion of the hole to be visually viewed from a relatively wide field of view, and the spring guide is installed on the side of the laminate of the other presser plate and is inserted through the hole of the spring guide so that the tip of the spring guide is inserted into the hole. 1. A laminated stack for a semiconductor rectifier, characterized by comprising a rod located within a part of the stack.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58018799A JPS59145558A (en) | 1983-02-09 | 1983-02-09 | Laminated stack for semiconductor rectifying device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58018799A JPS59145558A (en) | 1983-02-09 | 1983-02-09 | Laminated stack for semiconductor rectifying device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59145558A JPS59145558A (en) | 1984-08-21 |
| JPH0320902B2 true JPH0320902B2 (en) | 1991-03-20 |
Family
ID=11981632
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58018799A Granted JPS59145558A (en) | 1983-02-09 | 1983-02-09 | Laminated stack for semiconductor rectifying device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59145558A (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS512931A (en) * | 1974-06-28 | 1976-01-12 | Hitachi Ltd | SEIRYUSOCHI |
| JPS56108265U (en) * | 1980-01-21 | 1981-08-22 | ||
| JPS5712748U (en) * | 1980-06-27 | 1982-01-22 | ||
| JPS596851U (en) * | 1982-07-05 | 1984-01-17 | 日本電気株式会社 | flat semiconductor device |
-
1983
- 1983-02-09 JP JP58018799A patent/JPS59145558A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59145558A (en) | 1984-08-21 |
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