JPH0320932B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a cyclic code generation method for generating a cyclic code of arbitrary bit length using a general-purpose memory.

(Prior art) Conventionally, to generate a cyclic code, data in a general-purpose memory having n-bit (e.g., 8-bit) parallel output is loaded into a P/S converter (parallel/serial converter), and the data is synchronized with the clock timing. The method used was to serially output the loaded data one bit at a time. When the n-bit serial data has been output, the address counter for setting the address of the memory is incremented by one, and the data is loaded again, so that the previously stored data is sequentially output. Furthermore, when the final address at which data is stored is reached, the address counter is reset to the initial value and the first data is repeatedly output.

By the way, one of the uses of this type of cyclic code is to generate random data, and in this case,
By storing irregular data in memory in advance, a continuous pulse train of random data can be obtained. However, in the above configuration, the serial data output from the P/S converter is always in units of n bits, so serial data with a bit length that is a multiple of n is repeated, and when viewed over a long period, it appears random. The drawback was that I was not sexually satisfied.

Furthermore, even for applications other than those mentioned above, a cyclic code of arbitrary bit length is often required.

(Object of the Invention) The present invention has been proposed in view of the above points, and its purpose is to provide a cyclic code generation method that can generate a cyclic code of any bit length with a simple configuration. It is about providing.

(Structure of the Invention) The present invention will be described in detail below with reference to the drawings showing examples.

FIG. 1 shows the configuration of a cyclic code generator embodying the present invention. To explain the configuration in the figure, the data input terminal D _IN of the P/S converter (parallel/serial converter) 1 is connected to the data output terminal D _OUT (consisting of n bits) of the memory 2. The address output terminal A _OUT of the address counter 3 is connected to the address input terminal A _IN of the address counter 3, and the memory contents corresponding to the address given from the address counter 3 are given from the memory 2 to the P/S converter 1. There is. here,
The P/S converter 1 has the function of outputting parallel data input to the data input terminal D _IN as a serial data string from the output terminal Q. Specifically, the shift/load control input terminal S/L is When the clock is input to the clock input terminal CK when it is at one level, the n-bit data applied to the data input terminal D _IN is loaded at the positive rising edge (at this time,
The first bit of the loaded data appears at the output terminal Q. ), on the other hand, when a clock is input to the clock input terminal CK while the shift/load control input terminal S/L is at a high level, the loaded data is sequentially shifted and output.

Next, the output terminal Q _D of the ring counter 4 is connected to the clock input terminal CK of the address counter 3, and the output terminal Q _H is connected to the shift/load control input terminal S of the P/S converter ₁ via the inverter I1. /L is connected. Further, a signal inverted from the clock applied to the P/S converter ₁ is applied to the clock input terminal CK of the ring counter 4 via the inverter I2.

On the other hand, the address output of address counter 3
A _OUT is led to a comparison circuit 6, and it is determined whether it matches the setting input given by the setting circuit 5. Further, the output of the ring counter 4 is also appropriately selected and led to the comparison circuit 8, where it is determined whether it matches the setting input given by the setting circuit 7. Next, the output signal _S1 indicating a match from the comparator circuit 6 is applied to the load terminal LD of the address counter 3, and together with the output signal _S2 indicating a match from the comparator circuit 8, is applied to the input terminal of the AND gate _G1 . ing. Note that the load terminal LD is used to load data that presets the address output A _OUT of the address counter 3 to a predetermined value, and if a clock is input when the load terminal LD becomes high level, the data input is It loads the value given to the terminal D _IN . In this example, the data input terminal D _IN is set to ground level, so when loading is performed, the address output of address counter 3 is
A _OUT is initialized to zero.

Next, _the output O _G1 of the AND gate G ₁ is applied to the input terminal of the OR gate G 3 together with the output O _G2 of the NOR gate G ₂ , and the output of the OR gate G ₃ is applied to the input terminal A of the ring counter 4. Here, the input terminal A is used to set the first stage of the internal shift register that constitutes the ring counter 4, and when a clock is input while the input terminal A is at a high level, the output Q _A of the first stage shift register becomes " 1”
Turn to Further, the ring counter 4 is slightly different from a normal ring counter in that the NOR of each output except the signal Q _H is applied to the input terminal A of the ring counter 4 in OR logic with the comparator output. Therefore,
If a high level is output to the comparator output and a clock is applied while there is a stage at a high level in the intermediate shift register, two stages at a high level will appear at the same time.

In the illustrated example, the ring counter 4 is assumed to be 8 bits, and its output _QD provides a clock to the address counter 3, and the output _QH provides shift/load control to the P/S converter ₁ via the inverter I1. Although the signal S/L is provided, the connection is not limited to this connection, and even if other terminals of the ring counter 4 are used, the relative position of the timing will only change, and the basic operation will be changed. There is nothing that will change.

FIG. 2 shows signal waveforms at each part in FIG. 1, and the operation will be explained below with reference to FIG. 2.
Note that FIG. 2A shows normal operation without reducing the number of bits, and FIG. 2B shows the operation when the number of bits is reduced.

In FIG. 2, CK _CNT represents the clock applied to ring counter 4, and CK _P/S represents the clock applied to P/S converter 1, and both are inverted from each other by inverter _I2 . Therefore, the positive rising operating point is shifted by half a cycle. In addition, Q _A to Q _H indicate the output of the shift register of each stage of the ring counter 4,
In this example, an 8-bit one is used. In addition,
This number of bits corresponds to the number n of bits of the parallel data output of the memory 2.

In addition, A _OUT is the address output of the address counter 3, S ₁ is a signal indicating a match in the comparison circuit 6, S ₂ is a signal indicating a match in the comparison circuit 8, and O _G1 is the AND (logical product) of the signals S ₁ and S ₂ . ), O _G2 is the output signal of NOR gate G ₂ indicating the NOR of each output except output Q _H of ring counter ₄ , O _G3
is an OR gate that indicates the OR of signal O _G1 and signal O _G2
Output signal of _G3 , S/L is shift/load control signal given to P/S converter 1, OUT is P/S
This is serial data output from the converter 1.

Therefore, in _the normal operation in which the number of bits is not shortened as shown in _FIG . advances one step. When a high level signal appears at the output _QH , a low level signal is applied to the shift/load control input terminal S/L of the P/S converter ₁ via the inverter I1, and the immediately following clock signal CK The data output D _OUT of memory 2 is loaded into P/S converter 1 at the rising edge _{of P/S} . At this time, the first bit of the loaded data appears at the output terminal OUT of the P/S converter 1, and then every time the clock CK _P/S is input, n bits of data are sequentially input.
Outputs serially to the output terminal OUT. Also,
When the above output Q _H becomes high level, the input terminal A of the ring counter 4 is passed through the OR gate G ₃ .
A high level signal is applied to the clock CK _CNT , and immediately after that, a high level signal is set in the first stage shift register of the ring counter 4, and the ring counter 4 returns to its original state. Thereafter, these operations are repeated to sequentially convert the parallel data stored in the memory 2 into serial data and send it out. Furthermore, when the address output A _OUT of the address counter 3 reaches the set value given by the setting circuit 5, a signal is output from the comparison circuit 6, and the load terminal LD of the address counter 3 becomes high level.
Thereafter, when a clock is applied from the output terminal _QD of the ring counter 4, the address is initialized and data is read out again from address zero.

Next, the case where the number of bits in FIG. 2B is shortened will be explained. For the sake of explanation, it is assumed that the set value of the setting circuit 5 is 3F (in hexadecimal notation), and that the set value of the setting circuit 7 is the second bit from the end.

When the address output A _OUT of the address counter 3 reaches 3F at time t ₁ , the comparator circuit 6 detects a match with the set value and outputs a high level signal, and the load terminal LD of the address counter 3 and the AND One end of gate _G1 becomes high level. Thereafter, at time _t2 , when the output _QG of the second to last bit of the ring counter 4 becomes high level, the comparator circuit 8 detects a match with the set value and outputs a high level signal, and the AND gate _G1 is activated. Since both inputs are high level, a high level signal is output,
A high level signal is applied to the input terminal A of the ring counter 4 via the OR gate _G3 .

In this state, when the clock CK _CNT rises at time _t3 , a high level signal is set in the first stage shift register of the ring counter 4, and the signal _QA becomes high level earlier than usual. As mentioned above, the ring counter 4 does not have the output of the shift register at the final stage applied to the first stage, unlike the commonly known ring counters.
If a high level signal is applied to input terminal A and a clock is applied while there is a stage at high level in the intermediate shift register, two stages at high level will appear at the same time. i.e. the signal
The value of signal Q _G just before Q _A becomes high level is the signal
At the same time as Q _A is set to high level, output Q _H
At this point, both outputs Q _A and Q _H are at high level.

When a high level signal appears at the output _QH , a low level signal is applied to the shift/load control signal terminal S/L of the P/S converter ₁ via the inverter I1, and the immediately following clock signal is applied to the shift/load control signal terminal S/L of the P/S converter 1. The data output D _OUT of memory 2 is set to P/S by the rising edge of CK _P/S.
The data is loaded into converter 1, and then every time the clock CK _P/S is input, the data is serially output to the output terminal OUT. However, during this period, as mentioned above, the output Q _A of the ring counter 4 is set to a high level one clock earlier, so the next data load timing in the P/S converter 1 is delayed. Hurry up, waddle,
At time _t4 , although only seven pieces of data have been sent, the next data is loaded, and the number of bits of the serial data to be sent is reduced.

In other words, the comparison circuit 6 sets the set value (setting circuit 5)
When the comparator circuit 8 detects a match with the set value (setting circuit 7), the P/S converter 1
A constant signal is output to the shift/load control terminal of the P/S converter 1 earlier than usual, and the next data is loaded before the P/S converter 1 completes serial transfer of all n bits.

Similarly, it is possible to shorten the code to 2 to 7 bits, and in conjunction with selection of the set value for the address output of the address counter 3, it is possible to generate a cyclic code of any bit length.

(Effects of the Invention) As described above, in the present invention, n-bit parallel data corresponding to the address given from the address counter is loaded from the memory to the P/S converter, and the In a code generator that serially transmits bit data one by one and repeats this process, the first comparison means detects that the address counter for setting the address of the memory reaches a predetermined value; and second comparison means for detecting that the serially outputted data has reached a predetermined position in n bits, and the first comparison means detects that the address counter has reached a predetermined value. In this case, the address counter is initialized, and when the first and second comparison means operate simultaneously, the first and second comparison means are initialized.
Based on the output signal from the second comparison means, a constant signal is output to the shift/load control terminal of the P/S converter earlier than usual, and before the serial transfer of all n bits is completed in the P/S converter. By loading the following data into the code, it is possible to generate a cyclic code of any bit length with a simple configuration, and it can be applied to various fields such as generation of random data.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment embodying the present invention, and FIG. 2 is a time chart showing the operation of the same circuit. 1... P/S converter, 2... Memory, 3... Address counter, 4... Ring counter, 5, 7
... Setting circuit, 6, 8 ... Comparison circuit, G ₁ ... AND gate, G ₂ ... Noah gate, G ₃ ... OR gate, I ₁ , I ₂ ... Inverter.

Claims (1)

[Claims] 1 Load n-bit parallel data corresponding to the address given from the address counter from memory to the P/S converter, serially send out the n-bit data one bit at a time in n cycles of the clock, and repeat this process. The code generator includes a first comparison means for detecting that the address counter for setting the address of the memory has reached a predetermined value, and a first comparison means for detecting that the serially outputted data is at a predetermined position among the n bits. and second comparison means for detecting that the address counter has reached a predetermined value, and the first comparison means initializes the address counter when it detects that the address counter has reached the predetermined value, and When the comparing means operate simultaneously, a constant signal is outputted to the shift/load control terminal of the P/S converter earlier than usual based on the output signals from the first and second comparing means,
A cyclic code generation method characterized in that the next data is loaded before serial transfer of all n bits is completed in a P/S converter.