JPH03210486A - semiconductor test equipment - Google Patents

Abstract

PURPOSE:To reduce the load of a person preparing a device test program by changing over the timing edges from respective timing edge generators to a section judging strobe, an intermediate value judging strobe and an edge judging strobe in synchronous relation to the test cycle of a device test by a pin control signal. CONSTITUTION:An HI judgement exclusive timing edge generator 12a for judging the output of a semiconductor element (device) to be tested, an LO judgement exclusive timing edge generator 12b and a pin control signal generator 5 outputting a pin control signal are mounted. The timing edges from the timing edge generators 12a, 12b are changed over to a section judging strobe, an intermediate value judging strobe and an edge judging strobe in synchronous relation to the test cycle of a device test only by the pin control signal from the pin control signal generator 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor testing device for testing the logical characteristics of a semiconductor element.

[Conventional technology]

FIG. 2 is a block diagram showing a conventional semiconductor testing device. In the figure, 1 is an original oscillator that creates the basic period of the semiconductor test equipment, and 2a is a clock center timing edge generator (hereinafter referred to as [clock set TG) that creates the input waveform to the semiconductor device under test (hereinafter referred to as ``device'').
The same <2b is a clock reset timing edge generator (hereinafter referred to as "clock recent TGJ").
, 2c, 2d are strobe timing edge generators (hereinafter referred to as "strobe TGJ") for generating timing edges for judgment, and 3 is a strobe timing edge generator for generating timing edges for judgment.
1", a test pattern data memory that stores "0"data; 4, an address controller that controls the address of the test pattern data memory 3; and 5, a bin controller that specifies whether each test bin is an input bin or a judgment bin. It is a signal generator.

Furthermore, f is how to combine edges from each timing edge generator 2a to 2d, data from test pattern data memory 3, and signal p from pin control signal generator 5 (hereinafter referred to as "pin control signal"). This is a formant select signal that specifies which

7 is a format circuit that performs the above combination; 8 is an input waveform forming circuit that generates input waveform pulses from the input waveform rising edges and falling edges output from the format circuit; 9 is an input waveform forming circuit that executes pulse formation of the input waveform forming circuit 8; A driver circuit that makes the amplitude for the input waveform, 10 is a comparator for Hl (high) output that receives the output from the device, 11 is also a comparator for LO (low) output, and 12a is HI
12b is the LO judgment circuit, 12c is the intermediate value (
3 shows a HIZ determination circuit that determines whether the device is in a high impedance state (high impedance state).

Next, the operation will be explained. The basic period signal from the original oscillator 1 is sent to the clock center TG2a and the clock reset T.
The signal is sent to G2b, strobe TG2c, and TG2d, and the address controller 4. Clock reset TG2a and clock reset TG2b, to which the basic period signal is sent, are respectively input to the input waveform input to the device.
・Creates an edge and a reset edge and sends them to the format circuit 7. Furthermore, the strobe TG2c and the strobe TC2d generate a timing edge that determines at which timing the output from the device is determined, and sends the same timing edge to the formant circuit 7.

Further, the address controller 4 sends the test pattern data stored in the test pattern data memory 3 to the format circuit 7 according to the period of the basic period signal sent from the original oscillator l.

In the formant circuit 7, whether each test bin is an input bin to the device (hereinafter referred to as "driver bin"),
Judgment bin (hereinafter referred to as “
A pin control signal p indicates whether the comparator bin is a clock TG2a, 2b or a strobe TG2c.

Select 2d. In the case of a driver bin, the set edge from the clock node TG2a, the reset edge from the clock reset node TG2b, and the test pattern data from the test pattern data memory 3 are generated according to the format select signal f indicating what kind of input waveform to form. By combining these, the edges for the rising point and the edge for the falling point of the input waveform to the device are obtained. From these two edges, an input waveform pulse is created by the input waveform forming circuit 8, converted into a voltage actually used by the driver circuit 9, and output from the tip of the bottle.

If the pin control signal p from the pin control signal generator 5 is a comparator bin, the strobe T
Edges from G2C and strobe TG2d are selected. The pin control signal generator 5 also sends information indicating whether the judgment is edge judgment, window judgment (section judgment), or HIZ judgment. If it is an edge judgment, strobe TG2c or strobe TG2
If the information from the test pattern data memory 3 is "1", either edge of d, or in the case of window determination, the pulse generated from both edges of strobe TG2c and strobe TG2d, is sent to HI@ constant circuit 12a; If it is rOJ, it is sent to the LO determination circuit 12b. Further, in the case of HIZ determination (intermediate value determination), the edge of strobe TC, 2c or strobe TG2d is sent to HIZ determination circuit 12c.

The output from the device is received by the H1 output comparator 10 and the LO output comparator 11, and according to the preset judgment voltage setting value, the HI constant circuit 12a
, LO determination circuit 12b, and H12 determination circuit 2c. Each of the determination circuits 12a to 12c determines whether the signal from each comparator is correct or not based on the timing from the format circuit 7, and if not, error information a, b is sent.
.

Send C to CPU.

[Problem to be solved by the invention]

Conventional semiconductor test equipment is configured as described above, so those who create device test programs must specify test patterns (rlJ, rOJ output, rlj, rOJ judgment, etc.) and formats (input waveform shape, etc.). I had to take this into consideration when programming. In addition, there were problems such as a large number of TGs and a high cost per semiconductor test equipment bin.

The present invention has been made in view of the above points, and its purpose is to replace the format circuit and test pattern data memory of the conventional device (to reduce the burden on those who create test programs, Another objective is to obtain an inexpensive device.

[Means to solve the problem]

In order to achieve such objects, the present invention provides a timing edge generator exclusively for HI constant determination and a timing edge generator exclusively for LO determination for determining the output of a semiconductor device under test, and a pin control signal for outputting a pin control signal. The timing edge from each timing edge generator is switched to an interval judgment strobe, intermediate value judgment strobe, and edge judgment strobe in synchronization with the test cycle of the semiconductor device under test test using only a pin control signal. This is how it was done.

[Effect]

The semiconductor testing apparatus according to the present invention uses a timing edge generator for determining the device output as a timing edge generator dedicated to HI constant and a timing edge generator dedicated to LO determination, and various determinations can be switched only by a pin control signal.

〔Example〕

First, an outline of an embodiment of the present invention will be described.

In this embodiment, the device output judgment timing edge generator is a timing edge generator dedicated to HI constant and a timing edge generator dedicated to LO judgment, and various judgments can be switched only by a pin control signal. In addition, the edge generators for forming the input waveform to the device include a timing edge generator dedicated to the rise of the input waveform, a timing edge generator dedicated to the fall of the input waveform, and a timing edge generator dedicated to the HI constant and a timing edge generator dedicated to the LO determination. It is shared with the controller and can be switched using only a pin control signal.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block system diagram showing an embodiment of a semiconductor testing apparatus according to the present invention. In the figure, l is the original oscillator, 2e is the device input waveform rising timing edge, the wind strobe HI regular start timing edge,
TG that shares the generator of end timing edge at wind strobe LO judgment and timing edge at edge judgment, 2f is device input waveform falling timing edge, start timing edge at wind strobe LO judgment, wind strobe HI fixed end timing edge and edge judgment TG that shares the timing edge generator, 5 is a pin control signal generator, 8 is an input waveform forming circuit, 9 is a driver, 10 is a comparator for H1 output, 11 is a comparator for LO output, 12a is a HI judgment circuit, 12b is the LO judgment circuit, 12c is the HIZ
A determination circuit 13a is an input/output bin selection circuit 1 that selects whether the bin is a driver bin or a comparator bin based on the signal pa from the pin control signal generator 5.
3b is a wind strobe select circuit that selects edge judgment or window judgment based on the signal pb from the pin control signal generator 5; 13c is a HIZ judgment select circuit that selects intermediate value judgment; and 14a. 14b is an Hl window forming circuit that forms a wind strobe during H11 regular time, an L◯ window forming circuit that forms a wind strobe during LO determination, 15
is an OR gate that outputs two signals. Note that the TGs 2e and 2f may be of the same type as a common configuration, or may be of different types for exclusive use.

Next, the operation will be explained. A fundamental periodic signal is sent from the original oscillator 1 to TGa 2 e, TG 2 f and pin control signal generator 5 . TO2e and TG2f to which the basic periodic signal is sent generate edges at preset timings. The signal p from the pin control signal generator 5 generated in synchronization with the basic cycle
When the input/output bin select circuit 13a selects the driver bin at step a, the input waveform forming circuit 8 creates a pulse waveform that starts up at the edge coming out of TG2e and falls down at the edge coming out of TG2f, and this pulse is applied to the driver. 9, it is converted into the voltage of the actual device-powered waveform and exits from the tip of the bottle.

Further, the input/output bin select circuit 13a selects a comparator bin with the signal pa from the pin control signal generator 5, and the wind strobe select circuit 13b also uses the signal pb from the pin control signal generator 5.
selects edge judgment, TG2e and TG2
Edge coming out from f directly passes through or gate 15 and enters HIZI rect 13c. When the HIZ judgment select circuit 13c selects HIZ judgment by the signal pc from the pin control signal generator 5, TG2e or T
The edge from G2f is sent to HIZ judgment time 112c,
If the HIZ judgment select circuit 13C, which performs intermediate value judgment, does not select HIZ judgment, the edge from TG2e is sent to the HI constant circuit 12a, and an H,1 judgment is made at the timing of the edge, and the edge from TG2f is sent to the HI constant circuit 12a. The edge is sent to the LO determination circuit 12b, and LO determination is performed at the timing of the edge. Furthermore, when the wind strobe selection circuit 13b selects the window determination, the HI window forming circuit 14a generates a pulse that rises at the timing of TG2e and falls at the timing of TG2f, and the pulse that rises at the timing of TG2e and falls at the timing of TG2f is generated by the HI window forming circuit 14a, and the pulse is sent to the HI constant circuit 12a or the HIZI constant circuit 12c. Alternatively, a pulse that rises at the timing of TG2f and falls at the timing of TG2e is generated by the LO window forming circuit 14b, and is sent to the LO judgment circuit 12b or the HIZI constant circuit 12c, and the pulse is Perform interval judgment.

〔Effect of the invention〕

As explained above, the present invention includes a timing edge light generator dedicated to HI format determination, a timing edge generator dedicated to LO determination, and a pin control signal generator, and the timing edge from each timing edge generator is controlled by pin control. The formatting circuit and pattern data memory of the conventional device can be eliminated by switching to the interval determination strobe, intermediate value determination strobe, and edge determination strobe using only signals in synchronization with the test cycle of the semiconductor device under test test. Therefore, the device can be made inexpensive and the burden on the device test program creator can be reduced. Furthermore, if the device input waveform timing edge generator is also used in common with both of the above timing edge generators, the device can be made even more inexpensive.

[Brief explanation of drawings]

FIG. 1 is a block system diagram showing an embodiment of a semiconductor testing device according to the present invention, and FIG. 2 is a block system diagram showing a conventional semiconductor testing device. DESCRIPTION OF SYMBOLS 1... Original oscillator, 2e, 2f... Timing edge generator (TG), 5... Pin control signal generator, 8... Input waveform forming circuit, 9... Driver, 1
0... Comparator for H1 output, 11... Comparator for LO output, 12a... HI constant circuit, 12b...
・LO judgment circuit, 12c...) fIZI constant circuit, 13
a... Input/output bin select circuit, 13b... Wind strobe select circuit, 13c... HIZ determination select circuit, 14a... Hl window forming circuit, 14
b...LO window formation circuit, 5...OR gate. Agent Masuo Oiwa

Claims (1)

[Claims] In a semiconductor test device that tests the logical characteristics of a semiconductor device, a timing edge generator dedicated to HI judgment and a timing edge generator dedicated to LO judgment are used to judge the output of the semiconductor device under test, and a pin control signal that outputs a pin control signal. The timing edge from each of the timing edge generators is synchronized with the test cycle of the semiconductor device under test test only by the pin control signal, and the timing edge is generated into an interval judgment strobe, an intermediate value judgment strobe, and an edge judgment strobe. A semiconductor test device characterized by switching to.