JPH0321060A - Optical reading memory device - Google Patents

Abstract

PURPOSE:To form a memory part and an optical output part integrally on one chip as well as speed up reading by providing a conductive film as one end of laminate tunnel switch part in the direction of lamination and an electroluminescence layer formed between said conductive film and an electrode provided on said conductive film. CONSTITUTION:There is provided an electroluminescence layer 17 as an optical output part which can be formed at a low temperature process between a conductive film 3 as one end of a laminate tunnel switch part in the direction of lamination and an electrode 2 provided on said conductive film 3. Hereby, there can simultaneously be formed on one chip the laminate tunnel switch part as a memory part and the electroluminescence layer 17 as the optical output part. Further, since a plurality of the optical reading laminate memory device are integrated two-dimensionally such that the electroluminescence layers 17 of the optical reading laminate memory devices form the same plane, the electroluminescence layers 17 can emit light in a plane by being simultaneously supplied with voltage for high speed reading.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an optically readable memory element that optically reads out information stored in a memory capacitor.

[Conventional technology]

In recent years, with the development of an advanced information society, various information devices have become commonly used, and there is a strong demand for higher performance of memory elements, which are one of the main components of information devices. There is.

On the other hand, recent L'S I in the electronics field
Research and development of technology has been progressing in the direction of ultra-fine technology. However, today, as technological development toward ultra-fine design is reaching its limits, research and development into three-dimensional technology is being carried out with the aim of increasing the density, multifunction, and speed of memory elements.

As a technology for realizing such three-dimensional integrated circuits, SOI (Sioninsulator) using inorganic materials is used.
or ), SIMO
ation by Implanted Oxidant
), silicon-based technology such as ■-V technology that combines Group ■ and Group V materials, and technology that applies organic LB films (ultra-thin films formed by the Langmuir jet method). Various three-dimensional memory elements have been considered.

This type of three-dimensional memory element has a large number of memory cells built three-dimensionally, and has a structure in which a large number of memory cells are formed two-dimensionally on the same substrate, and a large number are stacked in the height direction. doing.

By the way, methods for reading information stored in a memory element include an electrical reading method and an optical reading method that outputs light. In particular, the optical readout method is superior to electrical readout in terms of high speed readout, connectivity with an optical processing system, and ability to be used as a display element. Therefore, conventionally, a memory section and a light output section consisting of a semiconductor diode (LED) or a laser diode (LD) are integrated on one chip, and the electric charge accumulated in the memory section is transferred from the light output section. It was optically read out.

[Problem to be solved by the invention]

However, when a semiconductor diode or a laser diode is used as the light output part of a three-dimensional memory element, it is possible to output light from one point or several points, but it is possible to output light from multiple memory cells arranged two-dimensionally. It was not possible to output light properly. Therefore, there was a problem in that high-speed optical readout was not possible. In addition, semiconductor diodes or laser diodes are made by one process.
Since a high-temperature thermal process of 000° C. or higher is used, there is a drawback that an organic LB film, which is a useful means for creating a three-dimensional memory, cannot be used. Moreover, since the type of substrate is limited to Si wafers, GaP wafers, etc.
A transparent conductive substrate such as ITO cannot be used, and light cannot be output. Therefore, it is necessary to latch the electrically read signal and output it to another discrete optical output element, which is not desirable in terms of making the element more compact.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an optically readable memory element in which a memory section and an optical output section can be integrally formed on one chip, and which can be optically read out two-dimensionally, thereby increasing the speed of reading. There is a particular thing.

[Means to solve the problem]

In order to solve the above problems, the present invention provides a laminated tunnel switch section formed by alternately laminating conductive films and insulating films connected to a charge storage capacitor, and one end of the laminated tunnel switch section in the stacking direction. a pair of electrodes provided on a conductive rise and an insulating film serving as the other end, and a conductive film serving as one end in the stacking direction of the laminated tunnel switch section and the electrode provided on the conductive film. The structure includes an electroluminescent layer.

In order to solve the above problem, the optical readout type stacked memory element according to claim 1 is two-dimensionally integrated, and each electroluminescent layer forms the same plane.

Note that it is desirable to use an injection type organic electroluminescent layer as the electroluminescent layer.

Further, the above insulating film is made of Langmuth 5 It is preferable to form by the Avroziets 1 method.

[Effect]

By taking the above measures, the following effects are achieved.

That is, between the conductive film that forms one end of the stacked tunnel switch section in the stacking direction and the electrode provided on this conductive film,
Since we have provided an electroluminescent layer as a light output section that can be created using a low-temperature process, there will be no adverse thermal effect even if an LB film is used in the tunnel switch section, for example, so that the stacked tunnel switch section as a memory section and the light output section can be used as a memory section. and an electroluminescent layer can be created on one chip.

Further, so that the electroluminescent layers of the optically readable stacked memory element according to claim 1 form the same plane,
Since a plurality of optical readout type stacked memory elements are two-dimensionally integrated, by simultaneously applying a voltage to each electroluminescent layer, it is possible to emit light from the surface and perform high-speed readout.

〔Example〕

6 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic diagram of an optically readable three-dimensional memory element according to this embodiment. This sequential readout type three-dimensional memory element is a stacked memory unit (Xi.Yi. , Zl to Z6) are arranged in a matrix on the same substrate.

In the stacked memory unit, as shown in FIG. 2, a transparent conductive layer 2 as a lower electrode is formed on a transparent substrate 1 made of glass or the like. A laminated tunnel switch section serving as a memory section is formed on this transparent conductive layer 2, in which conductive films 3 to 8 and insulating films 11 to 16 are alternately laminated. An electroluminescent layer (hereinafter referred to as EL layer) 17 as a light output section is formed between the lower conductive film 3 and the transparent conductive layer 2. An upper electrode 18 is provided on the insulating film 16 which is the second most layer of the laminated l/channel switch section.

In addition, capacitors C1 to C6 for charge storage are formed in each of the conductive films 3 to 8 of the laminated tunnel switch section, and (
It is configured such that voltages can be applied independently to C3, C6), (C2, C5), and (CI, C4).

Here, the transparent conductive layer 2 is ITO, SnO2, In2
03+ ZnO: It is formed of one of A, Q, and TiO2, and the insulating films 11 to 16 are formed of organic LB films.

Further, as shown in FIG. 3, the EL layer 17 serving as a light output section is formed by laminating a hole transport layer 21 and an EL light emitting layer 22 on a transparent conductive layer 2 formed on a transparent substrate 1, and further forming an EL layer 22 on a transparent conductive layer 2 formed on a transparent substrate 1.
2, an electrode 23 is provided on top of the electrode 23. Note that the light output section may have a structure in which a MIS type EL layer 24 and an insulating film 25 are laminated on the transparent conductive layer 2, and an electrode 26 is provided on the insulating film 25, as shown in FIG. As shown in FIG. 5, a hole transport layer 21, an EL light emitting layer 22, and an electron transport layer 27 are laminated on the transparent conductive layer 2, and the electron transport layer 27 is further laminated.
It may also be configured such that the electrode 23 is provided thereon.

Since the light output section constructed in this manner utilizes direct injection from the electrode or 1-channel injection light emission, it emits EL light at a low driving voltage of about 1 to 15V. Therefore, it can be directly driven by the charge of the capacitor C1 in the final stage of the stacked memory unit. Specifically, it depends on the output level of capacitor C1, but since the output level is usually about 0.3 to several V, the capacitance of capacitor C1 should be set to 1/2 to 1/3 of the capacitance of capacitor C2 in the previous stage. If you do that,
This means that it can be boosted to several volts to 15 volts and driven directly.

Note that triphenyldiamine derivatives, cyclopentadiene derivatives, phthalocyanine, etc., which have excellent hole injection and transport properties, are suitable for the hole transport layer 21. EL
As the light-emitting layer 22, coumarin, coronene, perylene,
Anthracene, 12-phthaloperinone derivative, tri(
8-hydroxyquinoline) aluminum, etc. are suitable. Further, as the MIS type EL light emitting layer 24, n-yv
r compound (e.g. ZnS, ZnSe, etc.), m-V compound 9? For example, GaP, InP, etc.) are suitable.

The electrode 23 is made of Mg (3.61e V), which has a small work function, in order to facilitate electron injection.
I n (3.85e V), S n (4.29
e V), All (4.19e V), A
g (4.34e V), or polypyrrole,
It is preferable to use an organic conductive film such as a charge transfer complex.

As the insulating film 25, it is preferable to use polyimide, polybenzimidazole, or an inorganic material such as Sin2 or St3N4.

As the electron transport layer 27, perylene derivatives (for example, 3.4, 9, 10 perylene), tetracarboxybisupenzimidazole, etc., which have excellent electron injection and transport properties, are suitable.

As a method for creating the EL layer 17 formed by depositing such a material, there is a vacuum evaporation method. A dry method such as an electron beam evaporation method, a sputtering method, a CVD method, or an LB method using an appropriate hydrophilic group and hydrophobic group can be used.

All of these film-forming methods are low-temperature processes below 400°C, so there is no need to worry about thermal damage even if the stacked memory section is created using an LB film first. .

Next, the basic operations of the stacked memory unit, such as writing, transfer, and optical reading, will be explained with reference to FIG. Note that FIG. 6 is a diagram showing the electrical configuration of the stacked memory unit shown in FIG. 2.

In this stacked memory unit, when the switch SW is turned on and a voltage is applied to the upper electrode 18, a write charge is transferred to the insulating film 1.
6 is tunnel-conducted and stored in the charge storage capacitor C6.

Then, by sequentially applying transfer pulses φa and φbφC with different phases to the capacitors C6 to C1,
The write charge accumulated in capacitor C6 is transferred to C6 to C1.

Next, by applying a negative transfer pulse φC to the final stage capacitor C1, electrons, which are the accumulated charges of the capacitor C1, are injected into the EL layer 17, and holes are removed from the positive lower electrode 2. Injected. As a result, EL
The light emitting layer emits EL light and the accumulated charges are optically read out.

11. In the case where the EL layer 17 as a light output section is provided in the uppermost layer of the stacked tunnel switch section and charges are read from the substrate 1 side which is the lowermost layer, the structure shown in FIG. 7 is used. At this time, the configuration of the light output section is such that the laminated structure of the light output section shown in FIGS. 3 to 5 is reversed upside down.

Next, the operation of an optically readable three-dimensional memory element in which the above stacked memory units are two-dimensionally integrated will be explained.

First, when writing, write on side 21, which will be the writing side.
By irradiating light onto a surface and applying light to the surface, (Xi, Yi, Zl)
Data is written to each capacitor C6 at once.

Alternatively, as shown in FIG. 9, a plurality of transistors Tr (
A voltage is applied from the top layer of each stacked memory unit using a thin film FET (or thin film FET) to write data all at once to each capacitor C6 of (Xi, Yi, Zl).

Next, charge transfer pulse φa shown in FIG. 6 is applied to each capacitor 12 C1 to C6 of each stacked memory unit.
, φb, φC are applied all at once to each laminated surface and are sequentially transferred to the lower capacitors. Note that the pulse used for charge transfer may be of two phases.

In this embodiment, in order to apply the transfer pulse to each laminated surface at once, as shown in FIG. 8, the charge transfer voltage application lines of each capacitor C on the Zi surface are commonly connected.

Then, when performing optical readout, (Xi, Yi, Z6)
A charge transfer pulse φC (negative pulse) is applied from a transfer pulse application line L commonly connected to each capacitor on the surface, and a positive pulse is simultaneously applied to each lower electrode 2. Then,
The (Xi, Yi, ZE) plane emits surface light, and collective optical reading is performed from each stacked memory unit.

Also, since the amount of charge injected into the EL layer 17 differs depending on the accumulated charge of each capacitor C6 on the (Xi, Yi, Z6) plane, during writing, the amount of charge injected into each capacitor C6 on the (Xi, Yi, Zl) plane differs. On the other hand, if A13 is changed analogously to accumulate charges, (Xi, Y
i, ZE) plane, analog light can be output. Therefore, when using the optical output surface of a stacked memory unit as a pixel, in the case of writing using digital signals, it is necessary to combine multiple pixels to obtain the density of the pixel, but in the case of analog optical output, , the density can be adjusted with one pixel, and the sharpness of an image formed from a plurality of pixels can be improved.

As described above, according to this embodiment, since the EL layer 7, which can be produced by a low-temperature process, is used as the light output section, the organic LB films 11 to 16 can be used in the stacked tunnel switch section, and the optical The output section and the memory section can be integrated on one chip, and the device can be made more compact.

In addition, the stacked memory units with their optical output parts facing the same direction are two-dimensionally integrated on the transparent substrate 1, and a common connection is made to each capacitor C on the Zi surface, which is the stacked surface of the stacked memory unit. Since the charge transfer pulses φa and φbφC are applied all at once from the transferred transfer pulse application line, the charges accumulated in each capacitor C can be transferred all at once to each laminated surface (Zi surface). Yi, ZE) surface can be surface-emitted, and high-speed optical reading can be performed. As a result, when combined with an optical arithmetic element, it is possible to increase the information transmission speed and the calculation speed.

Furthermore, since an injection-type organic EL layer or a MIS-type EL layer is used as the EL layer 17, light can be output directly using the accumulated charge in the capacitor C1 without using an amplifier or the like, and the device can be made more compact. can be achieved.

In the above embodiment, the light output section of each stacked memory unit is used as a pixel, and by optimizing the pixel area, the memory can have an output display function.

〔Effect of the invention〕

As described in detail above, according to the present invention, an electroluminescent layer that can be created by a low-temperature process is provided at one end of the stacked tunnel switch section in the stacking direction. can be created on a single chip, making the device more compact.In particular, the electroluminescent layer can be created using a low-temperature process, making it easy to three-dimensionally integrate it into the stacked tunnel switch section. organic LB
It has the advantage that a membrane can be used.

In addition, since a plurality of optically readable stacked memory elements each having an electroluminescent layer formed at one end are integrated, and each electroluminescent layer forms the same plane, it is possible to apply a voltage to each electroluminescent layer at the same time. Accordingly, it is possible to perform collective optical readout using surface emission, and high-speed readout can be performed.

[Brief explanation of drawings]

FIG. 1 is a perspective view showing a schematic structure of an optically readable three-dimensional memory element according to an embodiment of the present invention, FIG. 2 is a sectional view of a stacked memory unit, and FIGS. 3 to 165 are A cross-sectional view showing the structure of the light output section, FIG. 6 is a block diagram showing the electrical structure of a stacked memory unit with the light output section provided on the substrate side, and FIG. A diagram showing the electrical configuration of a stacked memory unit. Figure 8 is a diagram showing a state in which the transfer pulse application lines of each capacitor are commonly connected. Figure 9 is a diagram showing a three-dimensional structure in which a write transistor is provided for each stacked memory unit. FIG. 2 is a perspective view of a memory element. DESCRIPTION OF SYMBOLS 1... Transparent substrate, 2... Transparent conductive layer, 3-8...
Conductive film, 11-16... Insulating film, 17... Electroluminescent layer, 18... Upper electrode, c1-c6
...Charge storage capacitor.

Claims (2)

[Claims] (1) A laminated tunnel switch section formed by alternately laminating a conductive film and an insulating film connected to a charge storage capacitor, and a layer on the conductive film that is one end in the stacking direction of this laminated tunnel switch section and the other end. a pair of electrodes provided on an insulating film, and an electroluminescent layer formed between a conductive film serving as one end in the stacking direction of the laminated tunnel switch section and the electrode provided on the conductive film. An optical readout type stacked memory element comprising: (2) An optically readable three-dimensional memory element, characterized in that the optically readable stacked memory element is two-dimensionally integrated, and each of the electroluminescent layers forms the same plane.