JPH0321064A - Semiconductor device - Google Patents

Abstract

PURPOSE:To realize further greater capacity without expanding the occupied area of a memory capacitor in plan view by forming more thickly an insulating film below an adjacent word line. CONSTITUTION:A silicon oxide film 4 is deposited on one principal surface of a semiconductor substrate 1, which film 4 is then patterned into the shape of an adjacent word line 5b where a stacked capacitor can be extended and formed, by a photolithography technique and an etching technique. Accordingly, the silicon oxide film 4 is thickly formed under the word line 5b when the stacked capacitor is extended and formed. Hereby, the memory capacitor has a greater area corresponding to a thickened fraction of the silicon oxide film 4 even though the area of the memory capacitor viewed from the flat plane thereof is not expanded, to increase the capacity thereof.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device having a stacked capacitor type cell.

2. Description of the Related Art In recent years, the capacity of semiconductor memories has been increasing due to miniaturization and higher integration of semiconductor devices.

2 to 7 Conventionally, as shown in FIG. 3, word lines 5a and sb are formed on one main surface of a semiconductor substrate, for example, a silicon substrate 1, using a first layer of polycrystalline silicon film, and then After forming the insulating film, a stacked capacitor is formed by extending the spacer 1 on the transistor gate 5a and the adjacent word line 5b using the second layer of polycrystalline silicon film, thereby increasing the capacitance. I was getting .

Problems to be Solved by the Invention However, when further increasing density and integration,
If the memory cell size is simply reduced, the area of the memory capacitor will also be reduced and the capacitance will be reduced, and in order to secure the required capacitor area, the gate length can be extremely shortened.
This method has the problem of various problems caused by hot carriers.

The present invention solves the above-mentioned conventional problems without increasing the area occupied by the memory capacitor in plan view.
This makes it possible to achieve even greater capacity.

Means for Solving the Problems In order to solve the above problems, the semiconductor device of the present invention deposits a silicon oxide film on one main surface of a semiconductor substrate, and stacks the silicon oxide film using photolithography technology and etching technology. The capacitor is formed by patterning it into the shape of adjacent word lines that can be extended.

According to the above structure, since the silicon oxide film is formed thickly under the word line where the stacked capacitor is extended, the memory capacitor can be formed without increasing the area seen in a plane. As the silicon oxide film becomes thicker, the area becomes larger and the capacitance can be increased. Also, Nutasoku 1
- Since the silicon oxide film on the word line where the capacitor is not formed is formed thinly, there is no fear of cutting due to the step of the bit line.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIGS. 1a to 1b show an embodiment of the present invention.

As shown in FIG. 1a, a field oxide film 2 consisting of a silicon oxide film with a thickness of about 5,000 wafers is formed by applying a selective oxidation method on a silicon substrate 1, and a field oxide film 2 made of a silicon oxide film having a thickness of about 5000 nm is formed on a silicon substrate 1, and a field oxide film 2 made of a silicon oxide film is formed by applying a thermal oxidation method. Approximately 200 on the active area of 1
A gate oxide film 2 of the size of a human being is formed.

Next, a silicon oxide film 4 having a thickness of about 6,000 layers is formed by CVD.

As shown in FIG. 1B, the silicon oxide film is patterned into the shape of an adjacent word line by photolithography, and the silicon oxide film other than the adjacent word line on which the stacked capacitor is formed is removed by etching.

Next, as shown in Figure 1C, approximately 4000~
About 5,000 polycrystalline silicon films 5 are deposited.

Furthermore, as shown in FIG. 1d, the photoresist film 6 is patterned into a word line shape, and word lines 5a and 5b are formed using an etching technique.

5 ・＼ , Next, as shown in Figure 1e, form a silicon oxide film and form the first
As shown in the figure, in order to form a transistor with an LDD structure,
By using ion implantation method, a low concentration region of phosphorus is created,
A nupacer 8 made of a CVD oxide film formed by low pressure CVD is provided on the side surface of the gate.

Then, n+ source/drain diffusion regions 9 are formed by implanting arsenic ions.

Next, as shown in FIG. 1q, the second layer of polycrystalline silicon film is lengthened using the CUD method, patterned using photolithography technology, and etched. A stacked capacitor 11 made of a crystalline silicon film is formed.

Thereafter, as shown in FIG. 1b, the insulating film 1 is
After forming 2, a third layer of polycrystalline silicon film of approximately 2,500 layers is lengthened by the CVD method, and then the 3rd layer polycrystalline silicon film is formed by the ion implantation method.
After implanting n-type impurity ions into the second polycrystalline silicon film, patterning is performed using a phosphorography technique and etching is performed to form a stacked capacitor 13.

6 to 7 Next, after forming a silicon nitride film of about 200 layers using a low pressure CVD method, an interlayer insulating film made of boron phosphosilicate glass is formed using a CVD method of about 4,500 layers. Next, the interlayer insulating film 15 and the insulating film 14 are patterned using a photophosphorography technique to form a contact window between the polycide and the substrate. Next, the polycrystalline silicon film is grown to a thickness of about 1,600 mm using the CVD method, and after implanting n-type impurities, the polycrystalline silicon film is grown to a thickness of about 250 mm.
0 people's tungsten silicide is prefixed, bit line 1
form 6.

By the above method, about 600 mL of insulating film is formed under the word line 4b on the field oxide film forming the stacked capacitor.
Due to the shape of the oO person, the area occupied by the star socket capacitor increases and the capacitance increases by about 20%.

Effects of the Invention According to the present invention, by forming a thick insulating film on the portion of the Finored oxide film where adjacent word lines are to be formed, the planar area of the Stanocht capacitor can be increased without increasing the area. It becomes possible to increase the area, size, and capacity.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the process flow order of an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional example. 1...Silicon substrate, 2...Finored oxide film, 3...gate oxide film, 4...
...Silicon oxide film, 5a, 5b...Word line, 6--F1-resist film, 7...Silicon oxide film, 8...Side wall hole, 9 ...
. . . Diffusion layer region, 10 . . . Interlayer insulating film, 11
...Stacked capacitor electrode, 12...
...Capacitive insulating film, 13...Stacked capacitor electrode, 14...Interlayer insulating film, 15...
・Interlayer insulating film, 16...Bit 1 line.

Claims (1)

[Claims] A semiconductor device comprising a stacked capacitor type cell, wherein the stacked capacitor is in contact with a source or drain region of a transistor of the memory cell and extends over a gate portion of the transistor and an adjacent word line portion via an insulating film. A semiconductor device comprising a dielectric film on a first electrode and a second electrode on the dielectric film, the insulating film being thickly formed under the adjacent word line.