JPH03210654A - Distributed control processing device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a distributed control processing device that processes processing requests generated from a plurality of input/output control devices by balancing (distributing) processing loads among a plurality of processors.

[Prior art J Figures 5 and 6 are, for example, a conventional distributed control processing device shown in IEICE Switching Study Group Material 5E78-106 r Consideration of Switching Processing Methods in Multi-processor Controlled Electronic Switching Equipment. In Figure 0, which is a system configuration diagram showing the system configuration diagram and an explanatory diagram for explaining its operation, laxlm
are a plurality of processors that process requested information, and 28 to 2n are a plurality of input/output control devices that request the processors la to 1m to process information. 3 is an inter-processor communication control device that controls communication between these processors la-1m and the input/output control devices 28 to 2n, 4 is a bus connecting the processors 18 to 1m and the inter-processor communication control device 3, and 5 is an inter-processor communication control device This is a bus that connects the input/output control devices 28 to 2n and the interprocessor communication control device 3. In the interprocessor communication control device 3, IO is a contention control unit that controls contention of processing request messages from each of the input/output control devices 28 to 2n, and 11 is a processing request queue in which the processing request messages wait. Reference numeral 12 is a control unit with an empty charge that controls the reception of empty notification messages from each processor la-1m, and 13 is an empty display queue in which the empty notification messages wait. Reference numeral 14 denotes a load distribution control unit that distributes processing request messages waiting in the processing request queue 11 to each of the processors la to 1m using empty notification messages waiting in the empty display queue 13. Further, 15 is a processing result reception control unit that controls the reception of processing result messages returned from the processors la to 1m, and 16 is a processing result queue in which the processing result messages wait. Reference numeral 17 denotes a processing result distribution control unit that distributes the processing result messages waiting in the processing result queue 16 to the corresponding input/output control devices 28 to 2n. Next, the operation will be explained. Each input/output control device 28-2
When a processing request is issued to the processor lax1m, n acquires the right to use the bus 5, generates a processing request message including its own identification number, and sends it to the interprocessor communication control device 3 from the bus 5. The inter-processor communication control device 3 receives the processing request message at the competition control unit 10, and puts it into the processing request queue 11. In addition, the processors la to 1m themselves have input/output control device 2.
When the device becomes available (ready) to accept processing requests from devices 8 to 2n, it acquires the right to use the bus 4, generates an empty notification message containing its own identification number, and sends it through the bus 4 for inter-processor communication. Send to control device 3. When the inter-processor communication control device 3 receives the empty notification message in the empty charge control unit 12, it inputs it into the -air space display key 13. In the inter-processor communication control device 3, the processing request queue 11
If a processing request message is waiting in , and at that time, there is also an empty notification message in the empty display queue 13, the load distribution control unit 14 transfers the message. In other words, the load distribution control unit 14 analyzes the empty notification message. The processor fax1m that sent it is identified, and one of the processing request messages waiting in the processing request queue 11 is sent from the bus 4 to that processor (for example, la). Upon receiving the processing request message from the interprocessor communication control device 3, the processor 1a analyzes the processing request message, executes the corresponding process, and sends the result as a processing result message to the interprocessor communication control device via the bus 4. Return to 3. Here, the processing result message also includes the identification number of the input/output control device 28 to 2n that generated the processing request message. The inter-processor communication control device 3 that has received this processing result message receives it in the processing result reception control section 15 and puts it in the -H processing result queue 16. Furthermore, if a processing result message is waiting in the processing result queue 16 and the right to use the bus 5 has been acquired, the interprocessor communication control device 3 analyzes the identification number in the processing result message and applies the corresponding input. The processing result message is sent to the output control device (for example, 2a). Through the above processing, the inter-processor communication control device 3 distributes processing requests from the plurality of input/output control devices 28 to 2n in a well-balanced manner to the processors la to 1m that are waiting for processing requests. [Problems to be Solved by the Invention] Since the conventional distributed control processing device is configured as described above, various messages concentrate on the inter-processor communication control device 3, resulting in an enormous load. Since the processing capacity of the entire system is affected by the processing capacity of the communication control device 3, it is necessary to increase the processing capacity of the inter-processor communication control device 3. If this occurs, the entire system will go down, and to prevent this, a redundant configuration such as duplexing is required.The system becomes expensive, and furthermore, each message is sent regardless of the reception status of the destination. Since the data is sent to the other party, there were problems such as complicated transfer control such as retransmission control.This invention was made to solve the above problems, and it is possible to process the entire system by simple control. It is an object of the present invention to obtain an inexpensive and highly reliable distributed control processing device that eliminates the above-mentioned bottleneck. In addition to providing a timing control unit that supplies the timing at which an interrupt request generated by the interrupt request control unit of each input/output control device to each processor is staggered for each processor when the interrupt request occurs, a timing control unit is provided for each processor. A free display section that displays that the interrupt request can be accepted in the state, and a timing control section that takes in the interrupt request according to the timing given by the timing control section, and notifies other processors that the interrupt request is held. [Operation] In the interrupt reception control section of each processor according to the present invention, the idle display section indicates that the own processor is idle, and If the interrupt request is not captured by another processor, it captures the interrupt request according to the timing given by the timing control unit, and notifies other processors that the interrupt request has been held, so that the same interrupt is not captured. By preventing requests from being accepted by multiple processors, a bottleneck in the processing of the entire system can be eliminated with simple control, thereby realizing an inexpensive and highly reliable distributed control processing device. [Embodiment 1] Hereinafter, an embodiment of the present invention will be explained with reference to the drawings.
In the figure, la-zlm is a processor, and 2a~
2n is an input/output control device. 6 is each input/output control device 2
This is a system controller that generates the timing for each processor la to 1m to receive an interrupt request generated by processors 8 to 2n to request a processing request, and arbitrates the right to use the system bus, which will be described later. 7 is each of these processors 1a
~1m, each input/output control device 2a~2n, and a system bus as a bus that connects the system controller 6 with each other. In the system controller 6, a system controller 20 determines the timing at which each processor la-x1m takes in the interrupt request generated by each input/output control device 28 to 2n.
It is a timing control section that sequentially supplies data while being shifted in time every millimeter, and numeral 21 is an arbiter section that arbitrates requests for use of the system bus 7 of each processor la-1m. In each of the processors la to 1m, 22 controls the entire processors 1a to 1m to which it is arranged, and executes processing for accepting interrupt requests from each input/output control device 28 to 2n, processing received processing requests, etc. 23 is an information processing unit (hereinafter referred to as CPU); 23 is a bus request control unit that generates a request to use the system bus 7; 24 is the own processor la-1;
When m is in a vacant state, the input/output control devices 2a to 2n
This is an empty display section that indicates that it is possible to accept an interrupt request from. 25 indicates that the idle display unit 24 indicates that the own processors la to 1m are idle, and when the other processors 1a=1m do not hold the interrupt request, the timing control unit 20 displays the interrupt request. When the timing to capture an interrupt request is given, the interrupt request is captured and temporarily held, and an interrupt capture notification signal indicating that the interrupt request is held is sent to the other processors 1a to 1.
This is an interrupt acceptance control unit that notifies m. 26, each processor lax1m connects to other processor lax
1m and each of the input/output control devices 28 to 2n. In each of the input/output control devices 28 to 2n, 27 is connected to each processor 1a from the input/output control device 28 to 2n in which it is arranged.
This is an interrupt request control unit that controls sending of an interrupt request when a processing request to 1m is generated. Reference numeral 28 denotes a data transfer slave unit that controls the execution of data transfer between each input/output control device 28 to 2n and each processor la-1m. Reference numeral 29 denotes a common control section that controls the entire input/output control devices 2a to 2n in which it is arranged. On the system bus 7, 30 represents each processor lax1
31 is a data transfer signal bus for transmitting data exchanged between the input/output control devices 2a to 2n, and 31 is a data transfer signal bus for contention arbitration of requests to use the data transfer signal bus 30 between the processors la to 1m. This is an arbitration bus for this purpose. 32 is an interrupt notification signal bus through which interrupt notification signals exchanged between the processors 1m and 1m are transmitted;
33 is each processor 1a''=1m and each input/output control device 2
An interrupt acceptance signal bus through which interrupt acceptance signals exchanged between a to 2n are transmitted; 34 is each input/output control device 28 to 2n;
and an interrupt request signal bus 35 through which interrupt request signals exchanged between the processors 18 to 1m are transmitted;
This is an interrupt capture signal bus that transmits the capture timing of interrupt requests given to a to 1m. 36 is an interrupt priority signal bus through which interrupt priority signals between the input/output control devices 28 to 2n are transmitted. Next, the operation will be explained. Here, FIGS. 2 and 3
The figure is a flowchart showing the processing procedure of the CPU 22 and the interrupt reception control section 25 in the processor l mill 1m, and FIG. 4 is a flowchart showing the processing procedure of the interrupt request control section 27 in the input/output control devices 2a to 2n. . Below, the processors la and 1m are in a vacant state, and the input/output control devices 2a and 2n simultaneously control the processors la to 1m.
It is assumed that a processing request has been generated for the input/output control device 2a and 20, and the interrupt priority of the input/output control device 2n is high (
, a case will be described in which the processor 1a is given the interrupt request capture timing from the timing control unit 20 of the system controller 6 first. The CPU 22 of each processor la-1m monitors its status at step 5TIO in FIG. Now, since both processors la and 1m are in the idle state, a ready notification is sent to each idle display section 24 in step 5TII, and in step 5T12, the input/output control devices 28 to 2n
Upon receiving this notification, the idle display unit 24, which waits for an interrupt request from the processor 1a or 1m, displays to each interrupt acceptance control unit 25 that the processor 1a or 1m is idle. On the other hand, when the input/output control devices 2a and 2n simultaneously issue a processing request to the processor 1a"=1m, each common control section 29 sends an interrupt request instruction to its interrupt request control section 27. The interrupt request control unit 27 monitors this interrupt request instruction in step 5T30 of FIG. 4, and when it detects it, outputs an interrupt request signal to the interrupt request signal bus 34 in step ST31, and then outputs an interrupt request signal to the interrupt request signal bus 34 in step 5T32. At step 5T20 in FIG. 3, the processor lax1m waits for an interrupt acceptance signal to be sent from the processor lax1m, which has received this interrupt request. It is waiting for the timing to capture an interrupt request sent from the timing control unit 20 of the system controller 6 via the interrupt signal bus 35. In this case, the timing to capture this interrupt request is set earlier by the processor la than by the processor 1m. Since the interrupt reception control unit 25 of the processor la first executes step 5T2.
1 to 5T23, the status of the interrupt request signal bus 34, the display on the idle display section 24 of the own device, and the status of the interrupt capture notification signal bus 32 are checked. In this case, there is an interrupt request, a ready display is displayed, and since the interrupt request has not been taken in by another processor lb-1m, the interrupt request is taken in at the above-mentioned taking timing in step 5T22, and the interrupt request is taken in automatically. It interrupts the CPU 22 in the device and sends an interrupt notification signal to the interrupt notification signal bus 32 to notify that the interrupt request has been received. Then step 5T25
Waits for the CPU 22 of the own device to accept the interrupt. Even in the processor 1m, the interrupt request signal bus 34 is sent to the interrupt request signal bus 34 by the interrupt acceptance control unit 25 at a timing later than that of the processor 1a.
, the display on the idle display section 24 of the own device, and the state of the interrupt capture notification signal bus 32 in steps 5T21-3T2.
You can check it in 3. In this case, since the interrupt request has already been captured by the processor 1a and a notification to that effect has been output to the interrupt capture notification signal bus 32, the interrupt request is not captured, and the process returns to step 5T20 for the next step. The timing has come. When the CPU 22 of the processor la receives this interrupt request, it sends a busy notification to the free display unit 24 in step 5T13, and further sends an instruction to secure the right to use the system bus 7 to the bus request control unit 23 in step 5T14. , the bus request control unit 2 receives the instruction to secure the right to use the bus, waiting for notification that the right to use the bus has been secured in step 5T15.
3 sends a bus request signal to the arbitration bus 31. The arbiter unit 21 of the system controller 6 that has detected this bus request signal checks whether the system bus 7 is being used by other processors lb~1m, and if it is in use, checks that processor lbx1m.
In response, Akira gave instructions to pass the system bus 7.
When the bus becomes free, the right to use it is given to the bus request control unit 23 of the processor 1a. The bus request control unit 23 that has received the request notifies the CPU 22 of this fact. C of the processor la that received the notification of securing the right to use the bus.
In step 5T16, the PU 22 causes the interrupt acceptance control unit 25 to output an interrupt acceptance signal to the interrupt acceptance signal bus 33 for a certain period of time. Interrupt reception control unit 2 of processor la
5, upon receiving the interrupt acceptance signal from the CPU 22, cancels the interrupt to the CPU 22 at step 5T26 in FIG. Thereafter, in step 5T27, the end of the interrupt request acceptance process is monitored, and when the interrupt request acceptance process is finished, step 5
At T28, the interrupt notification sent to the interrupt notification signal bus 32 to the other processor lbA-1m is canceled. The interrupt request control units 27 of the input/output control devices 2a and 2n that have detected the interrupt acceptance signal from the processor la perform competition control by exchanging signals via the interrupt priority signal bus 36 in step 5733. In step 5T34, it is determined which one has higher priority for this interrupt acceptance signal.In this case, the input/output control device 2n wins this competition, and in step 5T35, the input/output control device 2n sends the data transfer signal bus 30 to the own device. After outputting the interrupt status such as the identification number, the interrupt request is released. Input/output control device 2a that lost the competition
Then, the process returns to step 5T32 and waits until the next interrupt acceptance signal is output. On the other hand, in the processor la, step 5T17 in FIG.
The data transfer mask section 26 receives this interrupt status and sends it to the CPU 22, which analyzes it and learns that the interrupt request has been sent from the input/output control device 2n. Thereafter, in order to know the details of the processing request from the input/output control device 2n, the right to use the system bus 7 is acquired again. When the right to use the system bus 7 is secured, the CPU 22 performs input/output control in step 5T18. Detailed data of a processing request is read from the common control unit 29 of the device 2n via the data transfer slave unit 28, the detailed data is analyzed, and necessary processing is executed. The execution results are transmitted to the input/output control device 2n and other processors lb to 1m as necessary, and all processing is completed. Here, the processing request of the input/output control device 2a for which the interrupt request was not accepted is processed by the processor 1m from the time when the interrupt capture notification signal outputted by the processor la is released.
Processing is performed in the same manner as in the above case by the other idle processors 1b to 1m such as . In this way, processing requests from each of the input/output control devices 2a to 2n are sequentially accepted by the idle processors 1a to 1m, and processing requests from the input/output control devices 28 to 2n are load-distributed to multiple processors. It is processed. In the above embodiment, the timing control section and the arbiter section are arranged centrally in the system controller, but these functions may be provided in each processor. Further, in the above embodiment, the common control unit in the input/output control device was explained as being distinguished from the CPU in the processor, but the
PU equivalent or equivalent may be used. [Effects of the Invention] As described above, according to the present invention, when the idle display section displays that the own processor is idle, and the interrupt request has not been received by another processor,
Since the configuration is configured to capture the interrupt request according to the timing given by the timing control unit and notify other processors that the interrupt request is held, it is possible for multiple processors to accept the same interrupt request. Instead, processing requests directly transmitted to multiple processors by interrupt requests from the I/O controller are processed by one of the idle processors, and the processing requests from the I/O controller, which is the boltneck, are processed by one of the idle processors. Since there is no need for a device to distribute data to the processors, processing is executed under the initiative of the processors, making control simple and easy, resulting in a distributed control processing device that can improve system reliability and reduce costs. It has the effect of

[Brief Description of the Drawings] Fig. 1 is a system configuration diagram showing a distributed control device according to an embodiment of the present invention, Fig. 2 is a flowchart showing the processing procedure of the CPU in the processor, and Fig. 3 is a system configuration diagram showing the processing procedure of the CPU in the processor. 4 is a flowchart showing the processing procedure of the interrupt reception control section in the input/output control device, and FIG. 5 is a system configuration showing the conventional distributed control processing device. 6 are explanatory diagrams for explaining the operation. la--1m is a processor, 28 to 2n are input/output control devices, 7 is a bus (system bus), 20 is a timing control section, 22 is a CPU, 24 is an empty display section, 25 is an interrupt acceptance control section, 27 is a Interrupt request control unit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] Distributed control processing consisting of a plurality of input/output control devices and a plurality of processors connected to each other by a bus, in which a processing request generated from one of the input/output control devices is processed by an unoccupied one of the processors. In the apparatus, a timing control unit is provided that supplies timing for each processor to take in an interrupt request generated by the input/output control device to request the processing request, with a time shift for each processor; , each of the input/output control devices is provided with an interrupt request control unit that sends the interrupt request to each of the processors and notifies them when the processing request occurs, When in the state, there is an empty display section that indicates that it is possible to accept an interrupt request from the input/output control device, and when the interrupt request from the interrupt request control section is accepted, the interrupt request is displayed. The information processing section executes the processing according to the accepted processing request, and the free space display section indicates the free state of its own processor. When the interrupt request is displayed and no other processor holds the interrupt request, when the timing control section gives the timing to take in the interrupt request, the interrupt request is taken in, temporarily held, and the interrupt request is 1. A distributed control processing device comprising: an interrupt reception control unit that notifies the other processor that an interrupt request has been held.