JPH0321075A - High voltage semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a high voltage MOSFET. High voltage MOSFETs are used as individual elements or integrated into ICs together with other semiconductor elements.

(Prior art) In high-voltage MOSFETs in which a source region and a drain region face each other on the surface of a substrate, the source region and the drain region are arranged on the surface of the substrate in order to prevent the formation of an inversion layer on the surface and increase the breakdown voltage. A so-called guard ring (field limiting ring) of an impurity diffusion region (hereinafter simply referred to as a diffusion region) of the same conductivity type as the source region is formed to surround the source region.

Figures 3 and 4 show such high-voltage MOSFETs, with Figure 3 showing the area where the source electrode wiring runs through the surface, and Figure 4 showing the area where no wiring runs through. It represents an area.

In Figures 3 and 4, the high voltage MOSFET has a dielectric film 2.
It is formed on an N-silicon substrate 6 separated by . A semiconductor integrated circuit device in which high voltage MOSFETs are formed on the same chip uses a lower concentration substrate than a conventional semiconductor integrated circuit device. 4 is the N+ layer. 8 is the source area,
10 is a drain region, and a guard ring P1 diffusion region 12 is provided so as to surround the source region 8.

Reference numeral 14 is a silicon oxide film, and reference numeral 6 is a metal wiring connected to the source region 8. 18 is a polycrystalline silicon layer supporting dielectrically isolated elements.

When such high breakdown voltage MOSFETs are integrated, it becomes inevitable that electrode wiring for source electrodes and gate electrodes passes through the surface of this FET.

(Problems to be Solved by the Invention) Under these conditions, surface depletion or inversion channel leakage often tends to occur in the region immediately below the electrode. In particular, as the surface depletion directly under the electrode progresses, a depletion layer (
Reach-through (the state shown in FIG. 3) occurs, where the broken line area in FIG. 3 is connected. The electric field strength increases in the vicinity of the reach-through drain region 10, and reaches a critical value as the applied voltage +■ increases. On the other hand, in the region where the wiring does not pass, as shown in FIG. 4, surface depletion has not progressed, and the electric field strength increases in the source region 8 and the guard ring 12.

To this end, some devices have introduced a channel stopper in a high concentration region of the same conductivity type as the substrate on the surface of the substrate directly under the wiring, but this still suffers from the problem of a drop in breakdown voltage.

As another countermeasure, in order to alleviate the breakdown voltage drop due to reach-through, FRR ( Field Reduction R
+4ion) structure has been proposed.

An object of the present invention is to use a guard ring potential to prevent a drop in breakdown voltage due to reach-through directly under the wiring.

(Means for Solving the Problems) In the present invention, a conductive layer is formed below the electrode wiring, which is connected to the substrate and the electrode wiring by an insulating film, and is short-circuited to a guard link.

(Embodiment) The first construction drawing is a sectional view showing an embodiment cut in the region of the source electrode wiring, and FIG. 2 is a plan view of the source electrode wiring region of the same embodiment.

The MOSFETs are formed in silicon substrate regions separated by dielectric legs 22 such as silicon oxide films. 26 is an N-type silicon substrate 3 with a low impurity concentration, 24 is a high-concentration N-type diffusion layer provided at the bottom of the substrate 26, and a high-concentration N-type diffusion region 30 which is a drain region provided on the surface. is connected to Reference numeral 28 denotes a source region made of a heavily doped P-type diffusion region, and is provided on the surface of the substrate.

Also on the substrate surface, a heavily doped P-type diffusion region 32 surrounding the source region 28 is formed as a guard ring. The guard ring 32 is introduced to prevent layer inversion on the substrate surface and to increase the withstand voltage. In this embodiment, the guard ring 32 is partially cut off at a portion where wiring such as the source electrode wiring 36 passes over the substrate 26.

The surface of the substrate 26 is a silicon oxide film 3 which is a gate oxide film.
It is covered by 4. A conductive layer 40 of a polycrystalline silicon film doped with impurities is formed on the silicon oxide film 34 in a region through which the source electrode wiring and the gate electrode wiring pass. In the figure, only the conductive layer 40 in the source electrode wiring 36 portion is shown. A gate electrode made of the same polycrystalline silicon film is formed in the region other than the region where the wiring is formed. An interlayer insulating film 42 such as a silicon oxide layer is formed as an insulating film between the polycrystalline silicon film 40 and the wiring 36 formed thereon. A source electrode wiring 36 and a gate electrode wiring (not shown) made of aluminum or the like are formed on the interlayer insulating film 42 . The wiring 36 is an insulating film 42.
The source region 2 is connected to the source region 2 through the contact hole provided in 34.
8 is connected. 50 is the wiring 36 and the source region 28
Contact 1~.

The conductive layer 40 is connected to the guard ring 32 as shown in FIG.
is short-circuited. A metal wiring 44 is formed, the guard ring 32 and the metal wiring 44 are connected through contacts 1 to 46, and the metal wiring 44 is connected to the conductive layer 4 through the contact 48.
Connected to 0.

Next, the operation of this embodiment will be explained.

When operating this high voltage MOSFET, a positive power supply voltage +V is applied to the drain region 30 and the source region 28 is grounded. As voltage is applied to the drain region 3o, the potential of the guard ring 32 increases in the positive direction, and the conductivity W
The potential of J4.0 also becomes a positive potential. In the area where the wiring 36 passes, a conductive layer 40 with a positive potential exists on the substrate 26'2 via the gate oxide film 34, which suppresses depletion of the substrate surface directly under the wiring 36, and reduces the withstand voltage. is prevented.

Since a conductive layer having the same potential as the guard ring potential also exists directly under the gate electrode wiring, reach-through is prevented from occurring when the gate electrode potential is OV.

(Effects of the Invention) In the present invention, a conductive layer is formed below the electrode wiring, which is insulated from the substrate and the electrode wiring by an insulating film and short-circuited with the guard ring, so that reach-through occurs directly under the wiring due to the guard ring potential. High voltage resistance M
It is possible to prevent a decrease in the breakdown voltage of the OSFET. For example, a high voltage MOSFET using an N-substrate with a resistance value of 40Ω・Cm
In the present invention, the withstand voltage can be increased by 60 to 70 V compared to the conventional device which does not have a conductive layer below the electrode wiring.

[Brief explanation of drawings]

FIG. E is a cross-sectional view showing one embodiment cut in the region of the source electrode wiring, and FIG. 2 is a plan view of the source electrode wiring region of the same embodiment. Figure 3 shows a conventional high voltage MOSFE
FIG. 4 is a cross-sectional view of the conventional high-voltage MOSFET taken through a region where the source electrode wire does not pass. 26...Substrate, 28...Source region, 30
... Drain region, 32 ... Guard ring, 34
...Gate oxide film, 36... Wiring, 40.
... Conductive layer, 44 ... Metal wiring, 46
．． 48...Go to contact 1.

Claims (1)

[Claims] (1) A source region and a drain region are provided facing each other on the surface of the substrate, an impurity diffusion region of the same conductivity type as the source region is formed between the two regions, and the substrate and the electrode wiring are provided below the electrode wiring. A high-voltage semiconductor integrated circuit device includes a conductive layer insulated by an insulating film and short-circuited to the impurity diffusion region.