JPH0321076B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a portable testing device for testing an inductive watt-hour meter already installed in a consumer.

Conventionally, testing equipment for inductive watt-hour meters has been limited to those that can be tested at the Japan Electric Meter Inspection Institute or manufacturing plants. Therefore, if a customer, etc. finds an abnormality in the operating state of the inductive watt-hour meter after actually installing and starting to use the inductive watt-hour meter, in order to conduct a test, There is a problem in that it is necessary to remove the inductive watt-hour meter from its installed state and take it to the location where the testing device is installed, such as the Japan Electric Meter Inspection Institute or a manufacturing factory.

In addition, it has been used as a testing device for electricity meters used at the Japan Electric Meter Inspection Institute, etc.
As disclosed in the publication, a method has been proposed that uses a microcomputer to calculate the average power of the power system and the average power measured by the meter under test, and calculates the instrumental error of the meter under test from both average powers. ing. However, if you try to use a test device using such a microcomputer as a portable test device to test the inductive watt-hour meter already installed at a consumer, the portable test device will not be sold. Since the number of microcomputers is small, the software development cost for each microcomputer is high, resulting in high costs.

Furthermore, this type of test equipment has a power-frequency conversion means that generates a pulse with a frequency proportional to the power of the power system, but if you try to reduce the error of this power-frequency conversion means to 0 on the circuit, the circuit The design becomes complicated, the circuit itself becomes expensive, and adjustment is troublesome.

An object of the present invention is to solve the above-mentioned problems, to enable testing with an inductive watt-hour meter installed, to reduce costs, and to reduce errors in the built-in power-frequency conversion means. An object of the present invention is to provide a portable inductive watt-hour meter testing device that can easily correct each device individually.

In order to achieve this object, the present invention includes an optical rotation speed detecting means for optically detecting the disk rotation speed of the instrument under test, and an optical rotation speed detection means that is detachably connected to the voltage terminal of the instrument under test and extracts the voltage. A voltage extraction means, a split type current transformer that is detachably attached to the load circuit and detects the load current, and the voltage extracted by the voltage extraction means and the load current detected by the split type current transformer are used to generate electric power. a power-to-frequency conversion means that generates a pulse with a frequency proportional to , a rotation speed setting means that sets a disk rotation speed of the instrument under test necessary for the test, and a rotation speed setting means that generates a rotation speed of the disk of the instrument under test at the set rotation speed. a counter means for counting the number of pulses generated by the power-to-frequency converter while the power-to-frequency converter generates pulses; a limit pulse number setting means for setting an upper limit value and a lower limit value of the number of pulses to be processed; and a determining means for determining whether the number of pulses of the counter means is between the upper limit value and the lower limit value set by the limit pulse number setting means. and master error correction means for correcting the upper limit value and lower limit value set by the limit pulse number setting means in accordance with the error of the power-frequency conversion means.

Hereinafter, the present invention will be explained in detail based on illustrated embodiments.

FIG. 1 is a block diagram showing one embodiment of the present invention. Further, FIG. 2 shows the state of signals in each part of the embodiment shown in FIG. 1.

First, a procedure for testing the inductive watt-hour meter 1 according to this embodiment will be explained. First, an alligator clip 2 for extracting voltage is attached to the voltage terminal (not shown) of the inductive watt-hour meter 1, and the load side electric wire 3
A split type current transformer 4 is attached to detect the load current. The reason why a split type current transformer is used here is
This is because it can be detachably attached to the load circuit without cutting the load-side electric wire 3. Next, a light emitter/receiver 6 for optically detecting the number of rotations of the disc 5 is set in the inductive power meter 1. In this embodiment, the light emitter/receiver 6 emits light onto the disc 5 from a light emitter, uses a light receiver to detect changes in reflected light when the light is projected onto an index 7 on the disc 5, Although the one that outputs one pulse every time the disk 5 rotates is shown, it is also possible to create two creep holes on the disk 5 symmetrically about the axis 8 by means of a light emitter and a light receiver. Those with a structure for detection can also be used. Next, the meter constants of the inductive watt-hour meter 1 are set in the numerical setting device DS ₁ , and the rotation speed of the disc 5 required for the test is set in the numerical setting device DS ₂ . The test is conducted by detecting the error of the inductive power meter 1 while the disc 5 rotates by the set number of revolutions. , preferably around 10 times. Further, the numerical value setting device DS ₃ is configured to perform power-frequency conversion while the disk 5 rotates by the number of rotations set in the numerical value setting device DS ₂ when the inductive watt-hour meter 1, which is the meter under test, has an error of 0. The number of pulses to be output when the power-frequency conversion means consisting of the circuit WF, the programmable frequency divider circuit DV, and the numerical value setter _DS1 has an error of 0 is set. In addition, the numerical value setting device DS ₄
Set the number of pulses equal to the number of pulses set on the numerical setting device DS ₃ multiplied by the allowable error (%) of the instrument under test. In addition, the numerical setting device DS ₅ ,
Error (%) of power-frequency conversion means of this test instrument
The number of pulses multiplied by the set number of pulses is set in the numerical value setter DS ₃ , and the sign indicating whether this error is positive or negative is set in the master error setting encoder 9. The output of the master error setting encoder 9 is high level when the error is positive, and low level when the error is negative. This completes the test preparation steps, and the test operation is started by turning on a test start switch (not shown).

Next, in accordance with the order of test operations, the structure of this example,
Explain the function. First, by turning on a test start switch (not shown), a start signal _P0 is input to the pulse signal generation circuit PG. As a result, the pulse signal generation circuit PG immediately outputs the single pulse signal P ₁ from the terminal T ₁ , and then outputs the single pulse signal P 1 at a certain interval.
The individual pulse signal P′ ₁ of the pulse number is outputted from the terminal T ₂ . The single pulse signal _P1 is input to an OR gate _G1 and an AND gate _G2 . Further, the single pulse signal P ₁ is delayed by a delay circuit constituted by a resistor R ₁ and a capacitor C, and is input as a signal P ₂ to an OR gate G ₁ and an AND gate G ₂ . As a result, a high-level signal _P3 is first output from OR gate _G1 , and the write preparation signal input terminal of presettable up-down counters _CT1 and _CT2 is output.
Enter into PS. And gate a little later
A high level signal _P4 is output from _G2 and input to the write signal input terminals CL of the presettable up-down counters _CT1 and _CT2 . To prevent malfunction, the presettable up-down counters CT ₁ and CT ₂ write and store the numerical value set in the numerical value setter DS ₃ only when a write signal is input while the write preparation signal is input. From then on, every time a pulse to be counted is input to the input terminal IN, if the input to the counting mode switching terminal U/D is low level and the subtraction mode is in effect, the count mode switching terminal U/D is subtracted.
When the input to is high level and in addition mode, addition is performed. Therefore, the signal P ₃
By inputting the signal _P4 , the numerical value set in the numerical value setter _DS3 is written and stored.

In addition, the single pulse signal P ₁ is sent to the counter CT ₃ ,
Reset CT ₄ , CT ₅ , and CT ₆ to make the count value 0. The numerical comparison circuit CP ₁ outputs a high level signal when the counted value of the counter CT ₃ becomes equal to the set value of the numerical setting device DS ₂ , and the numerical comparison circuit CP ₂ outputs a high level signal when the counted value of the counter CT ₃ becomes equal to the set value of the numerical setting device DS 2. The value is a value setter
Since it outputs a high level signal when it becomes equal to the set value of DS ₄ , the outputs of both at this point are low level. In addition, the numerical comparison circuit
CP ₃ outputs a high level signal when the count value of counter CT ₅ becomes larger than the count value of presettable up-down counter CT ₁ , and numerical comparison circuit CP ₄ outputs a high level signal when the count value of counter CT ₅ becomes larger than the count value of Since it outputs a high level signal when becomes larger than the count value of the presettable up-down counter _CT2 , the outputs of both at this point are also low level. Furthermore, the numerical comparison circuit CP ₅ is a counter
When the count value of CT ₆ exceeds the setting value of the numerical setting device DS ₅ , it outputs a high level signal, so if the setting value of the numerical setting device DS ₅ is 0, the output at this point is high. If the level is not 0, it is a low level. The low level signal from the numerical comparison circuit CP ₂ is sent to the three-input AND gate G ₃ and NAND gate G ₄
Close. Therefore, regardless of the output of the numerical comparison circuit _CP5 , the output of the NAND gate _G4 becomes high level, and the AND gates _G5 and _G6 are opened. Furthermore, since the low level signal from the numerical comparison circuit _CP2 closes the AND gate _G7 , the low level signal is input to the counting mode switching terminal U/D of the presettable up-down counter _CT1 . Presettable up-down counter _CT1 is designated to subtraction mode. Furthermore, the low level signal from the numerical comparison circuit _CP2 is inverted by the inverter _Io1 to become high level, and is input to the counting mode switching terminal U/D of the presettable up/down counter _CT2 via the OR gate _G3 . Therefore, the presettable up-down counter _CT2 is designated to the addition mode. In addition, the low level signal from the numerical comparison circuit CP ₃ closes the AND gate G ₉ , so the transistor T _r1 is not conductive and the light emitting diode PD ₁ does not light up, but it is inverted by the inverter I _o2 and the transistor Since it conducts T _r2 ,
The light emitting diode PD ₂ lights up by supplying the current voltage +V. This lighting confirms that the operation has started. Note that the low level signal from the numerical comparison circuit _CP4 does not conduct the transistor T _r3 , so the light emitting diode _PD3 does not light up.

Next, the second pulse signal _P'1 is output from the terminal _T2 , and is input to the set input terminal S of the RS flip-flop FF for controlling the AND gates _G10 and _G11 .
Enter. This allows the RS flip-flop
FF output is high level, AND gate
Open G ₁₀ and G ₁₁ . Therefore _, the output signal from the light emitter/receiver 6 is input to the counter CT 3 via the opened AND gate G ₁₀ , and the counter CT ₃ counts the number of rotations of the disc 5 of the inductive watt-hour meter 1 . Start. Also, the opened AND gates G ₁₁ , G ₅ , G ₆
The output signal from the programmable frequency divider circuit DV is input to the counters CT ₄ , CT ₅ and the presettable up-down counters CT ₁ , CT ₂ through the three-input AND gate.
Since G ₃ is closed, counter CT ₆ does not start counting. In addition, programmable frequency divider circuit
DV is a power output that outputs pulses with a frequency proportional to the power because the meter constants differ depending on the meter under test.
Since the number of pulses output from the frequency conversion circuit WF during one rotation of the disk of the meter under test varies depending on the meter under test, the frequency is divided by the meter constant value set in the numerical setting device DS ₁ . The ratio is set so that the number of pulses output during one rotation of the disc of the ratio test meter falls within a certain range regardless of the meter constant.

Presettable up-down counter CT ₁ ,
After CT ₂ , counters CT ₃ , CT ₄ , and CT ₅ start counting, the count value of counter CT ₄ is sent to the numerical value setter.
Equal to the set value of DS ₄ , the numerical comparator circuit CP ₂
output becomes high level. By this point, the presettable up-down counter CT ₁ has been set when the difference between the set value of the numerical setter DS ₃ and the set value of the numerical setter DS ₄ , that is, the error of the instrument under test is 0. The difference between the number of pulses output by the power-frequency conversion means with an error of 0 while the disk 5 rotates by the number of rotations, and the number of pulses with the maximum allowable error, in other words, the theory of the lower limit of the allowable number of pulses. The value is being counted. In addition, the presettable up-down counter CT ₂ is connected to the set value of the numerical value setter DS ₃ .
The sum with the setting value of DS ₄ , that is, the theoretical value of the allowable upper limit number of pulses is counted. Furthermore, the high level output of the numerical comparison circuit CP ₂ is connected to the AND gate
Since G ₇ is open, the counting mode switching terminal U/ of presettable up-down counters CT ₁ and CT ₂
When the error of the power-frequency conversion means is positive, a high-level signal is input to D to designate the addition mode, and when the error is negative, a low-level signal is input to D according to the sign setting of the master error setting encoder 9. input to specify subtraction mode. Further, the high level output of the numerical comparison circuit _CP2 is input to the three-input AND gate _G3 and the NAND gate _G4 , and the three-input AND gate _G3 is opened.

When the value set in the numerical value setter DS ₅ , that is, the error of the power-frequency conversion means is 0, the output of the numerical comparison circuit CP ₅ is at a high level, so the output of the NAND gate G ₄ is at a low level, and the AND Close gates G ₅ and G ₆ . Therefore, at this point, the presettable up-down counter CT ₁ ,
CT ₂ stops counting. When the set value of the numerical value setter DS ₅ is not 0, the output of the numerical comparison circuit CP ₅ is at a low level, so the output of the NAND gate G ₄ is at a high level, and the output pulse from the programmable frequency divider circuit DV is an AND gate. G ₁₁ , is input to the counter CT ₆ via the three-input AND gate G ₃ , and the counter CT ₆ starts counting. While the counter CT ₆ is counting, the presettable up-down counters CT ₁ and CT ₂ are also adding or subtracting according to the designated mode.

When the counted value of the counter CT ₆ becomes equal to the set value of the numerical value setter DS ₅ , the output of the numerical comparison circuit CP ₅ becomes high level, so the output of the NAND gate G ₄ becomes low level, and the three-input AND gate G ₃ ,
AND gates G ₅ and G ₆ are closed, and presettable up/down counters CT ₁ , CT ₂ and counter
CT ₆ stops counting. By this point, the presettable up-down counter CT ₁ has been set to the theoretically allowable lower limit number of pulses, assuming that the error of the power-frequency conversion means is ₀ .
A value corrected by adding or subtracting the error of the power-frequency conversion means set to , according to the code setting of the master error setting encoder 9, that is, a value corrected according to the error of the power-frequency conversion means,
The actual allowable lower limit pulse number is counted.
Similarly, the presettable up-down counter
CT ₂ counts the actual allowable upper limit number of pulses, corrected according to the error of the power-frequency conversion means.

Next, the count value of counter CT ₃ is sent to the value setter.
equal to the setting value of DS ₂ , the numerical comparator circuit CP ₁
output becomes high level. Since this high level signal is input to the reset input terminal R of the RS flip-flop FF, the output of the RS flip-flop FF becomes low level, and the AND gates G ₁₀ and G ₁₁
Close. Therefore, at this point the counter
CT ₃ , CT ₄ , and CT ₅ stop counting. Up to this point, the counter CT ₅ is connected to the programmable frequency divider circuit via the power-frequency conversion circuit WF while the disk 5 rotates by the number of rotations set in the numerical setting device DS ₂ .
The number of pulses output from DV is counted. Therefore, if the error of the instrument under test is 0, the number of pulses will be the value set on the numerical setting device DS ₃ ,
It is equal to the value corrected for error by the numerical value setter DS ₅ and master error setting encoder 9. If the instrument under test has a negative error, the time required for the disk 5 to rotate by the set number of revolutions will be longer than when the error of the instrument under test is 0, so the counter
The number of pulses counted by CT ₅ is greater than the value obtained by correcting the error of the setting value of numerical setting device DS ₃ . Conversely, if the instrument under test has a positive error, the number of pulses counted by the counter CT ₅ will be smaller than the error-corrected value set by the numerical value setter DS ₃ . Therefore, if the counted value of counter CT ₅ exceeds the value set by numerical setting device DS ₃ with error correction, the instrument under test has a negative error, and if it falls below, it has a positive error. It can be seen that it has

When the count value of counter CT ₅ is smaller than the count value of presettable up-down counter CT ₂ , that is, the allowable lower limit pulse number, the numerical comparison circuit
The outputs of CP ₃ and CP ₄ are both at low level. The low level signal from the numerical comparator circuit CP ₃ closes the AND gate G ₉ so that the transistor T _r1 is not conductive and the light emitting diode PD ₁ indicates that the error of the instrument under test is within the permissible range. does not light up, but is inverted by the inverter I _o2 and makes the transistor T _r2 conductive, so that the light emitting diode PD ₂ lights up, indicating that the positive tolerance range is exceeded. Further, since the low level signal from the numerical comparison circuit _CP4 does not conduct the transistor _Tr3 , the light emitting diode _PD3 , which indicates that the negative tolerance range is exceeded, does not light up.

When the count value of counter CT ₅ is greater than or equal to the count value of presettable up-down counter CT ₁ and less than the count value of presettable up-down counter CT ₂ , that is, the error of the instrument under test is within the allowable error range. At this time, the output of the numerical comparison circuit _CP3 is at a high level, so the output of the inverter _Io2 is at a low level, the transistor _r2 is not conductive, and the light emitting diode _PD2 is not lit. Numerical comparison circuit CP ₄
Since the output of is low level, the transistor
T _r3 is not conductive and the light emitting diode PD ₃ does not light up, but the high level signal conducts the transistor T _r1 through the inverter I _o3 and the opened AND gate G ₉ , so the error is within the allowable range. The light emitting diode PD ₁ lights up to indicate that there is.

When the count value of counter CT ₅ is larger than the count value of presettable up-down counter CT ₂ , that is, the allowable upper limit pulse number, the numerical comparison circuit
The outputs of CP ₃ and CP ₄ are both at high level. The high level signal from the numerical comparison circuit CP ₃ is inverted by the inverter I _o2 and does not make the transistor _r2 conductive, so the light emitting diode PD ₂ does not light up. In addition, the high level signal from the numerical comparison circuit CP ₄ is
It is inverted in the inverter I _o3 and closes the AND gate G ₉ , so that the transistor T _r1 is not conductive and the light-emitting diode PD ₁ does not light up, but on the other hand it conducts the transistor T _r3 , so that the negative tolerance range is exceeded. light emitting diode to indicate what is happening
PD ₃ lights up.

As described above, by using this embodiment, even if there is an error in the power-frequency conversion means, the error can be corrected and the error in the inductive watt-hour meter 1 can be corrected even when the inductive watt-hour meter 1 is installed. You can check whether it is within the tolerance range, exceeds the positive tolerance range, or exceeds the negative tolerance range.

Note that in this example, the allowable upper limit pulse number and upper limit pulse number were counted using presettable up-down counters CT ₁ and CT ₂ , but the allowable upper limit pulse number and upper limit pulse number are counted when the error of the power-frequency conversion means is assumed to be 0. The possible upper and lower limit pulse numbers are values obtained by adding or subtracting the setting value of the numerical setting device DS ₄ to the setting value of the numerical setting device DS ₃ , so the presettable up-down counters CT ₁ and CT ₂ Instead, two numerical value setters are provided to directly set these values, and these set values are corrected according to the error of the power-frequency conversion means to determine the allowable upper and lower limit pulse numbers. is also possible.

In this embodiment, the light emitter/receiver 6 is the optical rotation speed detection means of the present invention, the alligator clip 2 is the voltage extraction means, the power-frequency conversion circuit WF, the programmable frequency division circuit DV, and the numerical value setter DS _1. is electric power −
The frequency conversion means includes a numerical value setter DS ₂ as a rotation speed setting means, a counter CT ₅ as a counter means, presettable up-down counters CT ₁ , CT ₂ , a counter CT ₄ , a numerical comparison circuit CP ₂ , and a numerical value setting device. _DS3 ,
DS ₄ , AND gates G ₅ , G ₆ , inverter I _o1 serve as limit pulse number setting means, numerical comparison circuits CP ₃ , CP ₄ ,
Light emitting diode PD ₁ ~ PD ₃ , transistor T _r1 ~
T _r3 , inverters I _o1 , I _o3 , AND gate G ₉ serve as determination means, numerical value setter DS ₅ , master error setting encoder 9, counter CT ₆ , numerical comparison circuit CP ₅ , three-input AND gate G ₃ , NAND gate G ₄ , AND gate G ₇ OR gate G ₃ is the master error correction means,
They correspond to each other.

As explained above, the present invention includes an optical rotation speed detecting means for optically detecting the disk rotation speed of a meter under test, and a voltage extraction device that is detachably connected to the voltage terminal of the meter under test and extracts the voltage. means, a split current transformer that is detachably attached to the load circuit and detects the load current, and a voltage that is proportional to the electric power from the voltage taken out by the voltage extraction means and the load current detected by the split current transformer. a power-to-frequency conversion means for generating pulses at a frequency of a given frequency; and a rotation speed setting means for setting a disk rotation speed of the instrument under test necessary for the test.
a counter means for counting the number of pulses generated by the power-frequency conversion means while the disk of the instrument under test rotates at the set rotation speed; a limit pulse number setting means for setting an upper limit and a lower limit of the number of pulses generated by the power-frequency converting means while the power-frequency conversion means is rotating; and master error correction means for correcting the upper limit value set by the limit pulse number setting means in accordance with the error of the power-frequency conversion means, , the data necessary for the test is obtained from the inductive watt-hour meter as it is installed using the optical rotation speed detection means, voltage extraction means, and split type current transformer, and simple pulse processing of counting and comparing the number of pulses is performed. The test shall be carried out by
Furthermore, since the error of the power-frequency conversion means is reduced to 0 by numerically correcting the upper and lower limit values set by the limit pulse number setting means, it is possible to test the inductive watt-hour meter with it installed. I can,
Cost reduction can be achieved, and errors in the built-in power-frequency conversion means can be easily corrected for each device. Thereby, at the manufacturing stage, it is only necessary to measure the error of the power-frequency conversion means, and further cost reduction can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a diagram showing signal states in the embodiment of FIG. 1. 1...Inductive watt-hour meter, 2...Alligator clip, 4...Split type current transformer, 5...Disc, 6...Light emitter/receiver, 9...Encoder for master error setting, WF
...Power-frequency conversion circuit, DV...Programmable frequency divider circuit, _CT1 , _CT2 ...Preset pull-up/down counter, _CT3 to _CT6 ...Counter,
DS ₁ to _{DS 5} ... Numerical setting device, CP ₁ to CP ₅ ... Numerical comparison circuit, PD ₁ to _{PD 3} ... Light emitting diode, T _r1 to
T _r3 ... Transistor, I _o1 ~ I _o3 ... Inverter,
G ₃ ... three-input AND gate, G ₄ ... NAND gate, G ₅ ~ _{G 7} , G ₉ ... AND gate, G ₈ ... OR gate.

Claims (1)

[Claims] 1. Optical rotation speed detection means for optically detecting the disk rotation speed of the meter under test, voltage extraction means that is detachably connected to the voltage terminal of the meter under test and takes out the voltage, and A split current transformer that is attached to the unit and detects the load current, and a power source that generates pulses with a frequency proportional to the power from the voltage taken out by the voltage extraction means and the load current detected by the split current transformer. a frequency conversion means, a rotation speed setting means for setting the disk rotation speed of the instrument under test necessary for the test, and a power-frequency conversion means that generates power while the disk of the test instrument rotates at the set rotation speed. A counter means for counting the number of pulses and an upper limit value and a lower limit value for the number of pulses generated by the power-frequency conversion means while the disk of the instrument under test rotates at the set rotational speed within an allowable error range. determining means for determining whether the number of pulses of the counter means is between an upper limit value and a lower limit value set by the limit pulse number setting means; and an upper limit value set by the limit pulse number setting means. and master error correction means for correcting the lower limit value according to the error of the power-frequency conversion means.