JPH03210789A - Thin film el element - Google Patents
Thin film el elementInfo
- Publication number
- JPH03210789A JPH03210789A JP2004156A JP415690A JPH03210789A JP H03210789 A JPH03210789 A JP H03210789A JP 2004156 A JP2004156 A JP 2004156A JP 415690 A JP415690 A JP 415690A JP H03210789 A JPH03210789 A JP H03210789A
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- JP
- Japan
- Prior art keywords
- film
- electrode
- layer
- dielectric layer
- electrodes
- Prior art date
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Abstract
Description
【発明の詳細な説明】
産業上の利用分野
この発明はキャラクタやグラフィック等の表示に用いる
薄膜EL素子に関するものであり、更に詳しくは、薄膜
EL素子の外部導出端子電極の構造に関するものである
。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a thin film EL element used for displaying characters, graphics, etc., and more specifically to the structure of an external lead terminal electrode of a thin film EL element.
従来の技術
従来より電場発光蛍光体を用いたX−Yマトリックス型
固体映像表示装置が知られている。この装置は、電場発
光層の両面に水平平行電極群と垂直平行電極群とを互い
に直交するように配置し、それぞれの電極群に接続され
た給電線により外部駆動回路を通して信号を加えて、画
電極群の交点部分の電場発光層(以下EL発光体層と略
称する)を発光させ(この交点部分面を絵素と称する)
、発光した絵素の組合せによって文字記号、図形などを
表示させるものである。2. Description of the Related Art XY matrix type solid-state image display devices using electroluminescent phosphors have been known. This device arranges a group of horizontal parallel electrodes and a group of vertical parallel electrodes on both sides of an electroluminescent layer so as to be orthogonal to each other, and applies a signal through an external drive circuit using a power supply line connected to each electrode group to produce an image. The electroluminescent layer (hereinafter referred to as EL emitter layer) at the intersection of the electrode groups is caused to emit light (this intersection area is referred to as a picture element).
, characters, symbols, figures, etc. are displayed by a combination of emitted picture elements.
第4図および第5図に従来の薄膜EL素子の断面構造を
示す、ここで用いられる固体映像表示装置の表示板とし
ては、通常ガラスなどの透光性基板l上に透明な水平平
行電極群である透明電極2を形成し、その上に第1誘電
体層3、EL、発光体層4、第2誘電体層5を順次積層
し、さらにその上に垂直平行電極群である背面電極6を
下層の透明電極2に直交する配置で積層して形成する。Figures 4 and 5 show the cross-sectional structure of a conventional thin film EL element.The display plate of the solid-state image display device used here is usually a group of transparent horizontal parallel electrodes on a transparent substrate l such as glass. A transparent electrode 2 is formed, and a first dielectric layer 3, an EL layer, a light emitting layer 4, and a second dielectric layer 5 are sequentially laminated thereon, and a back electrode 6, which is a group of vertically parallel electrodes, is formed on top of the transparent electrode 2. are laminated in an arrangement perpendicular to the lower transparent electrode 2.
−般に透明電極2としては平滑な透光性基板l上に酸化
錫や錫添加酸化インジウム(以下ITOと略称する)を
被着し、所望の形状にバターニングすることにより形成
される。これに直交し、対向する背面電極6としてはA
lなどの金属膜番真空蒸着などにより成膜し所望の形状
にパターニングすることにより形成される。ここで、透
明電極2と背面電極6とを外部回路と接続する方法とし
て半田付が一般に用いられている。ところが、透明電極
2のITOおよび背面電極6のAlともに半田付性が悪
い、そこで、透明電極2および背面電極6の外部導出端
子電極7の作り方として、1つの方法は、背面電極6の
バターニングが終了したのちにストライプ状の窓が形成
されたメタルマスクを用いて真空蒸着法によりストライ
プ状の金属膜7(たとえばNi/Cr)を成膜する方法
(第4図)、また、別の方法として、背面電極6用のA
f膜を成膜したのちに引続き周辺に外部導出端子電極用
の金属膜8(たとえばNi)を成膜し、エツチング用の
レジストパターンを形成して湿式エツチングにより背面
電極6と外部導出端子電極のパターンを順次形成する(
第5図)といった方法がとられている。- Generally, the transparent electrode 2 is formed by depositing tin oxide or tin-doped indium oxide (hereinafter abbreviated as ITO) on a smooth light-transmitting substrate l and patterning it into a desired shape. A back electrode 6 perpendicular to this and facing
It is formed by forming a film by vacuum evaporation or the like and patterning it into a desired shape. Here, soldering is generally used as a method for connecting the transparent electrode 2 and the back electrode 6 to an external circuit. However, both ITO of the transparent electrode 2 and Al of the back electrode 6 have poor solderability. Therefore, one method for making the external lead terminal electrode 7 of the transparent electrode 2 and the back electrode 6 is to pattern the back electrode 6. After the process is completed, a striped metal film 7 (for example, Ni/Cr) is formed by vacuum evaporation using a metal mask in which striped windows are formed (FIG. 4), or another method. As, A for the back electrode 6
After forming the f film, a metal film 8 (for example, Ni) for the external lead-out terminal electrode is subsequently formed around the periphery, a resist pattern for etching is formed, and the back electrode 6 and the external lead-out terminal electrode are formed by wet etching. Form the pattern sequentially (
(Fig. 5) is used.
発明が解決しようとする課題
メタルマスクを用いる方法では、(+)精細度が高いも
のはできない、(2)大画面には向かない、(3)メタ
ルマスクの取扱いが難しい、(4)下部電極(透明電極
2および背面電極(6)との位置合わせが難しい、とい
った問題がある。また、湿式エツチング法では、(1)
外部導出端子電極7用の金属膜はEL素子の周辺にのみ
成膜しなくてはならないので、背面電極6用の金属膜を
成膜したのちに有効表示部分を覆うような成膜用のマス
クに替えて外部導出端子電極7用の金属膜を成膜しなけ
ればならない、(2)エツチングを成膜した金属膜の数
だけ行わなければならないため工程が複雑になる、とい
った問題がある。Problems to be Solved by the Invention Methods using metal masks (+) cannot produce high definition images, (2) are not suitable for large screens, (3) are difficult to handle metal masks, (4) lower electrodes (There is a problem that alignment with the transparent electrode 2 and the back electrode (6) is difficult.In addition, in the wet etching method, (1)
The metal film for the external lead terminal electrode 7 must be formed only around the EL element, so after forming the metal film for the back electrode 6, a mask for film formation that covers the effective display area is used. There are problems such as (2) etching has to be performed for the number of metal films that have been formed, which makes the process complicated.
課題を解決するための手段
本発明によれば、透光性基板上に、透明電極、第1誘電
体層、EL発光体層、第2誘電体層および背面電極を順
次積層してなる薄膜EL素子において、透明電極と背面
電極の両方の外部導出端子電極が、背面電極用の金属膜
を成膜するときに同時に同一膜を外部導出端子電極部分
にも成膜しパターンを形成したのち、無電解メツキ法に
よりNiを主成分とする膜を積層することにより形成す
ることができる。Means for Solving the Problems According to the present invention, a thin film EL is produced by sequentially laminating a transparent electrode, a first dielectric layer, an EL light emitting layer, a second dielectric layer and a back electrode on a transparent substrate. In the device, when forming the metal film for the back electrode, the same film is also formed on the external lead terminal electrode part to form a pattern, and then the external lead terminal electrodes of both the transparent electrode and the back electrode are formed. It can be formed by laminating films containing Ni as a main component by electrolytic plating.
作用
透明電極と背面電極の両方の外部導出端子電極を無電解
メツキ法により同時に形成することができる。しかも、
メツキにより形成された最上層膜は半田付は性のよいN
iを主成分とする膜であるから外部回路との接続を半田
付で行なうことができる。Both the working transparent electrode and the back electrode, which lead out to the outside, can be formed simultaneously by electroless plating. Moreover,
The top layer film formed by plating is made of N, which has good soldering properties.
Since the film is mainly composed of i, it can be connected to an external circuit by soldering.
実施例
第1図および第2図は本発明にかかる薄膜EL素子の背
面電極および透明電極の外部導出端子電極部分の構造を
表す断面図を、第3図は同じく平面図を示す、第1図、
第2図および第3図において、1は透光性基板であり、
2は透明電極である。Embodiment FIGS. 1 and 2 are cross-sectional views showing the structure of the back electrode and the external lead-out terminal electrode portion of the transparent electrode of a thin film EL element according to the present invention, and FIG. 3 is a plan view thereof. ,
In FIGS. 2 and 3, 1 is a transparent substrate;
2 is a transparent electrode.
その上に第1誘電体層3、EL発光体層4、第2誘電体
層5、そして背面電極6が形成されている。A first dielectric layer 3, an EL light emitter layer 4, a second dielectric layer 5, and a back electrode 6 are formed thereon.
透明電極2の第1の外部導出端子電極9および背面電極
6の第2の外部導出端子電極10は之透明電極2および
背面電極6にそれぞれ一部が重なるように形成されてい
る。そして、第1および第2の外部導出端子電極9.1
0の下層膜11は背面電極6と同一膜であり、上層膜1
2は無電解メツキ法により形成されたNiを主成分とす
る膜である。The first external lead terminal electrode 9 of the transparent electrode 2 and the second external lead terminal electrode 10 of the back electrode 6 are formed so as to partially overlap the transparent electrode 2 and the back electrode 6, respectively. Then, the first and second external lead-out terminal electrodes 9.1
The lower layer film 11 of 0 is the same film as the back electrode 6, and the upper layer film 1
2 is a film mainly composed of Ni, which was formed by an electroless plating method.
次に、具体的な例を示す、透光性基板1は、ガラス基板
であり、コーニング社の7059ガラスを用いた。なお
、透光性基板lの大きさは240■xiso閣で厚さ1
.l閣である。透光性基板1上に、直流スパッタリング
法により基板温度400″C、ガス圧0.8Pa(アル
ゴン対酸素の分圧比4:1)で厚さ600nmのITO
膜を形成した。このときのITollfiの抵抗率は2
.2X10“4Ω・cmであった。その後ITO膜をフ
ォトリソグラフィの技術によりストライプ状に加工した
。パターン間隔0.3閣で0゜23閣幅のパターンを形
成した。このようにして、ストライプ状の透明電極2を
形成した。その上にチタン酸ジルコン酸ストロンチウム
[Sr (TiXZr+−x)03]焼結体を基板温度
400℃でスパッタリングすることにより、厚さ300
nmの上記組成式の酸化物誘電体膜を第1誘電体層3
として形成した。さらに、その上に共蒸着法により、基
板温度200 ”Cで厚さ500nmのマンガン添加硫
化亜鉛膜からなるEL発光体層4を形成した。真空中4
50°Cで1時間熱処理の後、その上にタンタル酸バリ
ウム[BaTa2O6]焼結体を、基板温度150°C
でスパッタリングする事により厚さ300nmの酸化物
誘電体膜を第2誘電体層5として形成した。Next, the light-transmitting substrate 1, which will be described as a specific example, is a glass substrate, and 7059 glass manufactured by Corning Co., Ltd. was used. In addition, the size of the transparent substrate l is 240cm and the thickness is 1
.. It is a palace. ITO with a thickness of 600 nm was deposited on a transparent substrate 1 by direct current sputtering at a substrate temperature of 400''C and a gas pressure of 0.8 Pa (partial pressure ratio of argon to oxygen 4:1).
A film was formed. At this time, the resistivity of ITolfi is 2
.. The ITO film was then processed into a stripe shape using photolithography. A pattern with a width of 0°23 cm was formed with a pattern interval of 0.3 cm. In this way, the stripe-like A transparent electrode 2 was formed on which a sintered body of strontium zirconate titanate [Sr (TiXZr+-x)03] was sputtered at a substrate temperature of 400°C to a thickness of 300°C.
nm of the oxide dielectric film having the above composition formula as the first dielectric layer 3
Formed as. Furthermore, an EL light emitting layer 4 made of a manganese-doped zinc sulfide film having a thickness of 500 nm was formed thereon by co-evaporation at a substrate temperature of 200''C.
After heat treatment at 50°C for 1 hour, a barium tantalate [BaTa2O6] sintered body was placed thereon at a substrate temperature of 150°C.
An oxide dielectric film having a thickness of 300 nm was formed as the second dielectric layer 5 by sputtering.
さらに、その上に厚さ150nmのAffi膜を有効表
示部と外部導出端子電極部の両方に真空蒸着し、蒸着し
たA!膜をフォトリソグラフィ技術によりストライプ状
に加工し、背面電極6と第1および第2の外部導出端子
電極9.IOの下層@11を形成した。Furthermore, an Affi film with a thickness of 150 nm was vacuum-deposited on both the effective display area and the external lead-out terminal electrode area, and the A! The film is processed into stripes by photolithography, and a back electrode 6 and first and second external terminal electrodes 9 are formed. The lower layer of IO @11 was formed.
第1および第2の外部導出端子電極9,10の上層膜1
2は無電解メツキ法により形成した。用いた無電解Ni
メツキ液は、Bの含量が約1%である。メツキ温度30
°Cで約8分間メツキを行ったところ300nmの厚み
のNiメツキ膜が得られた。なお、メツキ時にメツキの
不要な部分についてはレジストでマスキングした。Upper layer film 1 of first and second external lead-out terminal electrodes 9 and 10
No. 2 was formed by an electroless plating method. Electroless Ni used
The plating liquid has a B content of about 1%. Metsuki temperature 30
When plating was performed at °C for about 8 minutes, a Ni plating film with a thickness of 300 nm was obtained. In addition, during plating, unnecessary portions of plating were masked with resist.
以上のようにして作成したfil14EL素子の外部導
出端子電極9,10と外部回路の端子電極(Cu箔のパ
ターンにSnメツキを施しである)とを半田付により接
続したところ良好な接続を得ることができた。A good connection was obtained when the external lead-out terminal electrodes 9 and 10 of the fil14EL element created as described above were connected to the terminal electrodes of the external circuit (Cu foil pattern with Sn plating) by soldering. was completed.
なお、Bの含量については実施例では1%のものを用い
たがメツキ膜の安定性を考慮する場合少なくとも0.1
%含まれていればよい。Regarding the content of B, 1% was used in the example, but when considering the stability of the plating film, it should be at least 0.1%.
It is sufficient if it contains %.
発明の効果
以上のように本発明によれば、透明電極と背面電極の両
方の外部導出端子電極を、背面電極用の金属膜を成膜す
るときに同時に同一膜を外部導出端子電極部分にも成膜
しパターンを形成したのち、無電解メツキ法によりNi
を主成分とする膜を積層することにより形成することが
できるため、従来の方法に比ベニ程が簡素化でき薄膜E
L素子の製造コストの低減に寄与できる。Effects of the Invention As described above, according to the present invention, when forming the metal film for the back electrode, the same film is also applied to the external lead terminal electrode portion of both the transparent electrode and the back electrode. After forming a film and forming a pattern, Ni is deposited by electroless plating method.
Because it can be formed by laminating films whose main components are
This can contribute to reducing the manufacturing cost of the L element.
第1図および第2図は本発明にかかる薄膜ELパネルの
断面図、第3図は同じく本発明にかかる薄膜ELパネル
の平面図、第4図および第5図は従来の薄1IELパネ
ルの断面図である。
1・・・・・・透光性基板、2・・・・・・透明電極、
3・・・・・・第1誘電体層、4・・・・・・EL発光
体層、5・・・・・・第2誘電体層、6・・・・・・背
面電極、9・・・・・・第1の外部導出端子電極、10
・・・・・・第2外部導出端子電極、11・・・・・・
最上N膜、12・・・・・・最下層膜。1 and 2 are cross-sectional views of a thin-film EL panel according to the present invention, FIG. 3 is a plan view of a thin-film EL panel according to the present invention, and FIGS. 4 and 5 are cross-sectional views of a conventional thin-film EL panel. It is a diagram. 1...Transparent substrate, 2...Transparent electrode,
3...First dielectric layer, 4...EL light emitter layer, 5...Second dielectric layer, 6...Back electrode, 9... ...First external lead-out terminal electrode, 10
...Second external lead-out terminal electrode, 11...
Top N film, 12... bottom layer film.
Claims (1)
体層、第2誘電体層、及び背面電極を順次積層してなる
薄膜EL素子において、前記透明電極および前記背面電
極の外部導出端子電極が金属膜の積層膜でできており、
かつ前記積層膜の最下層膜が前記背面電極と同一膜で形
成され、最上層膜が無電解メツキ法により形成されBを
少なくとも0.1%含むNiを主成分とする膜で形成さ
れていることを特徴とする薄膜EL素子。In a thin film EL device in which a transparent electrode, a first dielectric layer, an EL light emitter layer, a second dielectric layer, and a back electrode are sequentially laminated on a light-transmitting substrate, an external surface of the transparent electrode and the back electrode is provided. The lead-out terminal electrode is made of a laminated metal film,
and the lowermost layer of the laminated film is formed of the same film as the back electrode, and the uppermost layer is formed of a film mainly composed of Ni containing at least 0.1% B and formed by an electroless plating method. A thin film EL device characterized by the following.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004156A JPH03210789A (en) | 1990-01-11 | 1990-01-11 | Thin film el element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004156A JPH03210789A (en) | 1990-01-11 | 1990-01-11 | Thin film el element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03210789A true JPH03210789A (en) | 1991-09-13 |
Family
ID=11576890
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004156A Pending JPH03210789A (en) | 1990-01-11 | 1990-01-11 | Thin film el element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03210789A (en) |
-
1990
- 1990-01-11 JP JP2004156A patent/JPH03210789A/en active Pending
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