JPH03210814A - Driver circuit - Google Patents

Abstract

PURPOSE:To increase the amplitude of an output voltage by constituting a differential switch with 1st, 2nd, and 3rd, 4th differential TRs and giving an output switching signal to each base of 2nd and 4th and 3rd and 5th differential TRs respectively in in-phase and giving it between the groups in opposite phase. CONSTITUTION:When differential TRs 3, 6 are turned on by an output voltage switching signal, a current from a current source 2 all flows from the differential TR 3 to a reference voltage source 1 and does not flow to a load resistor 9. An extraction current of a current source 7 is all supplied from the differential TR 6 through a resistor 8 and the load resistor 9. When the differential TRs 4, 5 are turned on, the current supplied from the current source 2 is branched from the differential TR 4 to the resistor 8 and the load resistor 9. The extracted current from the current source 7 is supplied from the reference voltage source 1 by the differential TR 5 and does not flow to the load resistor 9. Thus, an output voltage being twice more than a conventional circuit is obtained with a high speed TR with a comparatively small current capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a driver circuit that drives a load at a predetermined voltage level.

[Prior Art] Next, the configuration of a driver circuit according to the prior art will be explained with reference to FIG. 2.

The circuit shown in FIG. 2 is used in IC testers and the like.

11 in Fig. 2 gives Vo□ to the load resistor 16 when rHJ, and V when rLJ. Reference power supply that gives L, 12
and 13 are transistors that control the current, 14 is a current source that supplies current to the load resistor 16 under the control of the transistors 12 and 13, and 15 is a resistor that determines the output impedance of the driver circuit, and the resistance value is R8. The resistance value of the load resistor 16 is assumed to be RL.

In FIG. 2, transistors 12 and 13 are used as switches.

Next, the operation of the circuit shown in FIG. 2 will be explained using the waveform diagram shown in FIG.

FIG. 4A is a waveform diagram of the output voltage switching signal H/L,
It is applied to the bases of transistors 12 and 13 as a differential signal.

Therefore, the transistors 12 and 13 function as differential switches and control the current drawn by the current source 14.

When the transistor 13 is on, part of the current drawn by the current source 14 flows through the load resistor 16, and the output voltage Vo is Vo = 2XRt, / (RO+RL) ・
It becomes VOL.

When the transistor 13 is off, only the current supplied from the reference power supply 11 via the resistor 15 flows through the load resistor 16, so the output voltage Vo is vo=2・RL/(Ro
+RL)・vOI(.

Note that since the output voltages are normally set to be Ro'' RL, the output voltages are voL and V.H, respectively.

[Problems to be Solved by the Invention] FIG. 4A is a waveform diagram of the collector current of the transistor 12, and FIG. 4 is a waveform diagram of the collector current of the transistor 13.

Figure 4: When both are on, 2 (VO) I VOL) /RO.

Therefore, although the collector current is proportional to the output voltage amplitude, the maximum collector current of a high speed transistor such as that used in FIG. 2 is generally not large.

In addition, Fig. 4 A is 2 (Van VOL) /R
01 4th figure 2 is 2 (VOHVOL) / RO1 4th figure is 2 (2 (RO+Rt) VOR2RL ”
Voi, )/RO/ (RO+RL), 4th figure's name is 2Voo/(RO+RL), 4th figure's name is 2V
OH/ (R.

+RL), Fig. 4 Sai's Ha is 2Vot, / (Ro +
Rt, ) The 4th figure force is 2RL / (RO+Rt)
・VOH1 4th figure force is 2RL / (RO+RL
)・Represents voL.

Therefore, in order to increase the maximum current, a method has been proposed in which a pair of differential transistors are arranged in parallel, but this increases the collector capacitance, resulting in a problem that the processing speed decreases.

The object of the present invention is to provide a high-speed driver circuit in which the maximum collector current of the transistors 12 and 13 is the same as that of the conventional circuit shown in FIG. 2, and the amplitude of the output voltage is doubled.

[Means for Solving the Problem] In order to achieve this object, the present invention includes a reference voltage source 1 whose setting voltage is set to an intermediate value of the output voltage, a first current source 2, and a reference voltage source. 1, a second differential transistor 4 connected between the first current source 2 and the load resistor 9, and a reference voltage a1.
7X1 and the second voltage source 7, a third differential transistor 5 connected between the load resistor 9 and the second current source 7, a fourth differential transistor 6 connected between the load resistor 9 and the second current source 7, Reference voltage source 1
The first differential transistor 3 and the second differential transistor 4 constitute a differential switch, and the third differential transistor 5 and the fourth differential transistor constitute a differential switch. The differential transistor 6 constitutes a differential switch, and the base of the first differential transistor 3 and the third differential transistor 5
A first output switching signal in phase is supplied to the base of the second differential transistor 4, and a first output switching signal in phase with the first output switching signal is supplied to the base of the second differential transistor 4 and the base of the fourth differential transistor 6. A second output switching signal is provided.

Next, the configuration of the driver circuit for an IC tester according to the present invention will be explained with reference to FIG.

In Fig. 1, 1 is a reference voltage source, 2 is a current source, 3 and 4 are differential transistors, and 5 and 6 are differential transistors. Differential transistors constitute a differential switch, and each base is supplied with an output switching signal.

Note that the output switching signal is applied to the differential transistors 3 and 5 and the differential transistors 4 and 6 in the same phase, respectively, and the signals in each group are in opposite phase.

Resistor 8 and load resistor 9 are the same as resistor 15 and load resistor 1 in FIG.
It is the same as 6.

Next, the waveform diagram in FIG. 3 will be explained with reference to FIG. 1.

FIG. 3A is a waveform diagram of the output voltage switching signal H/L,
3A to 3E represent the collector currents of the differential transistors 3 to 6.

Figure 3 represents (VORV.L)/RO.

The force in the third figure is the current flowing through the resistor 8, and the force in the third figure is
This is the current flowing through the load resistor 9.

The third diagram shows the output voltage Vo.

In addition, the power of the third figure is ((1-RL /RO)Voo+
(1+RL/RO) VOL)/(RO+R
L), the evening of the third power is ((1+RL/RO)
V. , + (1-RL /RO) VOL) / (R
O + RL ), Figure 3 Ki no Chi is 2VaH/ (Ro +
RL), Figure 3 is 2VOL/ (RO+RL)
, Te of the third diagram is 2RL/ (Ro + RL) ・
Van, the third figure is 2RL/ (RO+RL)
・Represents voL.

[Action Co. Next, the operation of FIG. 1 will be explained.

V when the predetermined output voltage is rHJ. l(, rLJ
V when . It becomes L. At this time, the value of the reference voltage source 1 is set to V. ) I + V OL, and set the values of current sources 2 and 7 to (Van VOL) / RO.

When the differential transistors 3 and 6 are turned on by the output voltage switching signal, all current from the current source 2 flows from the differential transistor 3 to the reference voltage source 1 and does not flow to the load resistor 9.

All current drawn by current source 7 is supplied from differential transistor 6 through resistor 8 and load resistor 9.

At this time, the output voltage Vo is Vo = 2 RL / (RO + RL) ・V
at.

becomes.

Further, the collector currents of the differential transistors 3 and 6 are each (Van V.L)/Ro.

When the differential transistors 4 and 5 are on, the current supplied by the current source 2 is shunted from the differential transistor 4 to the resistor 8 and the load resistor 9.

The current drawn by the current source 7 is supplied from the reference voltage source 1 by the differential transistor 5 and does not flow through the load resistor 9.

At this time, the output voltage Vo is vo=2・RL/(Ro+RL)・voH.

Further, the collector currents of the differential transistors 4 and 5 are respectively (■.uV.L)/RO.

Therefore, in FIG. 1, the maximum collector current (V OH
-Vot, ) / Ro, the output voltage Vo when rHJ is Vo = 2 ・RL / (RO+Rt) ・V
OR, and the output voltage Vo when rLJ is vO=
2.RL/(RO+RL).VOL will be obtained.

Note that since R8 is normally set to RL for output matching, the output voltage is V when rHJ. It becomes H, and when it is "L" it becomes V. It becomes L.

[Effects of the Invention] According to the present invention, the required maximum collector current can be halved in order to obtain the same output voltage as in the prior art.

Therefore, an output voltage twice as high as that of the conventional transistor can be obtained using a high-speed transistor with a relatively small current capacity.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a driver circuit according to the present invention, FIG. 2 is a configuration diagram of a driver circuit according to the prior art, and FIG.
FIG. 4 is a waveform diagram of the numbered part in the second figure. 1...Reference voltage source, 2...Current source, 3
．． ~6...Differential transistor, 7...
Current source, 8...Resistor, 9...Load resistance, 11...Reference power supply, 12/13...
Transistor switch, 14...Current source, 15
...Resistance, 16...Load resistance.

Claims (1)

[Claims] 1. A reference voltage source (1) whose set voltage is set to an intermediate value of the output voltage, and a first current source (2) connected between the first current source (2) and the reference voltage source (1). 1 differential transistor (3) and a first current source (2
) and a load resistor (9), and a reference voltage source (1) and a second current source (7).
) a third differential transistor (5) connected between the
A fourth differential transistor (6) connected between the load resistor (9) and the second current source (7), and a resistor connected between the reference voltage source (1) and the load resistor (9). (8), the first differential transistor (3) and the second differential transistor (4) constitute a differential switch, and the third differential transistor (5) and the fourth differential transistor (6) constitute a differential switch, the base of the first differential transistor (3) and the base of the third differential transistor (5) are supplied with the first output switching signal in phase, and the second The base of the differential transistor (4) and the base of the fourth differential transistor (6) are supplied with a second output switching signal that is in phase and opposite in phase to the first output switching signal. driver circuit.