JPH03210817A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To protect an insulation film adjacent to an output transistor(TR) and a ground wire from electrostatic destruction by connecting an electrostatic protective diode between both power wires at a ground level in an ECL semiconductor integrated circuit provided with plural ground level wires independent of each other. CONSTITUTION:Two electrostatic protection diodes D1, D2 in opposite polarity are added between 1st and 2nd ground level power supplies GND and GNDA independent of each other. Then if a surge higher than a level of the GNDA is applied to, e.g. an output terminal, the electrostatic protective diode D11 is activated and the increase of the potential of the output terminal is clamped to a diode forward operating voltage VF. Then the destruction of the base.emitter junction of an output emitter follower TR Q13 is prevented. When a surge is applied between the GNA and GNDA, the diode D1 or D2 is operated to clamp both the power supplies. Consequently, the electrostatic dielectric strength of the element or the insulation film is improved against various surge signals.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and in particular, a semiconductor integrated circuit device in which a plurality of mutually independent ground potential power supply wirings are formed in consideration of the influence of simultaneous operation of output circuits. The present invention relates to an electrostatic protection circuit device that enhances the electrostatic withstand voltage of a semiconductor integrated circuit device.

[Prior Art] Emitter-coupled logic circuits (ECL circuits) are well known as digital logic circuits capable of high-speed operation. recent years,
The integration of ICs that use ECL in their internal circuits has progressed significantly, and LSIs with a maximum number of gates exceeding 10,000 gates have appeared. At the same time, ICs have become more multifunctional, and the ECL level and TT
Many of them employ interfaces that can be mixed with L level. However, the high integration of such ICs,
Since multi-functionalization is achieved by making mask patterns finer, it is not necessarily preferable from the standpoint of electrostatic damage.Moreover, with multi-functionalization, the mode of electrostatic damage occurrence is becoming more complex.

Figure 3 shows a circuit diagram of an ECL output circuit having a conventional electrostatic protection circuit. As shown in the figure, a transistor Qll whose base is connected to the input terminal In, and a transistor Qll whose base is connected to the reference potential power supply V ref. connected transistor Q12
means that the emitters are commonly connected and connected to the negative potential power supply VEE via the constant current source Ics, and the collectors are connected to the first ground potential power supply G via collector load resistors R11 and R12, respectively.
Connected to ND. Output emitter follower transistor Q
13 has a collector connected to a second ground potential power supply GNDA independent of GND, a base connected to a connection point between the collector load resistor R12 and the collector of the transistor Q12 on the reference potential side, and an emitter connected to the output terminal. Connected to Out. The output terminal Out is connected to a negative potential power source (for example, -2V) via a resistor outside the integrated circuit device.

In contrast to the configuration of the ECL output circuit described above, the conventional electrostatic protection circuit is configured with a diode whose anode is connected to the output terminal Out and whose cathode is connected to GNDA.

In an era when the gate scale of ICs was still small, a single ground potential power supply was used to supply a common ground potential voltage to internal circuits and output circuits. However, with the increase in gate size, the number of bins in ICs has also increased, and when multiple output limiter followers operate at the same time, large power supply noise is generated, which can induce malfunctions in internal logic circuits. In order to avoid this, it has become common to provide an independent ground potential power source exclusively for the output limiter follower, as shown in FIG.

[Problems to be Solved by the Invention] In the conventional semiconductor integrated circuit device described above, a plurality of mutually independent ground potential power supplies are provided in order to reduce the influence of simultaneous operation of the output circuits, so it is difficult to use a single ground potential. Different electrostatic damage problems occur in integrated circuit devices powered by electric potentials. The electrostatic protection circuit shown in Figure 3 is connected to the output terminal Out.
However, due to the handling of integrated circuit devices, if the terminal of the second ground potential power supply GNDA is in an oven state and a surge is applied to the first ground potential power supply GND, there is no effect at all. The drawback is that it is ineffective. In this case, connecting an electrostatic protection diode from the output terminal to both GNDA and GND is undesirable in terms of high-speed operation because it increases the load capacitance due to the parasitic capacitance of the electrostatic protection diode.

In addition, when handling integrated circuit devices, the GND terminal, GNDA
When a surge is applied between the terminals, there is also a risk that the insulating film between the ground wires connected to these terminals will be destroyed.

[Means for Solving the Problems] A semiconductor integrated circuit device of the present invention includes first and second independent circuits.
An ECL type semiconductor integrated circuit device having a second ground wiring, the ECL having a collector connected to the second ground wiring.
An output emitter follower transistor constituting an output circuit, another circuit in the integrated circuit connected to the first ground wire, and an anode connected to the emitter of the output emitter follower transistor and a cathode connected to the second ground wire. and a second diode having an anode connected to a second ground wiring and a cathode connected to the first ground wiring. Further, if necessary, a third diode is connected in antiparallel to the second diode.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an ECL output circuit portion showing an embodiment of the present invention. The configuration of the ECL output circuit itself is the same as that shown in FIG. and a second ground potential power supply GNDA independent of this, two electrostatic protection diodes DI and D2 are connected in opposite directions to each other.
is added.

Next, the operation of the electrostatic protection circuit of the present invention will be explained.

The output terminal Out is connected from an output pad on the IC chip to an external lead terminal of the package via a bonding wire or the like. The operation when a surge is applied to the output terminal etc. when handling the IC is shown below.

■ When a surge higher than the potential of the second ground potential power supply GNDA is applied to the output terminal: The electrostatic protection diode Dll operates, and the increase in the potential of the output terminal is reduced to the diode's forward operating voltage VF (approximately O, SV).
clamp the output emitter follower transistor Q13 to
prevents damage to the base-emitter junction.

■ When a surge lower than the potential of the second ground potential power supply GNDA is applied to the output terminal: The electrostatic protection diode D2 operates, and a current flows through GNDA, the diode D2, the resistor R12, and the output transistor Q13. Clamp between power supply GNDA and output terminal Out.

■ When a surge higher than the potential of the first ground potential power supply GND is applied to the output terminal: The electrostatic protection diodes DI1 and D2 operate, and the potential rise of the output terminal is reduced to twice the forward operating voltage VF of the diode. (approximately 1.6 V) to prevent the base-emitter junction of the output emitter follower transistor 013 from being destroyed.

■ When a surge lower than the potential of the first ground potential power supply GND is applied to the output terminal: Current flows through the resistor R12 and the output emitter follower transistor Q13, and also through the diode D1 and the output emitter follower transistor Q13. flows and clamps between the power supply GND and the output terminal Out.

■ First ground potential power supply GND - second ground potential power supply G
When a surge is applied between NDA: The electrostatic protection diode D1 or D2 operates to clamp between the two power supplies.

As explained above, according to the present invention, in an ECL type semiconductor integrated circuit device in which a plurality of mutually independent power supplies with ground potentials are provided in order to reduce the influence of simultaneous operation of output circuits, an element can be protected against various surges. Alternatively, the electrostatic withstand voltage of the insulating film can be improved. Furthermore, since the only electrostatic protection diode connected to the output terminal is Dll as before, the load capacitance increases and the output circuit operation becomes slower than when another electrostatic protection diode is connected to this terminal. There isn't.

Next, the arrangement position of the electrostatic protection circuit of the present invention will be explained. two diodes D1 connected in opposite directions,
D2 is placed near the electrode pad to which the wiring for the second ground potential power supply GNDA is connected, and connected to the ground wiring near this electrode pad. With this configuration, even if noise occurs in the GNDA power supply due to simultaneous operation of multiple output circuits, the amount of noise is small because the ground potential is applied to the vicinity of the electrode pad from outside the integrated circuit, so it is possible to protect these areas from static electricity. The influence of noise on the internal circuit via the diode and GND power supply can be minimized.

Next, referring to FIG. 2, a case will be described in which the present invention is applied to an integrated circuit device having a TTL level output buffer.

Although not shown in FIG. 2, it is assumed that the integrated circuit device of this embodiment is provided with the ECL circuit shown in FIG. 3.

As shown in FIG. 2, a transistor Q21 whose base is connected to the input terminal In and a power supply V whose base is at a reference potential
The emitters of the transistors Q22 connected to ref are commonly connected and connected to the negative potential power supply VER via the constant current source IC5, and the collector of the transistor Q21 is connected to the positive potential power supply VCC via the collector load resistor R22. , the collector of the transistor Q22 is connected to the first ground potential power supply GND. Resistor R23, transistor Q23, diode D22, and resistor R24 form a phase dividing circuit between positive potential power supply ■CC and second ground potential power supply GNDA, and the base of transistor Q23 is connected to collector load resistance R22 on the input side. It is connected to the connection point with the collector of transistor Q21. transistor Q24,
The transistor Q25 is Darlington-connected, and the commonly connected collectors are connected to a positive potential power supply ■C through a resistor R26.
C and the base of transistor Q24 is connected to resistor R2.
3 and the collector of the transistor Q23, and the emitter of the transistor Q25 is connected to the output terminal ut to form an off-buffer circuit. The transistor Q26 has a collector connected to the output terminal Out,
The base is the emitter of transistor 023 and diode D
The emitter is connected to the connection point with the second anode.
The on-buffer circuit is connected to the ground potential power supply GNDA. The electrostatic protection circuit also includes diodes D1 and D2 connected in antiparallel between the first ground potential power supply GND and the second ground potential power supply GNDA, and a diode D21 connected in parallel to the transistor Q26. It is made up of.

In the circuit of this embodiment, the power supply G is connected to the output terminal Out.
When a surge with a potential lower than the potential of NDA or power supply GND is applied, it is discharged through the diode D21 or the diodes D1 and D21, and the output terminal Out
When a surge of a potential higher than the potential of power supply GNDA or power supply GND is applied to power supply GNDA or power supply GND, it is discharged through transistor Q26 or transistor Q26 and diode p2. Further, when a surge is applied between the power supply GND and the power supply GNDA, it is discharged through the diode D1 or D2.

[Effects of the Invention] As explained above, the present invention provides an ECL type semiconductor integrated circuit device in which a plurality of mutually independent ground potential wirings are provided in order to reduce the influence of simultaneous operation of output circuits. Since an electrostatic protection diode is connected between both power supply wirings, according to the present invention, the insulating film adjacent to the output transistor and the ground wiring can be protected from electrostatic breakdown. In addition, it is possible to improve the electrostatic withstand voltage without connecting electrostatic protection diodes to multiple power supplies with independent ground potential from the output terminal, thereby preventing an increase in load capacitance due to the parasitic capacitance of the electrostatic protection diodes. can. Further, in accordance with the present invention, an electrostatic protection diode is placed near the electrode pad to which the ground wiring on the side where a large current flows transiently and causes a large potential fluctuation because it is connected to the output transistor is connected to the ground wiring. By connecting to the wiring, even if noise is generated due to parasitic resistance components and parasitic inductance components of bonding wires, package leads, etc. when multiple output circuits operate simultaneously, this noise will be absorbed internally via the electrostatic protection diode. This can prevent the signal from propagating to the circuit.

[Brief explanation of drawings]

1 and 2 are circuit diagrams showing embodiments of the present invention, and FIG. 3 is a circuit diagram showing a conventional example. Dl, D2, Dll, D21... Electrostatic protection diode, D22... Diode, GND...
1st ground potential power supply, GNDA...2nd ground potential power supply, Ics...constant current source, In...input terminal, 0ut-=output terminal, Qll, Q12
, Q21-Q24...transistor, Q13...
・Output emitter follower transistor, Q25, Q2
6... Output transistor, R11, R12, R2
2...Collector load resistance, R23~R26...
Resistance, ■CC...Positive potential power supply, VER...
Negative potential power supply, V ref...Reference potential power supply.

Claims (4)

[Claims] (1) A first ground wiring, a second ground wiring independent of the first ground wiring, a logic circuit connected to the first ground wiring, and a collector connected to the second ground wiring. an output emitter follower transistor; a first diode having an anode connected to the emitter of the output emitter follower transistor and a cathode connected to the second ground wiring; and a first diode having a cathode connected to the first ground wiring. and a second diode having an anode connected to the second ground wiring. (2) A semiconductor integrated circuit device according to claim 1, further comprising a third diode having an anode connected to the first ground wiring and a cathode connected to the second ground wiring. (3) The semiconductor integrated circuit device according to claim 1 or 2, wherein an output circuit whose output level is a TTL level is added between the positive potential power supply wiring and the second ground wiring. (4) A semiconductor integrated circuit device, wherein the second diode or the third diode is arranged near an electrode pad to which the second ground wiring is connected.