JPH03210851A - Inter-processor communication system - Google Patents

Abstract

PURPOSE:To minimize the increase in kinds of interrupt signals even when number of CPUs is increased and to increase one kind of interrupt signals when number of the CPUs is increased by one by sending a message to a prescribed area of a common memory by a processor when the processor makes interruption and sending an interrupt signal added with an identification signal to a storage means of a destination processor. CONSTITUTION:An address of an operating area at interruption corresponds to a CPU for interruption and when a CPUn applies interrupt to a CPU 1, for example an address 1000H is to be accessed. When the address 1000H is accessed, an interrupt signal is sent to an interrupt logic circuit 25 via local memory 33 CPU 32 bus interface 34 bus 10. Moreover, when the other CPU accesses the address 1000H of its own local memory, the other CPU applies interrupt to the CPU 1. Thus, kinds of an interrupt signal inputted to the CPU 1 is one.

Description

Detailed Description of the Invention (Industrial Application Field) This invention relates to an inter-processor communication system, and in particular, an inter-processor communication system (prior art) for exchanging messages between a plurality of processors (multiprocessor system). The figure shows a system diagram of a conventional multiprocessor system using shared memory. As is clear from the figure, the multiprocessor system is composed of a shared memory 11 connected to a system bus 10 and a plurality of CPUI-n. Note that each CPUI~n is provided with a local memory.

As shown in FIG. 6, the shared memory 11 has a number of message writing areas set therein corresponding to the relationship between the sender and recipient of the message. In the above case,
Since there are n CPUs, Hx(n-1) message writing areas are set. The address of the message writing area is known in advance by both parties communicating.

Now, in the multiprocessor system, when exchanging messages, the n processors operate equally. Now, when the CPUn sends a message to the CPUI, the CPUn writes the message to the area n→1 of the shared memory 11, and sends an interrupt signal (n-1) to the CPUI to cause an interrupt.

In this way, when the CPUI~n exchange messages on an equal basis, the messages are stored in the message write area at a predetermined address in the shared memory 11, and each CPU has the message shown in FIG. As shown in the figure, (n-1) types of interrupt signals are input.

(Problem to be Solved by the Invention) When the number of CPUs connected to the system bus 10 of the multiprocessor system increases, the shared memory 11
The number of message writing areas and types of interrupt signals will be greatly increased. That is, when the number of CPUs increases by 1, the number of message writing areas and the types of interrupt signals in the shared memory 11 increase by n.

The capacity of the shared memory 11 can be increased relatively easily with advances in memory technology. However, as the number of types of interrupt signals increases, many hardware components are required to determine the type.

When the number of hardware components increases, not only does the device become larger and more expensive, but depending on the type of system bus, the number of types of interrupts is limited due to the specifications of the system bus, making it impossible to implement.

An object of the present invention is to eliminate the problems of the conventional device, and to
An object of the present invention is to provide an inter-processor communication system that can suppress an increase in the types of interrupt signals as much as possible even when the number of U increases. For example, an object of the present invention is to provide an inter-processor communication system that allows the number of types of interrupt signals to be increased by one when the number of CPUs is increased by one.

(Means and Effects for Solving the Problems) In order to achieve the above object, the present invention provides an inter-processor communication system in which a plurality of processors and a shared memory that can be commonly accessed by the plurality of processors are coupled through a system bus. A first means that generates the same type of interrupt signal to the same interrupt destination, adds its own identification number to the interrupt signal, and sends it; and a second means that detects one type of interrupt signal. The present invention is characterized in that each of the plurality of processors is provided with: and a storage means for sequentially storing the identification numbers.

According to the present invention, when the processor issues an interrupt, the processor sends a message to a predetermined area of the shared memory, and then the first means sends the interrupt signal to which the identification signal is added to the storage means of the destination processor. Send to.

On the other hand, the processor to which the interrupt has been applied uses the second means to detect the occurrence of the interrupt based on the interrupt signal, and sequentially stores the sent identification signal in the storage means.

As a result, an interrupted processor only needs to have one type of interrupt signal detection means.

(Example) The present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a system block diagram of one embodiment of the present invention. In the figure, the same reference numerals as in FIG. 5 indicate the same or equivalent parts.

As shown in the figure, the CPUI illustrated as a representative of CPUI~n connected to the system bus 10 generally includes a local bus 21, a CPU 22, a local memory 23,
, a bus interface 24, and an interrupt logic circuit 25, and similarly, CPUn generally includes a local bus 31, a CPU 32, a local memory 33, a bus interface 34, and an interrupt logic circuit 35.

The shared memory 11 can be the same as the conventional one, and has nX (n-1) message writing areas as explained in FIG. 6.

Although the number of entries in each message writing area may be one, it is preferable to have a plurality of entries. The following explanation is for the case where there are multiple entries.

The interrupt logic circuit 25.35 is composed of a FIFO memory that stores input data in the order in which it is received and outputs it in that order.

In addition, the local memory 33, as shown in the figure,
It has an area used by the processor, an area used for interrupts, an area used for messages, etc. The address of the area used at the time of interrupt corresponds to the CPU that issues the interrupt, for example, the CPU
When n issues an interrupt to the CPUI, it suffices to access address 100OH, for example. This addresses the CPUI interrupt logic 25 on the system bus 10. When address 100OH is accessed, an interrupt signal is sent to interrupt logic circuit 25 via local memory 33 → CPU 32 → bus interface 34 → bus 10. Furthermore, if another CPU accesses address 1000H of its own local memory, it means that an interrupt is issued to the CPUI from the grounded CPU in the same way as described above. Therefore, only one type of interrupt signal is input to the CPUI.

Next, when issuing an interrupt from CPUn to CPUUI,
The operation of PUn will be explained with reference to FIGS. 1 and 2. FIG. 2 is a flowchart showing the processing of the CPUn.

First, it is determined whether the area (n→1 area in FIG. 6) in the shared memory 11 corresponding to the processor to which an interrupt is to be applied is full (step 81).

- If it is not a cup (step S1 is negative), CPUn is
First, a necessary message is written in the entry of the area (the n→1 area) corresponding to the processor to which the interrupt is to be applied in the shared memory 11 (step S2).

This is done by writing the necessary message into the area corresponding to the yl-s-1 area of the message use area of the local memory 33. The written message is sent to a predetermined area of the shared memory 11 via the local memory 33 - CPU 32 -> bus interface 34 -> bus 10.

Next, it is determined whether the message is the first one (step S3). If the judgment is affirmative, the identification number of the own processor is attached and an interrupt is issued to the other processor (step 84).

This interrupt signal is sent to the other party's interrupt logic circuit, that is, the FI
It will be stored in the FO memory.

The processor to which the interrupt has been applied, for example the CPU 1, recognizes the occurrence of the interrupt by having its own CPU 22 take in the output of the interrupt logic circuit 25 via the bus interface 24.

When step S3 is negative, that is, when the message is not the first one, the process returns and is stored in the next entry in the area (n-1 area) in the shared memory 11.

In this way, when all the entries in the area (n→1 area) in the shared memory 11 are filled with messages (step S1 is affirmative), an error code is set (step S5), and a message communication processing request is made. will be rejected.

As described above, according to this embodiment, the processor that issues an interrupt can do so by accessing a specific address (for example, 100OH when issuing an interrupt to the CPUI) of the area of its own local memory that is used at the time of an interrupt. Since interrupts can be generated, the same type of interrupt signal will reach the processors that can be interrupted.

Furthermore, if the same processor, for example, the CPUn, interrupts multiple times and the previously sent message remains in the n-a-1 area, as is clear from the processing in steps S3 and S4, the second and subsequent messages The processor identification number output at the time of the interrupt is not sent to the interrupt logic circuit 25 of the CPUI, that is, to the FIFO memory. As a result, it can be seen that the FIFO memory only needs to have a maximum of (n-1) storage entries.

Next, the processor to which the interrupt is applied (the CPU
The process I) will be explained with reference to FIG.

When there is an interrupt to the CPUI from another processor, for example CPUn, as described above (step 811), the CPU
The contents of one predetermined register in the UI are saved to another (step 512). Next, the CPUI stores in its own interrupt logic circuit 25, that is, the FIFO memory.
Determine whether an identification signal is stored. (Step 513). If the identification signal is stored in the FIFO memory (step 513 is negative), the FIFO memory
I want to read the identification number from the IFO memory.Step 514
), the corresponding task is notified (step 515).

The task waits for notification of the identification number of the processor that issued the interrupt (step 521), and upon notification of the identification number, reads the message from entry 1 of the n-1 area on the shared memory 11 (step 521). Step 522). Next, necessary processing is performed on the message (step 523).

Next, it is determined whether or not there is a message in entry 2 of the n→1 area, and if there is (no in step S24), the process proceeds to step S22, where it is read out and the message is read out. processing is performed (step 523). On the other hand, if step S24 is affirmative, step S
The process advances to step 21 and waits for notification of the identification number of the processor that issued the interrupt.

FIG. 4 shows that processors CPU1 to CPUn that have been interrupted receive the same interrupt signals (1) to (n), respectively, and
The identification number of the other party's processor is stored in the FIFO.

As described above, according to this embodiment, when the interrupted processor CPUI detects the interrupt signal, the FI
By reading the processor identification number from the FO memory, it is immediately possible to know from which processor the interrupt occurred. Furthermore, if this identification number is passed to a task, the shared memory 11 will be accessed from the identification number and the message will be read out. At this time, if messages are stored in a plurality of entries in the shared memory 11, the messages are successively read out in sequence.

As is clear from the above description, each of the processors CPUI~n to which an interrupt is applied need only have one type of interrupt signal detection means, unlike the conventional system.

In the above embodiment, the interrupt signal is generated by accessing a specific address in the local memory of the processor, but the present invention is not limited to this, and the interrupt signal may be generated using other methods. .

(Effect of the invention) As is clear from the above explanation, according to the conventional method, the number of processors connected to the inter-processor communication method is n.
In this case, when the number of processors is increased by one, the number of types of interrupt signals increases by n, but according to the present invention, the number of types of interrupt signals increases by only one,
This has the effect of realizing efficient inter-processor communication with relatively small hardware.

Therefore, the present invention is particularly effective when applied to an inter-processor communication system with a very large number of processors, or when applied to an inter-processor communication system that cannot support many types of interrupts due to limitations such as the system bus.

[Brief explanation of drawings]

Figure 1 is a system block diagram of an embodiment of the present invention, Figure 2 is a system block diagram of an embodiment of the present invention.
FIG. 3 is a flowchart showing the processing of a processor that issues an interrupt; FIG. 4 is an explanatory diagram showing the interrupt signal and identification number input to each processor at the time of an interrupt; Fifth
The figure is a block diagram showing the overall system of the inter-processor communication method, Figure 6 is a conceptual diagram showing the message writing area of the shared memory, and Figure 7 is the interrupt that is input to each processor at the time of an interrupt in the conventional system. It is an explanatory diagram showing a signal. 11...Shared memory, 22.32...CPU, 23
゜33...Local memory, 25.35...Interrupt logic circuit (F I FO)

Claims (1)

[Claims] (1) In an inter-processor communication method in which multiple processors and a shared memory that can be commonly accessed by the multiple processors are connected through a system bus, each of the multiple processors can issue the same type of interrupt to the same interrupt destination. a first means for generating a signal and adding its own identification number to the interrupt signal and transmitting it; a second means for detecting one type of interrupt signal; and a storage means for sequentially storing the identification number. , when each of the plurality of processors receives an interrupt, each of the plurality of processors recognizes the occurrence of the interrupt by detecting the interrupt signal, and issues the interrupt according to the identification number stored in the storage means. An inter-processor communication method characterized by knowing the processor of the other party.