JPH03210892A - Secam system line identification circuit - Google Patents

Abstract

PURPOSE:To eliminate an adjustment component in an ID demodulation circuit by introducing a reference signal to the ID demodulation circuit employing a phase locked loop circuit and providing a means controlling the demodulation axis center frequency of the circuit the same as a reference signal frequency. CONSTITUTION:An input ID signal is inputted to a phase comparator 33 via an input terminal 31. Moreover, a reference signal foID is inputted to a phase comparator 38 via an input terminal 32. An oscillated output from a common voltage controlled oscillator (VCO) 37 is fed to the phase comparators 33, 38. The result of comparison by the phase comparator 33 is led to an output terminal 34 as a demodulated ID signal and inputted to a voltage current converter 35. A key signal from a terminal 41 is fed to a voltage current converter 39 and the voltage current converter 39 is controlled to be conductive/nonconductive depending on the key signal. The control information of the conductive state is stored in a capacitor 40 in the case of nonconduction.

Description

Detailed Description of the Invention [Objective of the Invention] (Industrial Application Field) The present invention provides an S
This invention relates to an ECAM line identification circuit.

(Prior Art) There are three color television signal systems currently used in the world: NTSCSPAL and SECAM. The SECAM method is mainly adopted in communist countries and France.

In the SECAM system, two different color signal information, a (B-Y) signal and a (R-Y) signal, are frequency-modulated using different carrier waves, and are alternately transmitted line-sequentially every horizontal period. On the receiver side, one horizontal period delay line and SE
A switching circuit called a CAM switch synchronizes the above two signals, and the (B-Y) signal is supplied to the (B-Y) demodulator, and the (R-Y) signal is supplied to the (R-Y) demodulator. Color signals are reproduced. The SECAM switch is driven by the output of a flip-flop circuit that inverts every horizontal period, or in order to correctly supply color signal information to each demodulator, the inverting and non-inverting phases of the flip-flop circuit must be line sequential. It is necessary to correctly synchronize with the color signal information sent.

For this purpose, as information for identifying color signal information,
In the SECAM system, an identification signal (ID signal) is transmitted.

That is, the (B-Y) signal is frequency-modulated on a 4.25 MHz carrier wave, and the (R-Y) signal is transmitted line-sequentially by frequency-modulating a 4.46 MHz carrier wave, each with one horizontal period. At the beginning of the signals, unmodulated carrier waves of 4.25 MHz and 4.408 MHz are inserted as ID signals, respectively. I
The D signal is discriminated by an ID identification circuit on the receiving side. The ID identification circuit extracts the ID signal and determines its frequency to reset the flip-flop circuit and return it to the correct phase state.

FIG. 8 shows a conventional SECAM type color demodulation circuit. A television signal input from an antenna (not shown) is demodulated into a composite video signal by a video detection circuit, of which only the chroma signal is input from the input terminal 1. The chroma signal is input to a color difference amplifier 7 and an ID amplifier 10 via a bandpass filter 6 called a bell filter.

The color difference amplifier 7 takes in and amplifies the color difference signal using the gate pulse from the terminal 3, and this color difference signal is supplied to the color difference demodulation circuit 8. The color difference demodulation circuit 8 obtains a baseband color difference signal, and this color difference signal is manually input to the baseband processing circuit 9 . The baseband processing circuit 9 performs de-emphasis processing and also obtains (GY) signals through matrix processing. This results in
Output terminal 91.9□, 9. From (R-Y) signal, (
G-Y) signal and (B-Y) signal are derived.

On the other hand, the ID signal is taken into the ID amplifier 10 using a gate pulse, amplified, and input to the ID demodulation circuit 11. The ID demodulation circuit 11 performs FM demodulation on the ID signal to obtain a baseband ID signal. This demodulated ID signal is supplied to the line discrimination circuit 12. Line discrimination circuit 1
2 determines whether the polarities of the demodulated ID signal and the output line pulse of the flip-flop circuit 13 match or not. If the polarity is reversed, an error pulse that reverses the polarity of the flip-flop circuit 13 is output, and the operating phase of the flip-flop circuit 13 is controlled to be reversed. The output line pulse of the flip-flop circuit 13 is used in the color difference demodulation circuit 8 as a distribution between a (B-Y) signal and a (R-Y) signal that are input line sequentially.

FIG. 9 shows the inside of the ID demodulation circuit 11 in more detail.

The input ID signal from the ID amplifier 10 is input to the phase comparator 15.
The signal from the voltage controlled oscillator (VC0) 16 is compared in phase. And the comparison result is Fuku, WID
It is output as a signal and is also input to the voltage-current converter 17. The voltage-current converter 17 adds the converted current of the voltage given by the resistor 18 to the converted current of the input voltage to create a control current, and the voltage-controlled oscillator 16
is supplied to the control terminal. The voltage controlled oscillator 16 is configured so that its oscillation frequency changes linearly with respect to the control current. This demodulation system is generally referred to as a phase-locked loop for demodulation (PLL), and utilizes the fact that the oscillation frequency of the oscillator is equally locked to the input signal frequency. The change is used as demodulated output.

FIG. 10 is a characteristic diagram and a signal waveform diagram shown to explain the operation of the circuits of FIGS. 8 and 9.

Two ID signals, foB and foR, which have different frequencies, are transmitted alternately in one horizontal period. Now, for the sake of explanation, we will define the intermediate frequency between this frequency f oB and f oR as f ol
Let it be D.

The initial oscillation frequency (free run frequency) of the voltage controlled oscillator 16 of the ID demodulation circuit 11 is controlled by the resistor 18.
Assuming that the detection characteristics of the demodulation circuit are adjusted as shown in Figure 3 (
A). The ID signal extracted from the chroma signal in (B) of the same figure is as shown in (C) of the same figure, and the signal obtained by demodulating this (demodulated ID signal) is as shown in (D) of the same figure when foR. When it is positive polarity and foB, it becomes a negative polarity pulse. Therefore, by comparing the polarities of the line pulse and the demodulated ID signal shown in FIG.

The line pulse is created by dividing the frequency of the horizontal synchronizing signal by 1/2.

If the polarities match as shown in the figure, the result of synchronous integration will be high level and no error signal will be output to the flip-flop circuit 13, but if the polarities are in the opposite phase relationship, the result of synchronous integration will be low level and an error will occur. Output a signal.

In addition, if there is no human ID signal, it can be assumed that a black and white video signal is being broadcast, but in this case, the result of synchronous integration will be "0", and a certain DC ( DC) value. At this time, the line discrimination circuit 12 determines that the state is black and white, outputs a color killer signal, supplies it to the baseband processing circuit 9, cuts off the color difference signal output, and outputs unnecessary signals to the screen. It prevents you from being

(Problem 8 to be Solved by the Invention) According to the S E CAM type line identification circuit described above, in order to set the free run frequency of the voltage controlled oscillator, it is necessary to adjust it using the resistor 18. Such volume adjustment increases the number of work steps in the manufacturing process of the television receiver, leading to an increase in the cost of the television receiver.

In addition, there is a high possibility that the adjustment point may shift due to changes in temperature or over time, and there is a weakness in that it lacks long-term reliability.

SUMMARY OF THE INVENTION An object of the present invention is to provide a SECAM type line identification circuit that can eliminate adjustment components in an ID demodulation circuit.

[Configuration of the Invention (Means for Solving the Problems) This invention provides means for generating a reference signal having a frequency intermediate between two ID signals in a SECAM receiver;
and means for controlling the reference signal so that it is centered on the demodulation axis of an ID demodulation circuit using a phase-locked loop circuit.

(Function) With the above means, a mechanical adjustment means for adjusting the center of the demodulation axis is not required in the ID demodulation circuit, and automatic adjustment control can be obtained.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. The chroma signal passes through an input terminal 21, a bandpass filter 22 called a bell filter, and is input to a color difference amplifier 23 and an ID amplifier 27. The color difference amplifier 23 captures and amplifies the color difference signal using the gate pulse from the terminal 26, and this color difference signal is supplied to the color difference demodulation circuit 24. The color difference demodulation circuit 24 performs demodulation processing using a phase-locked loop circuit, and f03. Demodulation axis switching is realized by switching the foR carrier wave every horizontal period using a line pulse. As a result, a baseband color difference signal is obtained from the color difference demodulation circuit 24, and this color difference signal is input to the baseband processing circuit 25.

In the baseband processing circuit 25, de-emphasis processing is performed, the demodulated color difference signal is delayed by IH as the case may be, and added/subtracted with a direct signal that is not delayed, and a (G-Y) signal is also obtained by matrix processing. As a result, the (RY) signal, (G-Y) signal, and (B-Y) signal are derived from the output terminals 25+, 25□, and 253.

On the other hand, the ID signal is taken into the ID amplifier 27 using the gate pulse, amplified, and input to the ID demodulation circuit 28.

Here, the ID demodulation circuit 28 is supplied with a reference signal fold for demodulation axis adjustment from the color difference demodulation circuit 24. This reference signal fold is the ID
This plays an important role in making the demodulation circuit 28 non-adjustable.

The ID demodulation circuit 28 performs FM demodulation on the ID signal to obtain a baseband ID signal. This demodulated ID signal is supplied to a line discrimination circuit 29. The line discrimination circuit 29 includes a demodulation I
It is determined whether the polarities of the D signal and the output line pulse of the flip-flop circuit 30 match. If the polarity is reversed, an error pulse that reverses the polarity of the flip-flop circuit 30 is output, and the operating phase of the flip-flop circuit 30 is controlled to be reversed. The output line pulse of the flip-flop circuit 30 is used in the color difference demodulation circuit 24 as a distribution between a (B-Y) signal and a (R-Y) signal that are input line sequentially.

FIG. 2 specifically shows the ID demodulation circuit 28.

The human ID signal is input to the phase comparator 33 via the input terminal 31.
is input. Further, the previous reference signal f_old is input to the phase comparator 38 via the input terminal 32. The phase comparators 33 and 38 have a common voltage controlled oscillator (VCO) 3.
The oscillation output from 7 is supplied. The comparison result of the phase comparator 33 is output to the output terminal 34 as a demodulated ID signal, and is also input to the voltage-current converter 35. In the voltage-current converter 35, the converted current of the input voltage is added to the adder 3.
Supply to 6. This adder 36 includes a voltage-current converter 3
The conversion current from 9 is also supplied.

The adder 36 adds the two input converted currents to create a control current and supplies it to the control terminal of the voltage controlled oscillator 37.

The comparison result of the phase comparator 38 is transferred to the voltage-current converter 39.
has been entered. This voltage-current converter 39 supplies the converted current to the adder 36. Here, a key signal is supplied to the voltage-current converter 39 from a terminal 41, and the voltage-current converter 39 is controlled to be in a conductive or non-conductive state by this key signal. The control information in the conductive state is held in the capacitor 40 in the non-conductive state.

The loop formed by the above-described phase comparator 33, voltage-current converter 35, adder 36, and voltage-controlled oscillator 37 is a phase-locked loop for ID demodulation, and the phase comparator 38, voltage-current converter 39, and adder 36, the loop of the voltage controlled oscillator 37 is a phase-locked loop for adjusting the reference demodulation axis.

FIG. 3 is a diagram shown to explain the operation of the above system.

Assume that the detection axis indicated by the solid line in FIG. 3(A) has been obtained before adjustment. I extracted from the chroma signal in Figure (B)
The demodulated ID signal obtained by demodulating the D signal ((C) in the same figure) is shown in the same figure ((C)).
D), and the foB detection output is almost gone.

Assume now that the reference signal fold as shown in FIG. 4A and FIG. A raw signal is also provided in synchronization with this reference signal fold. Then, the voltage-current converter 39 is activated by the key signal, the phase-locked loop for adjustment is activated, and the oscillation frequency of the voltage-controlled oscillator 37 is pulled into the same frequency as the reference signal f_old. At this time, the voltage-current converter 39
A detected output as shown in FIG.

In this way, once the modulation and demodulation axis is pulled in by the reference signal, the free-run frequency of the voltage controlled oscillator 37 will maintain this value thereafter, so that the demodulation axis will be moved as shown by the dashed line in FIG. This becomes an ideal demodulation axis centered on fold. When the ID signal is demodulated in this state (after the automatic adjustment is completed), it is possible to obtain a demodulated ID signal that is vertically symmetrical about the reference level as shown in (H) in the same figure, and accurate line discrimination can be obtained. . .

Next, a system for obtaining the reference signal fold from the color difference demodulation circuit 24 will be described.

FIG. 4 specifically shows the configuration of the color difference demodulation circuit 24. The chroma signal from the color difference amplifier 23 is input to the phase comparator 52 via the input terminal 51, and is input to the voltage controlled oscillator 56.
The phase is compared with the output of The comparison result is output to the output terminal 53 as a color difference signal demodulation output, and is also input to the voltage-current converter 54. The converted current obtained here is input to the adder 55. The adder 55 includes a current source 5
The output current of switch 61 is constantly supplied, and the output current of switch 61
．． 62 selectively supplies current from current sources 58,59. The output current of the adder 55 is supplied as a control current to the control terminal of the voltage controlled oscillator 56.

A loop formed by the phase comparator 52, voltage-current converter 54, adder 55, and voltage-controlled oscillator 56 forms a phase-locked loop, and demodulates the color difference FM signal (that is, the chroma signal).

The chroma signal has a different center frequency for each line (f
FM of oB -272fH, f oR-282fH)
Since it is a signal, if you try to make the black level of the demodulated color difference signal constant for each line, it is necessary to switch the demodulation axis.

Therefore, in this embodiment, this is realized by changing the direct current (DC) value of the control current supplied to the voltage controlled oscillator 56 for each line. That is, in a steady state, a current of 1oB from the current source 57 is supplied to the adder 55, and the voltage-current converter 54
During the ID signal period, the current from the current source 58 is further added to the output current of the (RY) signal period (f
During the oR off period, the output current from the current source 59 is further added.

FIG. 5 is a characteristic and waveform diagram shown to explain the operation of the color difference demodulation circuit 24 described above.

Now, when the current IoB is being supplied to the adder 55,
The oscillation frequency of the voltage controlled oscillator 56 is f oB ((B-Y
) carrier wave for signal demodulation). Then, the detection characteristic DB when the current IoB is supplied becomes as shown in the same figure (A), and (B-Y
) When the signal is demodulated, the demodulated output has a vertically symmetrical waveform with the black level V ref' as the center, as shown in FIG. Next, when the (RY) signal is input, both switches 61 and 62 are turned on. As a result, the detection characteristic DR becomes as shown in the figure (A), and as shown in the figure (C), the demodulated output becomes centered around the black level V ref. Each output current of current sources 58 and 59 is f
It is set to the amount of current that can shift the oB frequency by +5fH, and according to the total current, +1OfH.
You can get a shift of

This is exactly foR (-foB+10 fH), and the oscillation output at this time can be used as a carrier wave for demodulating the (RY) signal. The oscillation frequency at this time is 272f
'H+5f'H+5f'H-2g2fHte, and the center of the demodulation axis shifts to foR as shown in FIG.

The key signals for controlling the switches 61 and 62 have timings as shown in (D) and (E) in the same figure. In other words, both switches are on only during the (RY) signal period,
During the (B-Y) signal period, both switches are off, and during the ID signal period (blanking period), one switch, for example 61
only is turned on.

During this period, the oscillator 56 generates 272f'H+5fH-2
It will oscillate at 77fH (=fold). Therefore, when looking at the change in the oscillation frequency of the voltage controlled oscillator 56 over several horizontal periods, it becomes as shown in FIG. Therefore, the oscillation output during the ID signal period can be input from the color difference demodulation circuit 24 to the ID demodulation circuit 28 as the reference signal fold. With this configuration, the reference signal for adjusting the ID demodulation circuit 28 can be obtained without any problem in the demodulation operation of the color difference signal.

In the above embodiment, when automatically adjusting the free run frequency of the voltage controlled oscillator 37 in the ID demodulation circuit 28, the I
We focused on comparing the phases of the D signal and the reference signal fold. However, it is also possible to compare the demodulated output (voltage) when there is no signal and the demodulated output (voltage) when the reference signal fold is input, and control the free run frequency of the voltage controlled oscillator so that there is no error. .

FIG. 6 shows another embodiment of the ID demodulation circuit, with reference numeral 28.
' is added. An input ID signal is supplied to an input terminal 71, and a reference signal fold is supplied to an input terminal 72, which are selectively introduced into a phase comparator 74 by a switch 73. The phase comparator 74 compares the phases of the input signal from the switch 73 and the output signal from the voltage controlled oscillator 78, and outputs the phase comparison result to the output terminal 75 as a double ID signal.

An output terminal of the phase comparator 74 is connected to a voltage-current converter 76, a sample-and-hold circuit 79, and a comparator 81. The converted current of the voltage-current converter 76 is input to an adder 77 and added to the current from the voltage-current converter 83.

The output of the adder 77 is applied to the voltage controlled oscillator 7 as a control current.
The output of the voltage controlled oscillator 78 is supplied to the phase comparator 74.

The sample and hold circuit 79 samples the demodulated output using the key signal during the no-signal period supplied to the terminal 85, and
Hold on. Further, the comparator 84 outputs a reference signal fol
It operates in response to the key signal supplied to the terminal 84 when D is input, and compares the demodulated output (the demodulated output of the reference signal fold) with the voltage of the capacitor 80. The error output of comparator 81 is input to voltage-current converter 83. The output current of this voltage-current converter 83 is input to the adder 77 mentioned above.

A loop of the phase comparator 74, voltage-current converter 76, adder 77, and voltage-controlled oscillator 78 is a phase-locked loop for ID demodulation, and the phase comparator 74 and sample-hold circuit 7
A loop formed by 9, comparator 81, voltage-current converter 83, adder 77, and voltage-controlled oscillator 78 is an adjustment loop.

FIG. 7 is a characteristic and signal waveform diagram shown to explain the operation of the above circuit.

Now, the free run frequency of the voltage controlled oscillator 78 is shown in FIG.
Assume that the frequency deviates from the reference signal fold as shown in A). Then, the detection axis becomes as shown by a solid line, and when the ID signal extracted from the chroma signal (B) in the same figure (C) in the same figure is demodulated, f is shown in (E) in the same figure.
Almost no demodulated output of oB is obtained, and the subsequent line discrimination circuit is in a state where synchronous integration is not possible. The switch 73 selectively introduces the ID signal and the reference signal fold, and these signals exist in a time-division manner as shown in FIG. Furthermore, apart from this, in a sample and hold circuit 79 , the demodulated output during the no-signal period is sampled and held in a capacitor 80 . (G) in the same figure is a key signal supplied to the comparator 81, and (H,) in the same figure is a key signal supplied to the sample and hold circuit 79.

When the reference signal f olD is input here, the voltage controlled oscillator 78 is phase-locked to the reference signal f oJD.

At the same time, the comparator 81 compares the voltage held in the capacitor 80 with the demodulated output of the reference signal fold ((1) in the same figure), integrates the error voltage by the capacitor 82,
Prevents sudden changes in error voltage. However, due to the influence of the error voltage, the output current of the voltage-current converter 83 is changed.

As a result, when the reference signal f_old is input, the voltage controlled oscillator 78 is controlled to a frequency such that no error voltage occurs in the comparator 81. In other words, the level of the demodulated output when there is no signal and the level of the demodulated output when the reference signal is input are controlled to be the same.

As a result, the reference frequency of the voltage controlled oscillator 78 is adjusted, and the detection characteristics become as shown by the dashed line in FIG. Figure (J) shows the demodulated I obtained with this characteristic.
It shows the D signal.

In the above embodiment, the reference signal f old is introduced from the color difference demodulation circuit, but the present invention is not limited to this. Furthermore, there are various automatic and manual methods for adjusting the carrier wave frequency in the color difference demodulation circuit, and the method is not limited to the embodiments.

[Effects of the Invention] As explained above, the present invention can eliminate adjustment components in the ID demodulation circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the ID demodulation circuit of FIG. 1 in detail, and FIG. 3 is a diagram for explaining the operation of the circuit of FIGS. 1 and 2. 4 is a diagram showing the color difference demodulation circuit of FIG. 1 in detail. FIG. 5 is a characteristic and signal waveform diagram shown to explain the operation of the circuit of FIG. 4. 6 is a diagram showing another example of the ID demodulation circuit of FIG. 1, FIG. 7 is a characteristic and signal waveform diagram shown to explain the operation of the circuit of FIG. 6, and FIG. 8 is a diagram of a conventional color signal. FIG. 9 is a diagram showing the ID demodulation circuit of FIG. 8 in detail, and FIG. 10 is a characteristic and signal waveform diagram shown to explain the operation of the circuit of FIG. 9. 22... Bell filter, 23... Color difference amplifier, 24
... Color difference demodulation circuit, 25 ... Baseband processing circuit, 27 ... ID amplifier, 28 ... ID demodulation circuit, 2
9... Line discrimination circuit, 3o... Flip-flop circuit, 33.38.52.74... Phase comparator, 35
．． 39.54.76.83...Voltage-current converter, 36
．． 55.77... Adder, 37.56.78... Voltage controlled oscillator, 79... Sample hold circuit, 81
...Comparator.

Claims (5)

[Claims] (1) In a SECAM receiver, a means for generating a reference signal having a frequency intermediate between two ID signals, and a means for introducing the reference signal into an ID demodulation circuit using a phase-locked loop circuit to center the demodulation axis of this circuit. A SECAM type line identification circuit comprising: means for controlling a frequency to be the same as the reference signal frequency. (2) The ID demodulation circuit is composed of a first phase-locked loop circuit, and the initial oscillation of the first oscillator (
2. The SECAM type line identification circuit according to claim 1, further comprising means for controlling a free run frequency to be equal to said reference signal. (3) The color difference demodulation circuit has a second phase-locked loop circuit configuration, and the reference signal is supplied from a second oscillator controlled by a voltage or current in the loop of the color difference demodulation phase-locked loop circuit. S of claim 1, which is
ECAM method line identification circuit. (4) a third phase-locked loop circuit that also serves as a first oscillator in the loop of the first phase-locked loop circuit and configures a different loop from the first phase-locked loop circuit; 3. The SECAM type line identification circuit according to claim 2, further comprising means for drawing the free-run frequency of the first oscillator into the reference signal by a third phase-locked loop circuit when a signal is input. (5) means for sample-holding the demodulated output of the input to the loop of the first phase-locked loop circuit during the no-signal period, and the first phase-locked loop demodulating the sample-and-hold information and the reference signal. Claim 2, further comprising means for comparing the demodulated outputs at the time of the demodulation and mixing the comparison result into the loop control information of the first phase-locked loop circuit to make both the demodulated outputs equal. SECAM method line identification circuit.