JPH0321096Y2 - - Google Patents

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a single channel simple PCM transmitting and receiving device using a digital service channel in a digital wireless transmitting and receiving device.

Today, with the digitization of various communication lines,
Research on high-efficiency coding methods is progressing, and progress in single-channel PCMCODECLSI is particularly remarkable. In addition, the digital service channel of the digital wireless transmitter/receiver is the PCM terminal equipment.
This is a digital auxiliary channel that uses empty bits in the PCM multiplexed main signal.

(Prior art) Conventionally, the use of digital service channels in digital radio transmitter/receiver equipment has been based on the ΔM method.
This was done by CODEC. This ΔM method is
The advantages are that there is no need for frame synchronization and the circuit configuration is simple, but the transmission quality is
There is a problem that it is inferior to the PCM method, and in order to achieve the same transmission quality as the PCM method, the disadvantage is that the bit rate must be faster and the circuit must be more complex.

Currently, analog voice signal/digital signal conversion PCM terminal equipment is available to economically and effectively introduce digital transmission lines and digital exchanges.
Technologies such as digital multiplexing, frame synchronization, signaling transmission, and single channel
By using PCMCODECLSI, it was possible to achieve high-speed transmission and construct a high-quality telephone line.

However, transmission lines for sending and receiving remote monitoring and control data for digital wireless communication equipment and for maintenance meeting telephone calls require high-quality transmission lines, especially as data lines. Therefore, it cannot be said that using this telephone line as a high-quality line is a good idea in terms of effective use of the line. Furthermore, such a line configuration is not possible at relay and branch stations where PCM terminal equipment is not installed.

(Purpose of the invention) The purpose of the invention is to eliminate such drawbacks, simplify the circuit configuration, and create a digital circuit that can easily configure a high-quality circuit without using a telephone channel of a digital communication line. An object of the present invention is to provide a single-channel PCM transmitting/receiving device for a service channel.

(Structure of the invention) The single channel PCM transmitter/receiver of the invention is as follows:
A line driver/receiver circuit for connecting to a digital wireless transmitter/receiver device and the position of the data string input from this line driver/receiver circuit are detected, and if they are in an asynchronous state, the correct synchronization pattern is detected twice in a row. a frame synchronization circuit that outputs regular synchronization and is made into firmware using a ROM in its circuit configuration; a demultiplexer that separates audio data and signaling data from the data string; and a first frame synchronization circuit that temporarily stores the audio data. A storage unit, a level adjustment circuit that adjusts the input and output levels of audio signals from the terminal device, a PCM filter that limits the band of input and output signals of this level adjustment circuit, and a PCM filter that is connected to the PCM filter and adjusts its input and output signals. A PCM codec that performs modulation and demodulation and transmission from this PCM codec.
a second storage section that temporarily stores PCM data; a timing generation circuit that inputs data to the first and second storage sections and the PCM codec and sends out the data to create each timing from a predetermined clock; A multiplexer that adds frame synchronization bits/signaling bits to the audio data string from the output of the timing generation circuit and a synchronization bit pattern generation circuit, and conversion between the signaling signal and the contact signal between the demultiplexer/multiplexer and the input/output end. and a signaling input/output circuit.

(Example) Fig. 1 is a block diagram of an embodiment of the present invention.
The figure is a block diagram of a digital communication system using this embodiment, and FIG. 3 is a waveform diagram showing the signal relationship of FIG. 2. In this Figure 2, 1 is a digital radio transmitter/receiver, 2 is a PCM terminal equipment, 3 is a switching system, and 4 is a single channel simple device of the present invention.
The PCM transmitting/receiving device 5 is a telephone set. The interface with the digital service channel 5 of the digital radio transmitter/receiver 1 to which this single channel simple PCM transmitter/receiver 4 is connected is as follows:
A 64Kbit/s (15.625μs period) unipolar clock signal and a 64Kbit/s unipolar data pulse train synchronized with this.The signal relationship is as follows:
As shown in the figure.

Figure 1 shows a single channel simplified version of this embodiment.
In the block diagram of the PCM transmitter/receiver, 11 is a line driver/receiver circuit for connecting to the digital wireless transmitter/receiver 1, 12 is a frame synchronization circuit for detecting the position of a data string, and 13 separates voice data and signaling data. 14 is a temporary storage unit for audio data;
15 is a timing generation circuit for importing PCM data into PCMCODEC, 16 is PCMCODEC based on μ-law law, 17 is a PCM filter, 18 is an audio input/output level adjustment circuit, 19 is a temporary storage section for transmitting PCM data, 20 is PCMCODEC1
6 is a timing generation circuit for receiving PCM data, 21 is a multiplexer for adding frame synchronization bits and signaling bits to the audio data string, 22 is a synchronization bit pattern generation circuit, and 23 is a clock generator that is the basis of this system. 24 represents a signaling input/output circuit. In the figure, audio signal a from telephone 5
is input to the audio input/output level adjustment circuit 18, the level is set by this circuit 18,
It is passed to the PCM filter 17. This filter 1
7 limits the audio signal to 0.3 to 3.4KHz.
It is passed to PCMCODEC16 as voltage c. this
In PCMCODEC16, μ-law PCM encoding is performed and PCM data is transferred to the RX timing generation circuit 1.
5, the data is temporarily stored in the storage unit 19 by the timing signal.

Next, the audio data from the storage section 19 and the signaling input/output circuit 24 are sent to the multiplexer 21.
The SS signal and frame synchronization bits from the synchronization bit pattern generation circuit 22 are input and multiplexed at a bit rate of 64 Kbit/s to be passed to the digital radio transmitting/receiving device 1. The multiplexed signal is level-converted by the line driver 11 and sent out as a unipolar signal f.

In addition, in the decoding operation, the 64 Kbit/s PCM data string h from the digital radio transmitter/receiver 1 is input to the line receiver 11, where level conversion is performed, and then the data is sent to the frame synchronization circuit 12 and the demultiplexer 13. input. This frame synchronization circuit 12 detects the position of the PCM data string,
The detection display signal R is supplied to the demultiplexer 13 to start decoding processing. This demultiplexer 13 separates the audio data and the signaling signal SR, and the audio data l is sent to the memory 14.
It is temporarily stored in order to convert it into a bitrate to be passed to the PCMCODECLSI16. This signaling signal
SR is sent to the signaling input/output circuit 24,
This circuit outputs it to the outside as a contact signal.

The audio data m stored in the memory 14 is taken into the PCMCODEC 16 by a timing signal generated by the RX timing generation circuit 15. This circuit 16 performs PCM decoding, D
-A conversion operation is performed and the signal is sent to the PCM filter 17 by passing the voltage. Here, out-of-band signals generated during decoding are removed, and the signal is passed to the audio level adjustment circuit 18 as a 0.3 to 3.4 KHz audio signal, and after level setting, is output to the telephone 5 as an audio signal q.

Note that the clock generation circuit 23 is for creating the basic clock of the system, and includes the PCMCODEC 16,
Various clocks are supplied to the RX timing generation circuit 15 and the TX timing generation circuit 20.

In particular, the frame synchronization circuit 12 is essential for recognizing the time reference point in the received data pulse train and performing correct decoding processing. Specifically, the purpose is to match the frame phase of the reception timing counter with the frame phase of the reception data pulse train, and to determine an appropriate internal state transition based on the frame synchronization pattern in the reception data pulse train and the state signal indicating the operating phase of the timing counter. The purpose of this is to output a control signal that causes a forced transition of the operating state of the timing counter when necessary.

The data pulse train inputted from the line driver 11 is inputted to the S/P conversion circuit 31 inside the frame synchronization circuit 12, and the bits at the position of the synchronization pattern are serial-parallel converted and inputted to the ROM 32. At the same time, forward protection/backward protection, synchronization state determination information t, and a signal v indicating the operating phase of the timing counter 34 are inputted and written into the ROM 32 by delay feedback of a part of the output s of the ROM 32 from the latch 33. The program generates a new status signal s and timing counter 34.
A signal u is generated to forcefully transition the operating state of the device.

As a result, the timing counter 34 detects the correct received data position and sends the detection signal R to the demultiplexer 13 and the RX timing generation circuit 15.
supply to.

As a synchronization protection operation, when in an asynchronous state, normal synchronization is not established unless two correct synchronization patterns are detected in succession. Further, even if an erroneous synchronization pattern is detected from the synchronization state, the synchronization state will not be deviated from unless the synchronization pattern is received two or more times in a row within a Hamming distance of 2.

The frame structure of the data pulse train transmitted and received in this system is as shown in FIG.

As mentioned above, the frame structure is achieved by adopting firmware for the frame synchronization circuit and by adopting a fixed 7-bit decoding method for audio data.
The PCMCODEC circuit was simplified.

(Effect of the invention) As explained above, the present invention has a Hamming distance of 2
Since the synchronization state will not go out unless the synchronization pattern is received two or more times in a row within By using ROM in the synchronization circuit and converting it into firmware, the circuit configuration can be simplified, synchronization parameters can be changed easily by replacing the ROM, and the signaling data of contact signals can be transmitted using the same method as frame synchronization bits. This has the effect of enabling simple, high-quality signal transmission without using a telephone channel of a digital communication line.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention;
Figure 1 is a block diagram of a digital communication system using Figure 1. Figure 3 is a waveform diagram of the signals in Figure 2.
The figure is a frame configuration diagram of a data pulse train used in this embodiment. In the figure, 1...digital transmitter/receiver, 2
...PCM terminal equipment, 3...exchange system, 4...
...Single channel simple PCM transmitter/receiver, 11...
...Line driver/receiver circuit, 12...Frame synchronization circuit, 13...Demultiplexer, 14
...Audio data temporary storage unit, 15...
Timing generation circuit for importing PCM data into PCMCODEC, 16...PCMCODEC, 17
... PCM filter, 18 ... Audio input/output level adjustment circuit, 19 ... Transmission PCM data temporary storage section,
20...Timing generation circuit for receiving PCM data from PCMCODEC, 21...Multiplexer, 22...Synchronization bit pattern creation circuit,
23... Basic clock generation circuit, 24... Signaling input/output circuit.

Claims (1)

[Scope of utility model registration request] A line driver/receiver circuit for connecting to a digital wireless transmitter/receiver device and the position of the data string input from this line driver/receiver circuit are detected, and if they are in an asynchronous state, the correct synchronization pattern is detected twice in a row. a frame synchronization circuit that outputs regular synchronization and is made into firmware using a ROM in its circuit configuration; a demultiplexer that separates audio data and signaling data from the data string; and a first frame synchronization circuit that temporarily stores the audio data. A storage unit, a level adjustment circuit that adjusts the input and output levels of audio signals from the terminal device, a PCM filter that controls the band of input and output signals of this level adjustment circuit, and a PCM filter that is connected to the PCM filter and controls the input and output signals. PCM that modulates and demodulates
codec and transmission from this PCM codec
a second storage section that temporarily stores PCM data; a timing generation circuit that inputs data to the first and second storage sections and the PCM codec, sends out the data, and creates each timing from a predetermined clock; A multiplexer that adds frame synchronization bits/signaling bits to audio data from the output of the timing generation circuit, and a synchronization bit pattern generation circuit that converts the signaling signal and contact signal between the demultiplexer and multiplexer and the input/output terminal. A single channel PCM transmitter/receiver including a signaling input/output circuit.