JPH0321130A - Multiplex separation timing synchronizing system - Google Patents

Abstract

PURPOSE:To contract the size of a circuit without expanding frequency band width by converting a digital signal into a multiplexed high speed digital signal on a transmission side to send the signal and separating the multiplexed signal to be the original digital signal on a reception side. CONSTITUTION:Four bits of input data strings A, B are inputted to a multiplexing part on the transmission side as one block. When a timing shift is 0 bit, the data strings A, B are applied to corresponding error correcting coders 41, 42 and converted into error-corrected codes. The codes are inputted to corresponding shift registers(SRs) 511, 512 by using a timing signal inputted from a timing signal generator 522 and the order of signals is converted like A1, B1, A0, and B0 in an SR 521. The 4-bit data from the multiplexing part 52 are inputted to an SR 611 in a multiplex separation part on the reception side and data A0, A1 and data B0, B1 are respectively inputted to SRs 621, 622 by using a timing signal 612. Corresponding error correcting decoders 71, 72 execute normal decoding and extract the data strings A, B.

Description

[Detailed Description of the Invention] [Summary] Regarding a demultiplexing timing synchronization method used in a multiplex communication system, the purpose of this invention is to reduce the circuit scale without increasing the required frequency bandwidth. The multiple data streams are subjected to error correction coding by the corresponding error correction encoder, and then multiplexed using the multiplexing timing signal in the multiplexer and sent out to the transmission path. In a multiplex communication system in which a multiplexed signal received at a transmitting side is separated using a demultiplexing timing signal and then decoded by a corresponding error correction decoder to extract multiple sequences of data, the transmitting side uses a demultiplexing timing signal. When the timing signal and the multiplexing timing signal are out of synchronization, an order conversion means is provided to convert the order of the input multiple data strings so that the arrangement of the demultiplexed data is incorrect, and the receiving side can An order inversion converter that performs a conversion operation inverse to the arrangement order conversion operation of the order conversion means and an operation state monitoring section are provided, and the operation state monitoring section monitors the decoding state of the error correction decoder and performs the decoding operation. The timing control signal is configured to send out a timing control signal corresponding to the state and control the timing position so that the demultiplexing timing signal is synchronized with the multiplexing timing signal.

[Industrial application field]

The present invention relates to a demultiplexing timing synchronization method used in a multiplex communication system.

In digital transmission systems, the transmitting side temporally multiplexes multiple series of digital signals, converts them into high-speed digital signals, and sends them out, and the receiving side conversely separates the multiplexed signals and converts them into the original digital signals. I'm getting a signal.

At this time, as a multiplex communication system, it is necessary to reduce the circuit scale without increasing the required frequency bandwidth.

[Prior Art] FIG. 6 is a conceptual diagram of a multiplex communication system, and FIG. 7 is an explanatory diagram of the operation of FIG. 6. below. The operation of FIG. 6 will be explained with reference to FIG. 7.

First, in the multiplexing section on the transmitting side, the input two series of data (A, B) as shown in Figure 7 - ■ and ■ are transferred to the corresponding flip-flops by the multiplex timing ≧ timing signal generated internally. The data string A. The data strings are stored alternately in the order of B and sent out to the communication channel as multiplexed data as shown in FIG.

On the other hand, the demultiplexer on the receiving side uses a demultiplexing timing signal that is synchronized with the multiplexing timing on the transmitting side.
After storing the received multiplexed data in the shift 1 register 14, it is taken out alternately through the FF 15 or 14, and is divided into two series of data string A9 and data string B as shown in Fig. 7-1■ and ■. data.

Here, if the multiplexing timing signal and the demultiplexing timing signal are misaligned by bits as shown by the dotted lines in Figure 7-■ and ■, data string A and data string B as shown in Figure 7-■ and ■. Exchange occurs between the two, and normal communication becomes impossible.

Therefore, in order to synchronize the multiplex timing signal and the multiplex demultiplex timing signal, an appropriate synchronization word is added to the data string. That is, a unique word is inserted.

Figure 8 is a block diagram of the conventional example. Figure 8(a) shows a case where a synchronization word is inserted into data after multiplexing. FIG. 8(b) shows a case where a synchronization word is inserted into data before multiplexing. below,
The operation of the diagram will be explained.

First, in FIG. 8(a), on the transmitting side, the input data strings A and B are multiplexed in the multiplexer 21, and then speed converted using the timing signal from the tying generator 23. In section 22, the multiplexed data is sped up and applied to the OR gate.

Also, the synchronization word generation section 24 generates the synchronization word. The synchronization word that has the same speed as the speed-converted multiplexed data is also OR gate 2.
5, a timing signal is sent from the timing generator 23 to the sync word generator so that the sync word is inserted into the multiplexed data at the output side of the OR gate. Therefore,
The multiplexed data into which the synchronization word has been inserted is sent to the communication channel.

Next, on the receiving side, the received signal is applied to a synchronization word detection section 26 and a speed conversion section 28, the former of which synchronizes with the synchronization word tying generation section.

Mata. The latter returns the received signal to its original speed using the timing signal from the timing generation section 27 and adds it to the demultiplexer 29, where the synchronization word is removed and the original data string is restored. A and data string B are returned and sent to the outside.

In Figure 8(b). On the sending side, the input data string A
, B are speed converters 31. After speed conversion at 31°,
Added to OR game 1-32.32'.

Also, the synchronization word from the synchronization word generation section 34' is also OR game 1~
32. 32", but the same 1 is added to data strings A and B.
The synchronization word sending timing is controlled by the timing signal from the timing generator 23 so that one word is inserted. As a result, the multiplexed data into which the synchronization word has been inserted by the multiplexer 34 is sent to the communication channel.

On the receiving side, the process opposite to that on the sending side is performed. That is, after the received signal is separated into data strings into which two columns of synchronization words are inserted in the demultiplexing section 35, the synchronization word is detected from each separated data string in the synchronization edict detection section 37.

Also. The separated data string is sent to the speed converter 36. 36"
The synchronization words are removed and the data strings A and B are restored to their original speed.
is taken out. The timing generating section 38 is synchronized with the transmitting side using the output from the synchronization word detecting section, and supplies a timing signal that allows each section to operate correctly.

[Problems to be Solved by the Invention] Conventionally, speed conversion is performed to insert a synchronization word, so the data transmission speed increases and the required frequency bandwidth increases, and the synchronization word insertion part. Since a speed conversion section, a synchronization detection section, a timing generation section, etc. are required, there is a problem that the circuit scale increases.

An object of the present invention is to reduce the circuit scale without increasing the required frequency bandwidth.

[Means to solve problems]

Figure 1 shows a diagram of the principle of tree invention.

In the figure, 51 is an order conversion that changes the arrangement order of multiple input data strings so that the arrangement of demultiplexed data is incorrect when the demultiplexing timing signal and the multiplexing timing signal are out of synchronization. In the means, 62 is an order inversion converter that performs a conversion operation opposite to the arrangement order conversion operation of the order conversion means, and 8 is an operation status monitoring section.

and. The operating state monitoring unit monitors the decoding state of the error correction decoder, sends a timing control signal corresponding to the decoding state, and adjusts the timing so that the demultiplexing timing signal is synchronized with the multiplexing timing signal. Control position.

[Effect]

The present invention eliminates the need to insert a synchronization word by synchronizing the demultiplexing timing signal and the multiplexing timing signal using an error correction device.

Normally, error correction is often used in digital communication systems to ensure data quality, but if the order of the data input to the error correction decoder is changed, a very large error will occur and the system will not function properly. However, whether or not the decoder is in such a state can be easily determined by monitoring the operating state.

For example, in the case of convolutional encoding/Viterbi decoding, by focusing on the rate of increase in the path metric of the Viterbi decoder. If it is determined that decoding is not normal, decoding can be performed normally by shifting the timing position of the demultiplexing timing signal to obtain synchronization.

That is, since no synchronization word is inserted, it is possible to reduce the circuit scale and diagram without increasing the required frequency bandwidth.

〔Example〕

FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is an explanatory diagram of the demultiplexing operation of FIG. 2, FIG. 4 is a block diagram of an example of the operating state monitoring section in FIG. 2, and FIG. The operation explanatory diagram of FIG. 4 is shown.

In addition, in Fig. 3 (a), the timing is 0 bit, and Fig. 3 (
b) shows the Quieing ≥ 1 bit deviation, Fig. 3(c) shows the timing deviation of 2 bits, Fig. 3(d) shows the timing deviation of 3 bits/7 bits, and Fig. 3(e) shows the decoder operation for the timing deviation. It is an explanatory diagram of a state.

Here, the shift 1 register 51L 512 is a predetermined part of the 1,000-stage order conversion 51, the soft register 521, the timing signal generator 522 is a part on the side of the multiplexer 52, the counters 81, 82, the comparators 83, 84. The determiner 85 and the timing signal generator 86 are components of the operating state monitoring section 8.
9 10 The shift register 611 and the timing signal generator 612 are part of the demultiplexer 61, and the shift registers 621 and 6
Reference numeral 22 indicates a horizontal part of the 1,000-stage order inversion transform 62.

Hereinafter, assuming that there are two data streams A and B input to the multiplexing section, the demultiplexing operation of FIG. 2 will be explained using FIG. 3, and the operation of FIG. 4 will be explained using FIG. 5. Note that the symbols on the left side of FIG. 3 indicate the data strings in the portions with the same symbols in FIG.

First, as shown in FIG. 2, 4 bits of input data strings A and B to the multiplexer 52 on the transmitting side are set as one block, and the order of the data is changed within the block and multiplexed. On the receiving side, data strings A and B are obtained by performing the reverse switching and demultiplexing as on the transmitting side.

(1) When timing deviation is 0 bits Figure 3 (a
) The data strings A and B shown in 10 and , SR)5
After inputting the signals to 11 and 512, the order is further changed so that the 4-bit SR 521 has the sequence AIt B++ Ao+ B0 (see FIG. 3(a)-■).

The 4-bit data sent from the multiplexing unit 52 is sequentially input to the 4-bit l-SR 611 in the demultiplexing unit on the receiving side, and then the timing signal generated by the timing signal generator 612 (multiplexing timing signal and , S
A to R 621. , A,, SR 622 to 80B,
Enter.

Therefore, a corresponding error correction decoder (hereinafter referred to as DEC-A)
(abbreviated as DEC-B)71. Normal decoding is performed in step 72, and data strings A and B are extracted (see 1-2 and 2-2 in FIG. 3(a)).

(2) In the case of timing signal slip 1 bit 1- Figure 3 (
As shown in Fig. 3(b), the data of data string B in the correct order is input to the DEC-A 71, but the data string A in the reversed order is input to the DEC-8 72 (Fig. 3(b)).
(See 1■,■,■). For this reason, DEC-A decodes normally, but +. Since the order of DEC-B has been changed, normal decoding cannot be performed.

11 l2 (3) In the case of timing deviation 2 bits 1. Figure 3 (C)
As shown in (1) and (2), data strings with the order changed are input to both DEC-A and DEC-H, so normal decoding cannot be performed on both.

(4) Timing deviation of 3 bits As shown in Fig. 3(d) 1 and 2, the DEC-A receives data string A whose order has been changed, and Dll! Since data strings B in the correct order are input to C-H, DEC-A cannot be decoded normally, but DI! C-B can be decoded normally.

That is, when the results of FIGS. 3(a) to 3(d) are summarized, as shown in FIG. 3(e), DEC-A, DEC-B, or DEC
- Since A and DEC-B cannot be decoded, by monitoring the status of the error correction decoder, it is not only possible to determine whether or not the demultiplexing timing is synchronized, but also to determine how many bits the timing is off. Therefore, you can immediately and correctly synchronize.

Next, an example of a method for monitoring the state of an error correction decoder (for example, a Viterbi decoder) will be described using FIGS. 4 and 5.

First, the Viterbi decoding method uses only one of all code sequences that may be rejected by the convolutional encoder. The code sequence closest to the code sequence actually examined is selected, the distance between the selected transmitted code sequence and the received code sequence is calculated, and is stored in memory as a path metric. and. When the code of the next symbol is received, one distance per symbol is calculated, added to the stored bus metric, and this is repeated.

here. When an error is added to the received code sequence, as shown in FIG. 5(a), the path metric also increases in response to the increase in error rate, causing an adder (not shown), ie, a counter, to overflow. Therefore, in order to prevent this, a threshold value is provided, and when this threshold value is exceeded, the above-mentioned counter is forcibly set to 0 and the count is added again.

At this time, a reset pulse is outputted from the Viterbi decoder to the outside as shown in FIG. 5(b), and the frequency of occurrence of this reset pulse corresponds to the error rate.

Therefore, the counter 8182 in the operating state monitoring unit 8
The number of cent pulses per hour is counted by the counter 83, and the count value is sent to the corresponding comparator 83. 84 as well as a threshold value v1.

Here, Yu + I'S. If the timing signal shifts, the error rate of the data output from the Hitabi decoder will be higher than the line error rate. By determining the increase rate, it is possible to set a threshold value V for determining whether an error is due to line deterioration or a timing signal shift.

Now, comparator El3. Based on the comparison result of 84, a judger 85
For example, with reference to FIG. 3(e), it is determined by how many bits the tying signal of the decoder should be shifted, and the timing signal is sent to the tying signal generator 612 in the demultiplexer 61 as a timing control signal. .

Therefore, the timing signal generator 612 sends out a correct timing signal for demultiplexing and synchronizes the timing signals, so that correct decoded data is sent out from the DEC-ADEC-B.

As a result, the frequency bandwidth can be increased without increasing the required frequency bandwidth.
- It is possible to reduce the circuit scale.

〔Effect of the invention〕

As described in detail above, the present invention has the advantage that it is possible to reduce the circuit scale without increasing the required frequency bandwidth.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is an explanatory diagram of the demultiplexing operation of Fig. 2, and Fig. 4 is an operational state monitoring diagram in Fig. 2. 5 is an explanatory diagram of the operation of FIG. 4, FIG. 6 is a conceptual diagram of the multiplex communication system, FIG. 7 is an explanatory diagram of the operation of FIG. 6, and FIG. 8 is a diagram of the conventional example. A block diagram is shown. In the figure, reference numerals 15, 16, and 8 refer to an operating state monitoring unit, 41 an error correction encoder, 51 an order converter, 52 a multiplexer, 61 a demultiplexer, 62 an order inverter, and 71 an error correction decoder. Show the container. 17 ○O O ■O ■ ■O ■ ■O ■ ■ < ■ P Koto1to1to○ O ■ ■ O

Claims (1)

[Claims] On the transmitting side, after error correction encoding is performed on a plurality of input data strings in a corresponding error correction encoder (41),
A multiplexer (52) uses a multiplexing timing signal to multiplex the signal and sends it to the transmission path, and on the receiving side, a demultiplexer (61) demultiplexes the received multiplexed signal using a multiplexing timing signal. In a multiplex communication system in which data is then decoded by a corresponding error correction decoder (71) and multiple sequences of data are extracted, the transmitting side is informed that the demultiplexing timing signal and the multiplexing timing signal are out of synchronization. When the demultiplexed data is arranged incorrectly, an order converting means (51) is provided for converting the order of the input multiple data strings so that the arrangement of the demultiplexed data is incorrect. an order inversion converter (62) for performing a conversion operation, and an operating state monitoring unit (8), the operating state monitoring unit monitors the decoding state of the error correction decoder, and determines the timing corresponding to the decoding state. A demultiplexing timing synchronization method characterized in that a timing position is controlled by sending a control signal so that the demultiplexing timing signal is synchronized with the multiplexing timing signal.