JPH03211479A - Testability circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention is directed to a large-scale logic circuit for easily testing large-scale logic circuits such as VLSI and boards on which large-scale logic circuit components are mounted. This invention relates to testability circuits.

(Prior art) Conventionally, in functional tests of large-scale logic circuits and boards on which large-scale logic circuit components are mounted, a human cover turn is applied to the entire circuit from an external input bin, and the output is observed from the output bin. , it is determined whether the product is good or not by comparing it with the expected value.

In addition to testing the boards on which components are mounted, in-circuit tests were performed in which a test turbine was brought into contact with the signal line on the board, input was applied to each component, and the output was observed.

To explain this in more detail, when testing a board on which large-scale logic circuit components are mounted, an input pattern sequence is applied from the external input terminal of the board, and its output is observed from the external output terminal of the board. It was determined whether a product is good or defective by comparing the output value and the expected value. Although this method can easily determine whether a product is good or defective, there is a problem in that it is not easy to perform a failure analysis to identify where a defective part is located on the board. Furthermore, for a board on which large-scale logic circuit components such as VLSI are mounted, it is extremely difficult to create a test input cover pattern series with a high failure detection rate.

On the other hand, as a test method for a board, a probe bin is brought into contact with the signal line on the board, and a test person covers the parts mounted on the board, and the output is observed and the test is carried out. There is an "in-circuit test" method. When using this method, the probe bin of the tester comes into contact with the input/output signals of the components mounted on the board, so the test input pattern series can be applied and the output can be observed on a component by component basis. Tests and failure analysis can be easily performed compared to However, in recent years, as high-density packaging has progressed, it has become difficult to bring the probe bin into contact with the board due to the narrower bin pitch of components and surface mounting.

[Problem to be solved by the invention]

Conventional board testing uses the methods described above, making it difficult to create a test person cover turn series and difficult to perform failure analysis to identify defective locations. There were problems such as making it more difficult to conduct board tests.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a testability circuit that allows easy testing of large-scale logic circuits.

[Means to solve the problem]

The testability circuit according to the present invention, when testing a board on which a large-scale logic circuit is mounted, divides a shift register in the large-scale logic circuit into a master circuit and a slave circuit, and each divided circuit It is designed to perform a circuit test on the interface between the two.

[Effect]

The testability circuit of the present invention divides a shift register of a large-scale logic circuit into a master circuit and a slave circuit, divides the entire logic circuit into testable circuit scales, and creates an interface circuit between each divided circuit. Facilitate testing by conducting tests.

(Example〕 An embodiment of the present invention will be described below with reference to the drawings.

Figure 1 shows an example of the configuration of a shift register, in which a shift register operated by a two-phase clock is divided into a master circuit and a slave circuit. (1) is the master circuit, (2)
) is a slave circuit. (12) shows the clock of the master circuit, (13) shows the clock of the slave circuit, and (1
1) is the control input, which allows you to select shift input (9) or data input (10). Note that (3) is an AND gate, (4) is an OR gate, and (5) is an OR gate. ^ND gate, (6) is inverter, (
7) and (8) are flip-flops or latch circuits.

Figure 2 shows an example configured using this shift register.The LSI mounted on the board is divided into LSTI and LSI2, and LSII is equipped with shift register master circuits (l^) and (IB). be done. (181, (1
7) is a human output buffer, and this human output buffer is connected to the master circuit (IA) by the input/output control (14).
, (1B+ output value is selected, or the LSII human output values SIa and Slb are selected.

In addition, LSI2 has a shift register slave circuit (
2) is installed, and (18) and (19) are configured to control the output value of the slave circuit (2) or select the value of the input/output 52a and S2b of the LSI by the input/output control (15). .

Using the test facilitation circuit configured as described above, the second
When testing the circuit part of the interface signal between LSII and L5I2 in the figure, set the shift input value to shift manual (9), and shift it to the master circuit (1^) using control (11) and clock (12). The human power value is set. Next, the human output control (14) controls the human output buffer (16) to output the output value of the master circuit (IA). Next, the human output buffer (1
8) to select the value of the LSI input/output bin 52a, and by applying the clock (13), the shift input value is set in the slave circuit (2). Next, the slave circuit (
2) Select the value set in the section and output it to the input/output bin 52a of the LSI2.

Next, the LSII human output control (14) controls the human output buffer (16), and the control (11) and clock (12) control the master circuit (IB).
Import the shift input value into the part. By repeating this, it is possible to shift out the shift human power value up to the shift output (20) of LSI2. Further, if there is no LSII, the slave circuit (2) portion of LSI2 can be used as a normal register.

(Effects of the Invention) As explained above, the present invention has the effect that testing can be easily performed by dividing the interface circuit portion between large-scale logic circuits such as LSIs mounted on a board. It is not necessary to contact the test probe on the signal line on the board as in the past, and it is possible to support high-density packaging.

[Brief explanation of drawings]

Figure 1 is a configuration diagram of a shift register operated by a two-phase clock.
FIG. 2 is a block diagram illustrating a method of testing an LSI mounted on a board and its interface circuit according to an embodiment of the present invention. (1), (1^), (1B): Master circuit (2
) Nislepe circuit Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] When testing boards equipped with large-scale logic circuits,
A test facilitation circuit characterized in that the shift register in the large-scale logic circuit is divided into a master circuit and a slave circuit, and a circuit test is performed on an interface portion between each divided circuit.