JPH0321149A - Pulse generation circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pulse generation technology and a technology that is effective when applied to a clock frequency switching system, such as a CODEC.
(encoding circuit/decoding circuit) and its peripheral functions in a digital telephone circuit control LSI
The present invention relates to a technique effective for use in ringing (hereinafter referred to as ringing).

[Conventional technology] With the digitization of telephone lines, CO
Along with DEC, various functional circuits such as a linking circuit and a volume adjustment circuit are provided. In this case, it is convenient to have an LSI in which these functional circuits and the CODEC are integrated into one semiconductor chip, in order to miniaturize the telephone circuit.

The ringing circuit built into such a multifunctional CODEC is often required to have a ring tone selection function by generating a plurality of types of tones and switching tones.

Regarding CODEC, there is a description in "Ultra LSI Device Handbook" published by Science Forum Co., Ltd., January 28, 1982, pages 483 to 488.

[Problems to be Solved by the Invention] The present inventor has studied a ringing circuit that repeatedly generates 21-- or 31-. As a result, if the tone is switched without considering the tone generation state, there is a problem in that noise is generated when the tone is switched, resulting in a harsh ringing tone, as shown in Figure 3 (A). I discovered that.

The present invention has been made in view of the above-mentioned problems, and its object is to provide a ringing circuit that does not generate noise when switching from one to the other.

The above-mentioned and other objects and novel features of the present invention will become clear from the description and accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, a comparison circuit compares the value of the counter that counts the clock with the tone designation code set in the register, and when they match, the counter is reset to determine the frequency of the generated pulse. In a ringing circuit that switches the frequency by switching the supplied tone designation code, a latch circuit is provided between the register and the comparison circuit to detect the completion of the cycle of the pulse being generated. At this point, the latch circuit latches the next tone designation code.

[Function] 3 According to the above-described means, even if a 1--on switching signal is input, the next 1--on designation code is not immediately supplied to the comparator circuit, but is supplied only when the cycle of the currently generated pulse is completed. This prevents noise from occurring when switching between 1 and 2.

[Embodiment] The first drawing shows an embodiment of the ringing circuit according to the present invention.

In the first drawing, l is supplied from outside the chip 128
A counter that counts a clock φC such as KHz, and a tone register 2 for setting a tone designation code supplied from a microcomputer etc. outside the chip. The game consists of 4 bits, 1-, and is divided into 3 times into set 1.

Also, 3 is a mode register that holds a mode designation code supplied from a microcomputer, etc., and the mode designation code taken into this mode register 3 controls the shift 1 and control circuit 4 to control the 3-bit shift register 5. Decide how to operate, 4-? Mono 1--tone mode in which only one tone is generated continuously, 2-tone mode in which two 1--tones are repeatedly generated,
The shift register 5 is operated in a mode corresponding to the mode designation code in the mode register 3, such as a 3-tone mode in which three tones are repeated.

The tone register 2 has a game 1 corresponding to each bit.
A selector SEL consisting of ~ao-a, 1 is connected, and the gate G is controlled by signals from each stage of the 3-bit shift register 5. -G1■ are configured to be controlled to open and close four at a time at the same time. Furthermore, Gate G. -G
, there are four D-type flip-flops FFo=F in the rear stage.
A latch circuit 6 consisting of F3 is connected, and the gate G
. - Bit R in tone register 2 by G2 3.
、． Any one bit signal among R2, , R1o can be supplied to the flip-flop FFo, and the bits R,1, R21, R1■ are output by gates 03 to G5.
One of the bit signals is sent to the flip-flop F.
The bit signal of any one of bits R3■, R2■, R1■ is made available to be supplied to F, and gates 06 to Gll output the bit signal of any one of bits R3■, R2■, and R1■. It can be supplied to the flip-flop FF, and also to the games G9 to G1. By Bit-R,,,
A bit I signal of any one of R, , J, and R3 can be supplied to flip-flop FF3.

When the mono mode is specified by the mode 1 specification code I in motor register 3, shift I to register 5
does not perform a shift operation, and is controlled so that, for example, the outputs of the lowest H1~ continuously maintain a high level. As a result, game 1 to G 2 1 (] S +G,,
Only G and ■ are opened, and the bit- RIOI R41 1 R+ of the code 1< held in the tone register 2
．． 21R. The four signals of 3 are evenly supplied to the latch circuit 6,
Latched.

Reference numeral 7 denotes a coincidence detection circuit that compares the code 1- latched by the latch circuit 6 with the count value of the counter 1.
■l E21 E3T Consists of E4 and a four-manpower AND gate Ga that uses these outputs as human power signals. The coincidence detection signal INV. output from this detection circuit. is supplied to a flip-flop FFa consisting of. The output signal of the flip-flop FFa is supplied to the reset terminals of the four first-order flip-flops of the above-mentioned counter to reset them, and the output signal Q of the flip-flop FFa is
The signal a is supplied to the frequency dividing circuit 8 and is divided into, for example, 1/16. As a result, a pulse P train having a frequency corresponding to the codes 1 to 1 latched by the latch circuit 6 is formed and outputted from the frequency dividing circuit 8. The output pulse train P of the frequency dividing circuit 8 is
For example, it is supplied to a sine wave generation circuit consisting of a resistor ladder and a switch row, and a staircase waveform pseudo sine wave is generated.
Supplied to the speaker. However, the output pulse train P of the frequency dividing circuit 8 may be outputted to the outside from an external terminal, and the speaker may be directly driven by this pulse train.

In this embodiment, the output signals of each stage of the frequency dividing circuit 8 and the output of the flip-flop FFa are connected to an inverter INV,
The output signal of 7, which uses the inverted signal as the input signal, is supplied to the latch circuit 6 with -1 as the launch timing signal -φL.

Further, in this embodiment, an AND gate 10 is provided which receives as an input signal the output signals of the respective flip-flops FFo to FF constituting the latch circuit 6, although not particularly limited thereto. Depending on the signal, the flip-flops of each stage constituting the frequency dividing circuit 8 are
It is now possible to do so. As a result, the frequency divider circuit 8 is reset.
is reset, and when all "O"s are latched in the latch circuit 6.

Next, the operation of the ringing circuit of the above embodiment will be explained using timing charts 1 to 1 in FIG. 2.

The 8-bit signal supplied from an external microcomputer has the 7th-order 4 bits as a command section and the lower 4 bits as a data section. By decoding the upper 4 bits with a decoder (not shown), the lower 4 bits 1-- The register that latches the data is specified.

8? When operating the switching circuit in the 31-on mode, the microcomputer supplies the tone designation code for l2 bits 1 to 4 bits three times, and sets the corresponding bits in tone register 2. be done. Separately, a 4-bit mode designation code is set in the mode I register 3 in a similar manner.

As a result, the shift control circuit 4 shifts the shift register 5 according to the clock CK supplied with 0 from the outside, and first shifts the gates 1' G 2 , G s , G 8 ,
Open G■1, then play games 1 to G,,G. ,,G7,G,
. , and then Gae G. , G,, GIi,
Open the G9 and repeat this until the mode is converted by the microcomputer. Game 1~G2, G5
, G8, and G11 are open, and when a reset signal '; The circuit 8 is reset. Then, do you believe the latch timing that is the output of AAND game 1-9? φ14 is high? When reset 1 is released, φL changes to high level in synchronization with the fall of clock φC, and bit R■ of register l. , R11, R1■, and R■3 are taken into the latch circuit 6. At the same time, the counter 1 starts counting the clock φC, and when the data matches the data held in the launch circuit 6, the output of the match detection circuit 7 changes to high level.

FIG. 2 shows the timing when (1 0 1 0) is captured in the latch circuit 6.

When the output of the coincidence detection circuit 7 changes to a high level, the output Qa of the flip-flop FFa changes to a high level and the counter 1 is reset. Then, since the value of the counter 1 changes, the output of the coincidence detection circuit 7 quickly changes to low level. On the other hand, the output Q of flip-flop FFa
a is supplied to the frequency dividing circuit 8 as a clock. Therefore, a coincidence detection signal is output every time it takes for the counter 1 to count the value taken into the latch circuit 6.
The frequency dividing circuit 8 outputs a pulse train P that changes at a period 16 times that of the pulse train P. Based on this pulse train P? When the speaker is moved, an I--on having a frequency f1 corresponding to the code in the latch circuit 6 is generated.

When a clock CK which is asynchronous with the clock φC and has a much longer period comes in while this 1 hone is occurring, the shift 1-register 5 operates as shift 1, and the shift 1 to Go-0
In order to switch the R x o in the tone register 2,
+ R 1 , + R 1 2 1 R ■ R2. in place of a. , R2■, R2■, and R23 are supplied to the latch circuit 6. Therefore, in the ringing circuit of this embodiment, even if the gates GIl-Ge are switched, the tone designation code is not immediately taken into the latch circuit 6, but the frequency dividing circuit 8, which uses the coincidence detection signal as the clock, When all the outputs of each stage have changed to the output level,
That is, as shown in FIG. 3(B), when the cycle of the generated tone (frequency f) is completed, the latch timing signal φL is formed and the next 4 bits in register 2 are input. The code is taken into the latch circuit 6. As a result, La 11? A pulse train of f2 is output.

In the 3-tone mode, when the clock CK is input again, the switching is performed from 1 to G, -G, and when the cycle of the tone being generated (frequency t'z) is completed, the next code is started. is taken into the latch circuit 6, and a pulse train of frequency fJ corresponding to the code is output. after that,
Gate G again in synchronization with clock CK. -6■1 is switched and the tone changes from f1 → f2 → f3 → f1 → f2 →...
Repeat changes like...

On the other hand, in the 2-tone mode, shift 1 to register 5 are controlled to repeat shift 1 to only between the first stage and second stage, so only two types of tone designation codes are loaded into the latch circuit 6. f1→f2→f■→f2→・・・
Repeat the tone.

In mono 1 hane mode, as mentioned above, one type of 1・-
Since only the ON designation code is supplied to the latch circuit 6, the same 1 to -ON continues to be generated. The generation of 1-- continues until the next command is issued from the microcomputer.

In the embodiment described above, the latch timing signal φL of the latch circuit 6 is generated by an AND gate 9 whose input signals are the output of the flip-flop FFa that receives the coincidence detection signal and the output of each stage of the frequency divider circuit 8. However, a ringing circuit in which the coincidence detection signal itself is used as the latch timing signal of the latch circuit 6 is also conceivable. However, in order to realize the same 1 to - generation function as in this embodiment with such a circuit type, a coincidence detection circuit that compares the outputs of each stage of the frequency divider circuit 8 in addition to the counter 1 is required. The disadvantage is that the circuit scale becomes large.

As explained above, in the above embodiment, the value of the counter that counts the clock and the tone designation code set in the register are compared in the comparison circuit, and the counter is reset when they match, thereby generating a pulse. In the ringing circuit, which determines the frequency and switches the frequency by switching the tone specifying code supplied to the comparison circuit, a latch circuit is provided between the register and the comparison circuit to detect the frequency being generated. Pulse Ii'i
As soon as the completion γ of the l period is detected, the next 1-Hen designation code is launched in the upper edict latch circuit, so even if the tone switching signal is input, the next 1Hen designation code is immediately supplied to the comparator circuit. First, since the signal is supplied when the period of the pulse currently being generated is completed, it is effective to prevent noise from occurring when switching tones.

Hereinafter, the invention made by the present inventor has been specifically explained based on Examples, but the present invention is not limited to the above Examples, and various modifications can be made without departing from the spirit thereof. Needless to say. For example, in the above embodiment, the selector S consisting of the game hG o - G tr
A latch circuit 6 is provided between E L and the coincidence detection circuit 7, and when the period of the pulse being generated is completed, the next I~-in designation code is latched to the launch circuit 6 and sent to the coincidence detection circuit 7. However, instead of providing the Lanochi circuit 6, the output φL of the AND gates 1-9 is supplied to the shift 1/control circuit 4AO (supplied to the shift 1/control circuit 4AO), and the cycle is completed based on the clock CK and φ■. The shift 1 resistor 5 may be set to shift 1 to switch between Go 1 and Go-0.

In the following explanation, the invention made by the present inventor will be mainly explained in terms of the multifunctional CODEC, which is the field of application in which the invention was made.
Although the present invention has been described in the case where it is applied to a linking circuit built in, the present invention is not limited thereto, and can be applied to an LSI for a clock that generates an alarm sound, or other cases where it is desired to continuously generate pulse trains of different frequencies. I can do it.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, the comparison circuit compares the value of the counter that counts the evening lock with the tone designation code set in the register, and when they match, the counter is reset to determine the frequency of the generated pulse. In a ringing circuit configured to switch frequencies by switching the tone specifying code supplied to the comparator circuit, it is possible to prevent the generation of noise when switching tones.

[Brief explanation of the drawings] Fig. 1 is a circuit diagram showing an example of an actual journey when the present invention is applied to a ringing circuit, Fig. 2 is a timing chart 1 to 1 of the circuit, and Fig. 3 is a circuit diagram showing an example of the circuit when the present invention is applied to a ringing circuit. 2 is a timing chart showing waveforms at the time of tone switching in the conventional ringing circuit and waveforms at the time of 1-tone switching in the ringing circuit according to the present invention. 1...Counting means (counter), 2...1~-n register, 3...Mode register, 5...Shift 1~register, 6...Latch circuit, 7... ... Comparison circuit (coincidence detection circuit), 8... Frequency division circuit, 9...
Logical product circuit (AND gate). -16 JP-A-3 21149 (6) JP-A-3 21149 (7)

Claims (1)

[Claims] 1. Counting means for counting clocks to determine the cycle of generated pulses, a register holding a plurality of frequency designation codes, and the value of the counting means and the selected frequency designation code. and a selector that selects one of the plurality of frequency designation codes held in the register and supplies it to the comparison circuit, and the comparison circuit selects one of the plurality of frequency designation codes held in the register and supplies it to the comparison circuit. 1. A pulse generation circuit configured to supply a frequency designation code to a pulse generator. 2. A latch circuit is provided between the selector and the comparison circuit, and the frequency designation code selected by the selector is configured to be captured into the latch circuit at the completion of the cycle of the pulse being generated. Claim 1
The pulse generation circuit described. 3. A frequency divider circuit whose clock is the output signal of the comparison circuit, and an AND circuit whose input signals are the output signals of the flip-flops in each stage of the frequency divider circuit and the signal corresponding to the output signal of the comparison circuit. 3. The pulse generating circuit according to claim 1, wherein said AND circuit is configured to detect a cycle completion time and generate a switching signal for said frequency designation code.