JPH03211633A - Control system for computer - Google Patents

Abstract

PURPOSE:To securely judge whether a computer normally is operated or not by outputting a requiring signal to the computer at every prescribed period and monitoring a response signal from the computer for the requiring signal. CONSTITUTION:A frequency divider 4 frequency-divides a reference signal A from an oscillation circuit 1, generates the requiring signal B and outputs it to the computer 5. When the requiring signal B is inputted, the computer 5 is programmed in such a manner that it outputs the response signal C to a decision circuit 6 within prescribed time. The decision circuit 6 inputs the reference signal A from the oscillation circuit 1, the requiring signal B from the frequency divider 4 and the response signal C from the computer 5 and decides whether the computer 5 is normally operated or abnormally operated. Thus, the abnormality of a computer system and the malfunction of the program can securely be detected, and the computer system with high reliability can be obtained.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention relates to a computer control method for detecting system abnormalities and program malfunctions in a computer. 119836
There was something disclosed in the issue.

FIG. 4 is a block diagram showing the system configuration of the conventional computer control method described above, and FIG. 5 is a waveform diagram (timing chart) of each part for explaining its operation. In FIG. 4, 41 is a computer, 42 is an oscillator, 43 is a computer abnormality detection counter, 44 is a comparator, 45 is a setter,
46 is a differential circuit.

In the computer control method having the above configuration, when the computer 41 is operating normally, the counter clear signal 47 is output from the computer 41 to the computer abnormality detection counter 43 at each final stage of the program. As shown in the figure, the computer abnormality detection counter 43 is cleared at the cycle of the program execution time ts. Therefore, since the count value of the computer abnormality detection counter 43 does not become larger than the abnormality detection setting value tr set in the setting device 45, the comparator 44 does not output the computer abnormality detection signal 51 to the differentiating circuit 46, and the differentiating circuit 46 The computer reset signal 52 is not output to the computer 41.

On the other hand, when an abnormality occurs in the computer 41, a counter clear signal 47 is sent from the computer 41 to the computer abnormality detection counter 43.
cannot be output, so the count value of the computer abnormality detection counter 43 is equal to the abnormality detection setting value tr set in the setting device 45.
becomes larger, and the comparator 44 receives the computer abnormality detection signal 51.
is output to the differentiating circuit 46, and the differentiating circuit 46 outputs it to the computer 4.
1, a computer reset signal 52 is output, and the computer 41 is reset.

[Problem to be solved by the invention]

However, in the conventional computer control method described above, only the time interval between outputs of the counter clear signal 47 from the computer 41 is monitored, so the counter clear signal 47 may be periodically output due to system abnormalities or program malfunctions. In the case where the computer 41 is abnormal, the computer 41 does not receive the computer reset signal 52 even though the computer 41 is abnormal.
There was a problem that the file was not output.

The present invention has been made in view of the above points, and an object of the present invention is to provide a J control method for a computer that eliminates the above problems and can reliably determine whether the computer is operating normally or abnormally. .

[Means to solve the problem]

In order to solve the above problems, the present invention outputs a request signal to a computer at predetermined intervals, and when a response signal is output from the computer within a predetermined period in response to the request signal, the computer operates normally. The control circuit is configured to determine that the computer is operating abnormally when the computer does not output a response signal in response to the request signal within the predetermined period, and the control circuit also determines that the computer is operating abnormally. The system is configured to output a computer reset signal to the computer if it is determined that the computer is operating abnormally.

[Effect]

By configuring the computer control system as described above, a request signal is output to the computer at predetermined intervals, and an abnormality or abnormality is detected depending on whether there is a response signal from the computer between the door and the door to this request signal. Since normality is determined, unlike the conventional computer control method described above, which monitors the time interval between outputs of counter clear signals from the computer, it is possible to reliably detect computer system abnormalities and program malfunctions, making it reliable. This makes it possible to realize a highly flexible computer system.

〔Example〕

Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing the circuit configuration of a computer control system according to the present invention. In the figure, 1 is an oscillation circuit, 2 is a resistor, 3 is a capacitor, 4 is a frequency divider, 5 is a calculator, and 6
is a judgment circuit.

The oscillation circuit 1, the resistor 2, and the capacitor 3 are connected to the frequency divider 4.
It can be output to the judgment circuit 6. The frequency divider 4 divides the reference signal A of the oscillation circuit 1 into 1/8 period in this embodiment.
(converted into a cycle-width signal) to create a request signal B, which is output to the computer 5 and the determination circuit 6. Calculator 5 is frequency divider 4
It is programmed to output a response signal C to the determination circuit 6 within a predetermined period of time when the request signal B is input.

The determination circuit 6 inputs the reference signal A from the oscillation circuit 1, the request signal B from the frequency divider 4, and the response signal C from the computer 5, and determines whether the computer 5 is operating normally or abnormally. is determined, and a reset signal R is output to the computer 5.

Next, the operation of the control method of the computer will be explained using FIG. 3. As shown in the diagram, the relationship between the reference signal A and the request signal B is as shown in the figure.
is output. The computer 5 includes a program that inputs the falling edge of the request signal B as an interrupt or the like, and a program that outputs the response signal C while the request signal B is being output. The determination circuit 6 determines whether the computer 5 is operating normally or abnormally based on the reference signal A, request signal B, and response signal C as described above. This determination method is as shown in FIG.
3 (b), when the response signal C is not output while the request signal B is being output, and ( As shown in c), when the request signal B is not output, the response signal C
There is a method of determining that the computer 5 is operating abnormally when this is output. When it is determined from the result that the computer 5 is operating abnormally, the determination circuit 6 outputs a reset signal R to the computer 5.

Furthermore, as mentioned above, by externally connecting the resistor 2 and capacitor 3 that constitute the oscillation circuit, the resistance value of the resistor 2 and the capacitance of the capacitor 3 can be arbitrarily selected, that is, the constant can be arbitrarily selected. However, since the oscillation period can be set arbitrarily, the output time of the request signal B can be set arbitrarily.

FIG. 2 is an example of a circuit embodying the determination circuit 6 described above. In the same figure, 20, 21, and 24 are D-type flip-flop circuits (hereinafter referred to as 'latch circuits'), 22
．． 28 is an AND circuit, 27.29 is an OR circuit, 23.2
6 is an inverter circuit, and 25 is a delay circuit.

The latch circuit 20 has the power supply (+SV) as the D input, and by inputting the response signal C from the computer 5 at CK, the Q output signal S is "L" in the initial state (based on the CLR signal).
”, the Q output signal S was “H”, but due to the rising signal C of the response signal C, the Q output signal S was “H” and the Q output signal S8 was “L”.
It is a circuit that changes to ”.

Latch circuit 21, AND circuit 22, and inverter circuit 23
converts the Q output signal SI of the latch circuit 20 and the request signal B to A
The signal S, which is ANDed by the ND circuit 22, is used as the D input,
By inputting a signal obtained by inverting the reference signal A by the inverter circuit 23, the output signal S of the AND circuit 22 is latched by the falling signal of the reference signal A, and the output signal S of the AND circuit 22 is latched.
This is a circuit that outputs an output signal OI.

The latch circuit 24 uses the Q output signal S2 signal of the latch circuit 20 as a p input, and inputs the request signal B at a high CK level, thereby latching the d output signal S by the rising signal of the request signal B, and latches the d output signal S, and the Q output signal 0. ．． This is a circuit that outputs as .

The delay circuit 25 and the inverter circuit 26 are circuits that create a reset signal R by delaying the reference signal A with the delay circuit 25 and inverting it with the inverter circuit 26. Note that the delay circuit 25 delays the Q output signal S8 of the latch circuit 21 and the Q output signal 0. This is to wait for the output.

The OR circuit 27 and the AND circuit 2B are connected to the Q of the latch circuit 21.
The output signal O and the Q output signal O1 of the latch circuit 24 are logically summed by the OR circuit 27 (when the computer 5 operates abnormally, either one becomes "H"), and based on the result, the AND circuit 28 determines whether to open or close the gate. This circuit determines whether or not to output the output signal of the inverter circuit 26.

The OR circuit 29 logically adds the output signals of the inverter circuit 23 and the delay circuit 25.
This is a circuit that creates CLR signals for latch circuits 20, 21, and 24.

By making the determination circuit 6 have the above-mentioned circuit configuration, the determination circuit 6 makes a determination based on the period of the reference signal A. That is, the reference signal A
The latch circuit 20 determines the input of the response signal C during the “H” period of
At the falling position of reference signal A (request signal B
(starts up almost simultaneously), the latch circuit 21 and the latch circuit 24 determine whether the computer 5 is normal or abnormal, and the reference signal A
During the L'' period, the computer 5 outputs a reset signal R in the event of an abnormality, and the latch circuit 20, latch circuit 21, and latch circuit 2
Clear 4.

Next, the operation of the determination circuit 6 having the above circuit configuration in each state will be explained.

First, a case where request signal B and response signal C are not input will be described.

When the response signal C is not input enough, the Q output signal S1 of the latch circuit 20 becomes "L", the Q output signal S becomes "H", and the Q output signal S is logically multiplied with the request signal B by the AND circuit 22. .Here, the Q output signal S1 is 'L'' and the request signal B
is “H”, so the output signal S of the AND circuit 22 is “L”
becomes.

Next, as the reference signal A falls, the latch L path 21
(7) No. 011 0. Since the output signal S is "L", the AND circuit 22 (7) becomes "L", and the latch circuit 24
request signal B is not input (and Q output signal 0. is “
As a result, the output of the OR circuit 27 becomes 0.
Q output signal 〇 is “L” Q output signal 0! is “L”, so it becomes “L”, and the output of the inverter circuit 26 is AND
Banned by Kai Liu 28, reset believer R on computer 5
is not output.

Second, an agreement in which request signal B and response signal C are input will be explained.

latch circuit 2o by inputting response signal C. pressure signal S
1 is “L”, the Q output signal S is “L”, and further Q
The output signal s1 is ANDed with the request signal B by the AND circuit 22, and since the Q output signal S is "H" and the request signal B is "L", the output signal S of the AND circuit 22 becomes "L". Next, due to the falling of the reference signal A, the Q of the latch circuit 21 is
The output signal O1 is such that the output signal S of the AND circuit 22 is “L”.
”, so it becomes “L”, and the rising edge of request signal B 1
becomes. As a result, as in the first case, Q output signal 01 is "L". is L", the output of the inverter circuit 26 is prohibited by the AND circuit 28, and the output of the computer 5
There is no way to output the reset signal R.

Thirdly, the case where the request signal B is inputted by λ and the response signal C is not inputted will be explained.

Since the response signal C cannot be inputted, the Q output signal S of the latch circuit 20 becomes "L" and the output signal S becomes "H".
The Q output signal S is ANDed with the request signal B by the AND circuit 22, so that the Q output signal S is "L" and the request signal B is "
Since the output signal S of the AND circuit 22 is "L", the output signal S of the AND circuit 22 is "L".
becomes. Next, with the fall of the reference signal A, the Q output signal 0□ of the latch circuit 21 becomes "L" because the output signal S8 of the AND circuit 22 is "L", and with the rise of the request signal B, the Q output signal 0□ of the latch circuit 21 becomes "L". of.

The output signal O3 is the ζ output signal S! of the latch circuit 2o. is H
", so it becomes "L". As a result, the output 0. of the OR circuit 27 is "L" for the Q output signal oI, and "L" for the output signal oI of the OR circuit 27.
Since it is H'', it becomes atH'', and the output of the inverter circuit 26 is output from the AND circuit 28, and a reset signal R is output to the computer 5.

Fourth, a case will be described in which the request signal B is not input and the response signal C is input.

Due to the input of the response signal C, the latch circuit 20 (7) Q output signal S becomes "H". becomes “L”,
Further, the Q output signal s1 is logically multiplied with the request signal B by the AND circuit 22, and the Q output signal S is "H2" and the request signal B is "H".
"Therefore, the output signal Sj of the AND circuit 22 becomes H". Next, as the reference signal A falls, the latch circuit 2
1 Q output signal O8 is the output signal S of the AND circuit 22,
is “H”, so it goes “H”, and since the request signal B is not input to the latch circuit 24, the Q output signal 0 goes “L”.
As a result, the output of the OR circuit 27 is such that the Q output signal 01 is "L" and the Q output signal 0. is “L”, so
sH'', the output of the inverter circuit 26 is output from the AND circuit 28, and a reset signal R is output to the computer 5.

Note that the computer control method of the present invention is not limited to the above-mentioned embodiment, and the operating state of the computer can be determined by outputting a request signal to the computer and checking the signal from the computer in response to this request signal. There are no particular restrictions on the specific configuration as long as the configuration includes a determination circuit that does this.

〔Effect of the invention〕

As explained above, according to the present invention, the request signal output means outputs a request signal to the computer at predetermined intervals, and the response signal from the computer to the request signal is monitored to check whether the computer is operating normally. Since it is determined whether there is an abnormal operation, it is possible to detect an abnormality in the computer at an early stage, and to provide an excellent effect that a highly reliable computer control method can be provided.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a circuit configuration of a computer control system of the present invention, FIG. 2 is a diagram showing an example of a circuit embodying the determination circuit of FIG. 1, and FIG. 3(a). (b) and (c) are waveform diagrams (timing charts) of various parts showing the operation of the circuits shown in Figs. 1 and 2, respectively. Fig. 4 is a block diagram showing the circuit configuration of the conventional computer control method. Figure 5 is a waveform diagram (timing chart) of each part showing the operation of the circuit in Figure 4.
5... Calculator, 6... Judgment circuit, 21...
Latch circuit, 22...AND circuit, 23...Inverter circuit, 24...Latch circuit, 25...
Delay circuit, 26... Inverter circuit, 27...
OR circuit, 28...AND circuit, 29...OR
circuit.

Claims (1)

[Scope of Claims] Reference signal generation means for outputting a reference signal at every predetermined period; and request signal output means for dividing the frequency of the reference signal from the reference signal generation means and outputting a request signal to a computer at every predetermined period. and determining means for determining whether or not the computer is abnormal based on a reference signal from the reference signal generating means, a request signal from the request signal outputting means, and a response signal from the computer to the request signal. . A control method for a computer, comprising means for outputting a reset signal to the computer when the determining means determines that the computer is abnormal.